JP2008245257A - Template pulse generating circuit, communication device, and communication method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a template pulse generating circuit suitable for low power consumption in pulse communication, a communication device, and its communication method. <P>SOLUTION: The template pulse generating circuit 820 continuously generates template pulses in a synchronization acquisition mode in which synchronization acquisition (823) is performed in accordance with a control signal CTL from a system controller 830 at detection of a received pulse, and after synchronization acquisition is substantially established template pulse generating states are switched and template pulses are intermittently outputed in a synchronization tracking mode, thereby using continuous template pulses at the beginning of pulse communication to quickly establish synchronization acquisition, and thereafter, intermittently outputting template pulses, leading to a reduction in power consumption. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a template pulse generation circuit, a communication device, and a communication method that are well suited for UWB (Ultra Wide Band) communication, and in particular, a template pulse generation circuit, a communication device, and a power saving method in a receiving system, And a communication method.

A very wide band communication method using very short pulses in UWB communication is also called UWB impulse radio (UWB-IR) communication. In the UWB-IR system, modulation / demodulation is possible only by time axis operation not based on conventional modulation, and it is expected that simplification of the circuit and low power consumption can be expected (for example, see Patent Document 1, Patent Document 2, etc.). .
Further, in a receiving device that receives a transmission signal composed of a pulse signal train, a pulse generator generates a template pulse having a generation interval that is substantially the same as a transmission pulse, and a position of the template pulse generated at a predetermined interval by a phase shift unit. It has been proposed to phase-shift, correlate each template pulse that has been phase-shifted by a correlator, and a received pulse, and perform synchronization acquisition for a received signal based on the correlation result (Patent Document 3).

Furthermore, a proposal has been made to control power consumption by controlling the generation position of the template pulse and stopping the reception circuit during a period when the reception pulse does not arrive (Patent Document 4).
Japanese translation of PCT publication No. 2004-528776 (paragraph 0035 to paragraph 0040, FIG. 5) JP-T-2005-517355 (paragraphs 0015 to 0020, FIG. 2) Japanese Patent Laying-Open No. 2004-241927 (paragraphs 0025 to 0028, FIG. 1) Japanese Patent Laying-Open No. 2005-217899 (paragraphs 0023 to 0026, FIG. 1)

As described above, in UWB communication, communication with low power consumption is realized due to its characteristics. However, in the proposals described in Patent Documents 1 to 3 above, it exceeds the normal level by applying this communication method. No other proposal has been made regarding the recognition of technical issues such as reducing power consumption and, consequently, the means for solving such technical issues.
Patent Document 4 discloses a proposal to reduce power consumption. However, in the technique described in this document, the presence of a pulse itself is searched from a state in which the timing of an incoming pulse is unknown, and synchronization is performed. It is not possible to save power in the process of capturing.

In other words, in the process of acquiring the synchronization by searching for the existence of the pulse itself, the timing of the incoming pulse is searched while sequentially shifting the phase of the template pulse generated on the receiving side. Thus, the technical problem that power consumption also increases remains in Patent Document 4.
The present invention has been made in view of the above situation, and an object thereof is to provide a template pulse generation circuit, a communication device, and a communication method suitable for power saving in pulse communication.

In order to solve the above problems, the present application proposes the following technologies.
(1) A template pulse generation circuit for generating a template pulse used for detection of a received pulse in pulse communication,
The template pulse is generated in any one of a continuous output mode in which the template pulse is continuously output according to the supplied control signal and an intermittent output mode in which the template pulse is intermittently output. A template pulse generation circuit comprising an output mode switching circuit for switching an output mode.

  In the template pulse generation circuit of (1) above, for example, a continuous output mode in which a control signal is supplied from a system controller or the like provided in a communication apparatus and a template pulse is continuously output by an output mode switching circuit is intermittently generated. Since the output mode can be switched so that the template pulse is output according to any output mode of the intermittent output mode that outputs the signal, the continuous template pulse is used promptly in the synchronous acquisition mode at the beginning of the pulse communication. By establishing synchronization acquisition and then intermittently outputting a template pulse, the overall power consumption can be greatly reduced.

(2) a continuous pulse generating circuit for continuously generating the template pulse;
An intermittent pulse generation circuit for intermittently generating the template pulse,
The template pulse generating circuit according to (1), wherein the output mode switching circuit switches the output mode by selecting an output of one of the continuous pulse generating circuit and the intermittent pulse generating circuit. .

  In the template pulse generation circuit of (2), in particular, in the template pulse generation circuit of (1), a continuous pulse generation circuit that continuously outputs template pulses and an intermittent pulse generation circuit that outputs intermittently are provided. Since any one of these outputs is switched and output by the output mode switching circuit, the continuous output mode and the intermittent output mode of the template pulse are switched by the output mode switching circuit having a very simple configuration.

  (3) a mode variable pulse generating circuit for generating the template pulse continuously or intermittently in response to an oscillation mode switching signal supplied to a mode control signal input terminal, and the output mode switching circuit includes the oscillation mode switching signal; Is supplied to the mode control signal input terminal of the mode variable pulse generating circuit. (1) The template pulse generating circuit according to (1).

  In the template pulse generating circuit of (3), the operation mode of the mode variable pulse generating circuit is switched by the oscillation mode switching signal from the output mode switching circuit, particularly in the template pulse generating circuit of (1). The output mode of these template pulses is switched by a small circuit that does not have a separate circuit corresponding to the intermittent output mode.

(4) The mode variable pulse generation circuit includes a multi-stage inverter circuit unit including a cascade connection of a plurality of inverters, and a plurality of switching elements whose opening / closing is controlled by the output of the inverter of the multi-stage inverter circuit unit. Including a predetermined frequency output terminal connected to the positive electrode side or the negative electrode side of the power source according to the opening and closing of the plurality of switching elements, and a frequency higher than the clock pulse signal supplied to the input terminal of the first-stage inverter of the inverters A pulse generation logic circuit part capable of generating the template pulse, which is a high intermittent pulse signal,
The multi-stage inverter circuit unit feeds back the output of the inverter at the final stage in a predetermined multi-stage part to the input terminal of the first stage of the multi-stage part according to the oscillation mode switching signal supplied to the mode control signal input terminal It is configured to switch the intermittent loop of the feedback loop circuit that forms the ring oscillation circuit by connecting the closed loop,
(3) The template pulse generation circuit according to (3), wherein the pulse generation logic circuit section generates the template pulse continuously or intermittently in accordance with the intermittent switching of the feedback loop circuit.

  In the template pulse generation circuit of (4) above, particularly in the template pulse generation circuit of (3), the mode variable pulse generation circuit includes a multi-stage inverter circuit unit including a cascade connection of a plurality of inverters, and the multi-stage inverter. Including a plurality of switching elements whose opening and closing is controlled by the output of the inverter of each stage of the circuit unit, and selectively connecting a predetermined output terminal to the positive electrode side or the negative electrode side of the power supply in accordance with the opening and closing of the plurality of switching elements A pulse generation logic circuit unit that can generate a template pulse that is an intermittent pulse signal having a frequency higher than that of the clock pulse signal supplied to the input terminal of the first-stage inverter among the inverters of each stage. This is a template that has a higher frequency than the clock pulse signal from this pulse generation logic circuit It is possible to output the pulse.

In addition, the multi-stage inverter circuit unit forms a closed loop that feeds back the output of the final stage inverter of the predetermined multi-stage part to the first stage input terminal of the part according to the oscillation mode switching signal supplied to the mode control signal input terminal. The pulse generation logic circuit unit generates the template pulse continuously or intermittently according to the switching of the feedback loop circuit for switching the intermittent loop of the feedback loop circuit. Is configured to do. For this reason, a template pulse having a high frequency as described above can be output by selecting a continuous output mode or an intermittent output mode by a small circuit.
Furthermore, it is possible to reduce the difference in phase jitter and frequency deviation between the oscillation in the continuous output mode and the oscillation in the intermittent output mode due to the variation in the characteristics of the circuit elements of each inverter.

(5) The template pulse generation circuit according to (4), wherein the multistage inverter circuit section is configured by cascade connection of a plurality of differential inverter circuits.
In the template pulse generation circuit of (5) above, in particular, in the template pulse generation circuit of (4), two (differential) templates having opposite polarities in either the continuous output mode or the intermittent output mode described above Pulses can be obtained simultaneously.

(6) a counter that counts oscillation pulses by the ring oscillation circuit;
Any one of (4) to (5), wherein the output mode switching circuit is configured to define a duration of the template pulse in the intermittent output mode according to a count value of the counter. A template pulse generation circuit.
In the template pulse generation circuit of (6) above, in the intermittent pulse output mode in particular in the template pulse generation circuit of any one of (4) to (5) above, by the counting operation by the counter that counts the oscillation pulses by the ring oscillation circuit. The duration of each intermittent pulse at is controlled with high precision by measuring the number of pulses.
Furthermore, it is possible to reduce the difference in phase jitter and frequency deviation between the oscillation in the continuous output mode and the oscillation in the intermittent output mode due to the variation in the characteristics of the circuit elements of each inverter.

  (7) The multi-stage inverter circuit unit generates the pulse of the I-phase system by opening and closing the corresponding switching element of the pulse generation logic circuit unit of the corresponding I-phase system according to the output of the even-numbered inverter. The template pulse of the I phase is generated from the output terminal of the logic circuit unit, and the corresponding switching element of the pulse generation logic circuit unit of the corresponding Q phase system is opened and closed by the output of the odd-numbered inverter. The template pulse generation circuit according to (6), wherein the template pulse generation circuit is configured to generate the Q-phase template pulse from an output terminal of a Q-phase system pulse generation logic circuit unit.

  In the template pulse generating circuit of (7) above, in particular, in the template pulse generating circuit of (6), the I-phase driven by the output of each inverter of even stages among the inverters of each stage constituting the multi-stage inverter circuit section. A template pulse in the continuous output mode or the intermittent output mode is obtained from the pulse generation logic circuit section of the system, and the template pulse of the system of I phase can be applied to the detection of the I phase system of the received signal, A template pulse in the continuous output mode or the intermittent output mode is obtained from the pulse generation logic circuit portion of the Q-phase system driven by the output of each of the odd-numbered inverters among the inverters of each stage constituting the multi-stage inverter circuit portion. The template pulse of the Q phase system can be applied to the detection for the Q phase system.

(8) The template pulse generation circuit according to (6), wherein the ring oscillation circuit is configured such that an oscillation frequency can be adjusted according to a supplied frequency control signal.
In the template pulse generation circuit of (8) above, the ring oscillation circuit is particularly adapted to the synchronous detection method because the oscillation frequency of the ring oscillation circuit is adjusted according to the supplied frequency control signal in the template pulse generation circuit of (6) above. Thus, a template pulse generating circuit is realized.

(9) The template pulse generation circuit according to any one of (1) to (8) above,
A detection circuit that performs detection based on a correlation between an output pulse of the template pulse generation circuit and a reception pulse;
The template pulse generating circuit is operated in the continuous output mode in the synchronous acquisition mode for performing synchronous acquisition upon detection of the received pulse, and the template pulse generating circuit is operated in the intermittent output mode when the synchronous acquisition is established. And a system controller for supplying a control signal for switching an operation mode to the template pulse generation circuit.

  In the communication device of (9) above, the template pulse generation circuit operates in the continuous output mode in the synchronous acquisition mode in which the synchronous acquisition is performed when detecting the received pulse by the control signal from the system controller, and the synchronous acquisition is substantially established. Sometimes the template pulse generation circuit operates in the intermittent output mode, so that the template pulse can be generated continuously at the beginning of pulse communication to establish synchronization acquisition in a short time, and thereafter the template pulse generation circuit is intermittent. Since it is switched to the output mode, power consumption is reduced.

(10) The template pulse generation circuit according to any one of (7) to (8) above, an I-phase pulse multiplier that multiplies the received pulse by the I-phase template pulse of the template pulse generation circuit,
A Q-phase pulse multiplier that multiplies the received pulse with the Q-phase template pulse of the template pulse generation circuit;
An I-phase envelope detection processing circuit that performs envelope detection processing on an I-phase multiplication output pulse that is an output of the I-phase pulse multiplier;
A Q-phase envelope detection processing circuit for performing envelope detection processing on a Q-phase multiplication output pulse that is an output of the Q-phase pulse multiplier;
An envelope signal adding circuit for adding and synthesizing an I-phase envelope signal that is an output of the I-phase envelope detection processing circuit and a Q-phase envelope signal that is an output of the Q-phase envelope detection processing circuit;
A synchronization acquisition processing unit that performs synchronization acquisition based on a composite envelope signal that is an output of the envelope signal addition circuit;
A pulse position tracking processing unit that performs a pulse position tracking process based on the composite envelope signal;
The template pulse generation circuit is operated in the continuous output mode in the synchronization acquisition mode in which the synchronization acquisition processing unit performs synchronization acquisition, and the template pulse generation circuit is operated in the intermittent output mode when the synchronization acquisition is established. A system controller for supplying a control signal for switching the operation mode to the template pulse generation circuit;
A communication apparatus comprising:

In the communication device of the above (10), the I synergy obtained by multiplying the I-phase template pulse and the Q-phase template pulse of the template pulse generation circuit by the received pulse by the I-phase pulse multiplier and the Q-phase pulse multiplier, respectively. The calculated force pulse and the Q-phase multiplication output pulse are respectively subjected to envelope detection processing by the I-phase envelope detection processing circuit and the Q-phase envelope detection processing circuit to obtain an I-phase envelope signal and a Q-phase envelope signal. The phase envelope signal and the Q phase envelope signal are added and synthesized by an envelope signal adding circuit to obtain a combined envelope signal.
Based on this composite envelope signal, the synchronization acquisition processing unit performs synchronization acquisition, and then the pulse position tracking processing unit performs pulse position tracking processing to obtain a baseband signal (data) that is a detection output related to the received pulse signal. obtain.

In this case, under the control of the system controller, the template pulse generation circuit is operated in the continuous output mode in the synchronization acquisition mode in which the synchronization acquisition processing unit performs synchronization acquisition, and when the synchronization acquisition is substantially established, the template pulse generation circuit is operated in the intermittent output mode. The operation mode is switched to operate.
Therefore, it is possible to continuously generate a template pulse at the beginning of pulse communication and establish synchronization acquisition in a short time, and thereafter, the template pulse generation circuit is switched to the intermittent output mode, thereby reducing power consumption. The

(11) The I-phase envelope detection processing circuit includes an I-phase pulse square circuit that squares the I-phase multiplication output pulse,
(10) The communication apparatus according to (10), wherein the Q-phase envelope detection processing circuit includes a Q-phase pulse square circuit that squares the Q-phase multiplication output pulse.
In the communication device (11), in particular, in the communication device of (10), each square value of the I-phase multiplication output pulse and the Q-phase multiplication output pulse obtained by the I-phase pulse square circuit and the Q-phase pulse square circuit, that is, I Synchronization acquisition and pulse position tracking processing are performed based on the combined value of the values corresponding to the envelope detection of the phase and Q phase pulses.

(12) The I-phase envelope detection processing circuit includes an I-phase pulse rectifier circuit that rectifies the I-phase multiplication output pulse,
The communication device according to (10), wherein the Q-phase envelope detection processing circuit includes a Q-phase pulse rectification circuit that rectifies the Q-phase multiplication output pulse.
In the communication device (12), in particular, in the communication device of (10), each rectified value of the I-phase multiplication output pulse and the Q-phase multiplication output pulse obtained by the I-phase pulse rectification circuit and the Q-phase pulse rectification circuit, that is, I Synchronization acquisition and pulse position tracking processing are performed based on the combined value of the values corresponding to the envelope detection of the phase and Q phase pulses.

(13) The pulse position tracking processing unit is configured to compare a pulse position based on a comparison between an integral value of a phase advance DLL circuit that performs a phase advance process for advancing a phase and an integral value of a phase delay DLL circuit that performs a phase lag process for delaying a phase. The communication apparatus according to any one of (10) to (12), wherein the demodulated output is obtained based on an output of an in-phase DLL circuit that performs a follow-up process and performs an in-phase process for maintaining a phase.
In the communication device (13), in particular, in the communication devices (10) to (12), the phase advance DLL circuit among the outputs of the phase advance DLL circuit, the in-phase DLL circuit, and the slow phase DLL circuit of the pulse position tracking processing unit. The pulse position tracking process is performed based on the comparison of the integral values of the outputs of the slow-phase DLL circuit, and the demodulated output is obtained based on the output of the in-phase DLL circuit.

(14) The synchronization acquisition processing unit is configured to include a synchronous detection function unit that performs a frequency adjustment process for matching frequencies together with a phase synchronization process of the template pulse and the received pulse ( The communication apparatus according to any one of 10) to (13).
In the above communication device (14), particularly in the communication devices of (10) to (13), the frequency adjustment that matches the frequency together with the phase synchronization processing of the template pulse and the input pulse in the synchronous detection function unit of the synchronous acquisition processing unit. Processing is performed, and a highly accurate detection processing result is obtained.

(15) The communication device according to any one of (9) to (14), further including a storage function unit that stores pulse position information acquired when the synchronization acquisition is established.
In the above communication device (15), in particular, in the communication devices of (9) to (14), the pulse position information acquired when the synchronization acquisition is established is held in the storage function unit. A clock pulse is supplied to the template pulse generation circuit so as to be synchronized with the timing based on the pulse position information, and the detection processing for the received pulse can be performed using the template pulse whose phase is appropriately adjusted in this way.

(16) The system controller supplies a clock pulse used for operating the template pulse generation circuit in the intermittent output mode to the template pulse generation circuit in accordance with the pulse position information stored in the storage function unit. (15) The communication apparatus characterized by the above-mentioned.
In the communication device of (16), particularly in the communication device of (15), the system controller supplies a clock pulse to the template pulse generation circuit so as to synchronize with the timing based on the pulse position information held in the storage function unit. Therefore, the detection process for the received pulse can be performed using the template pulse whose phase is appropriately adjusted.

(17) Provided with a power supply control unit for controlling the supply of operating power,
The communication according to any one of (9) to (16), wherein the system controller controls the power supply control unit to partially stop power supply during a period when the received pulse has not arrived. apparatus.
In the communication device of the above (17), in particular, in the communication device of any one of (9) to (16), by partially stopping the operation power supply of the communication device during the period when the received pulse has not arrived. Thus, unnecessary standby power consumption can be minimized.

(18) A continuous output mode in which a template pulse used for detection of a received pulse is continuously generated is selected during a period of synchronization acquisition in pulse communication, and the template pulse is intermittently generated during the period after the establishment of the synchronization acquisition. A communication method characterized by switching to a discontinuous output mode generated in
In the communication method of (18), in the synchronization acquisition mode at the beginning of the pulse communication, synchronization acquisition is quickly established using a continuous template pulse, and then the template pulse is output intermittently. The power consumption can be greatly reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings to be referred to below, for the sake of convenience, the main part that is the subject of the description is exaggerated as appropriate, and other than the main part is appropriately simplified or omitted.
FIG. 1 is a waveform diagram of an output signal (template pulse) representing a characteristic action of a pulse generation circuit as an embodiment of the present invention applied to the communication method of the present invention. In the present invention, as shown in the drawing, in the synchronous acquisition mode in which the pulse position search operation is performed at the beginning of the pulse communication, the synchronous acquisition is quickly established using the continuous template pulse by the continuous output mode of the pulse generation circuit.
After synchronization acquisition is almost established, it shifts to synchronous tracking mode where pulse position tracking operation (precise pulse position adjustment) is performed, and the template pulse is output intermittently by the intermittent output mode of the pulse generation circuit. The overall power consumption can be greatly reduced.

FIG. 2 is a diagram showing a pulse generation circuit as one embodiment of the present invention for generating the template pulse shown in FIG.
FIG. 2A is a block diagram showing an outline of a pulse generation circuit as one embodiment of the present invention, and FIG. 2B is a more detailed configuration example of the block diagram of FIG. FIG.
As shown in FIG. 2A, a pulse generation circuit according to an embodiment of the present invention includes a continuous pulse generation circuit 210 that continuously outputs pulses and an intermittent pulse generation circuit that intermittently outputs pulses. 220 and are provided, one of these outputs is output as a template pulse P ₀ is switched by the output mode switching circuit 230 which performs switching operation in response to the supplied control signal CTL.

Therefore, the continuous output mode and the intermittent output mode of the template pulse are switched by the output mode switching circuit 230 having a very simple configuration.
Note that the continuous pulse generation circuit 210 is a self-running circuit configured by, for example, a ring oscillation circuit, and the intermittent pulse generation circuit 220 is operated by being supplied with a clock pulse CTL from the outside. Details will be described with reference to FIG.

In FIG. 2B, the continuous pulse generation circuit 210 has three stages of cascade connections of inverters 211, 212 and 213, and the output of the last stage inverter 213 is supplied to the input of the first stage inverter 211. In this way, a ring oscillation circuit is configured.
A continuous template pulse P ₀ as shown in FIG. 1 as a continuous output mode (synchronization acquisition mode in the operation of a communication apparatus to which this circuit is applied) is generated at the pulse output terminal 2110 of the continuous pulse generation circuit 210. The

The intermittent pulse generation circuit 220 includes a multi-stage inverter circuit unit 2210 configured by connecting 9 stages of inverters 221 to 229, and a plurality of inverters whose opening and closing are controlled by outputs of the inverters of each stage of the multi-stage inverter circuit unit 2210. Of the first stage of the inverters in each stage by selectively connecting a predetermined output terminal to the positive side V1 or the negative side V2 of the power source in accordance with the opening and closing of the plurality of switching elements. And a pulse generation logic circuit unit 2220 for obtaining a template pulse P ₀ which is a pulse signal having a frequency higher than that of the clock pulse CLK supplied to the end.

The pulse generation logic circuit unit 2220 includes P-channel MOS transistors 230, 231, 234, 235, 238, 239, 242, 243, 246 as switching elements, and N-channel MOS transistors 232, 233, 236, 237, 240, 241, 244, 245 are connected as shown in the figure, and a positive power source V 1 and a negative power source V 2 are connected as shown.
The pulse D ₀ supplied to the input terminal of the first stage inverter 221 of the multi-stage inverter circuit unit 2210 propagates through the inverters while being delayed by time td for each stage of the inverter and the logic is inverted, and a delay signal is output from each stage. Is output.

That is, the signal CLK (clock pulse D ₀ ) applied to the input terminal of the first-stage inverter 221 is positive logic, and the i-th stage of the multi-stage inverter circuit unit 2210 is:
If k is an integer and the negative logic of the signal is expressed by prefixing the signal name with X,
When i = 2k-1, XD _2k-1
When i = 2k D _2k
Is output.

N-channel MOS transistors 233 and 232 are turned on when the output XD ₁ of the first-stage inverter 221 and the output D ₂ of the second-stage inverter are high, and connect the pulse output terminal 2230 to the potential level V1 of the positive-side power supply. .
Next, when the output D ₂ of the second-stage inverter and the output XD ₃ of the third-stage inverter are low (that is, both the negative logic of D ₂ and D ₃ are high) of the P-channel MOS transistors 230 and 231 respectively. It conducts and connects the pulse output terminal 2230 to the potential level V2 of the negative power supply.

Similarly, the N-channel MOS transistors 236, 237, 240, 241, 244 and 245 are respectively provided when the output XD _{2k-1 of the 2k-1} stage inverter and the output D _2k of the 2k stage inverter are high, that is, XD _2k- Conducting when the logical product of ₁ and D _2k is true, the pulse output terminal 2230 is connected to the potential level V1 of the power supply on the positive side.
Next, the P-channel MOS transistors 234, 235, 238, 239, 242 and 243 are respectively connected when the output D _2k of the 2k-th stage inverter and the output XD _{2k + 1} of the 2k + 1-th stage inverter are low, that is, negate D _2k When the logical product of the logic XD _2k and the logic D _{2k + 1} , which is the negative logic of XD _{2k + 1} , is true, the pulse output terminal 2230 is connected to the potential level V 2 of the negative power supply.

With the above operation, the intermittent template pulse P as shown in FIG. 1 as the intermittent output mode (synchronous tracking mode in the operation of the communication apparatus to which this circuit is applied) is applied to the pulse output terminal 2230 of the pulse generation logic circuit unit 2220. ₀ can be generated.
An output mode switching circuit in which a continuous template pulse appearing at the pulse output terminal 2110 of the continuous pulse generation circuit 210 or an intermittent template pulse appearing at the pulse output terminal 2230 of the pulse generation logic circuit unit 2220 responds to the control signal CTL. 230 is output as a template pulse P ₀ in the continuous output mode or the intermittent output mode.

FIG. 3 is a diagram showing a pulse generation circuit as another embodiment of the present invention for generating the template pulse shown in FIG.
FIG. 3A is a block diagram showing an outline of a pulse generation circuit as one embodiment of the present invention, and FIG. 3B is a more detailed configuration example of the block diagram of FIG. FIG. 3 (c) is a timing chart of signals at various parts of the circuit of FIG. 3 (b).

The template pulse generation circuit shown in FIG. 3A generates a template pulse P ₀ continuously or intermittently in accordance with a control signal CTL as an oscillation mode switching signal supplied to its own mode control signal input terminal 301. A variable oscillation circuit 300 is provided, and an output mode switching circuit 302 is configured to supply an oscillation mode switching signal CTL to a mode control signal input terminal 301 of the mode variable oscillation circuit 300.

  As shown in FIG. 3B, details of the mode variable oscillation circuit 300 include inverters 321, 322, a NAND circuit 323 that functions as an inverter when a positive voltage is applied to one input terminal, and , A multi-stage inverter circuit unit 3210 configured by cascade connection of 9-stage inverters (or functional units as inverters) 324 to 329, and a plurality of inverters whose opening / closing is controlled by outputs of the inverters of each stage of the multi-stage inverter circuit unit 3210 Of the first stage of the inverters in each stage by selectively connecting a predetermined output terminal to the positive side V1 or the negative side V2 of the power source in accordance with the opening and closing of the plurality of switching elements. A template pulse that is a pulse signal having a higher frequency than the clock pulse CLK supplied to the end A pulse generating logic circuit portion 3220 to obtain configured to include a.

  The pulse generation logic circuit unit 3220 includes P-channel MOS transistors 330, 331, 334, 335, 338, 339, 342, 343, and 346 as switching elements, and N-channel MOS transistors 332, 333, 336, 337, 340, 341, 344, and 345 are connected as shown, and a positive power source V1 and a negative power source V2 are connected as shown.

The pulse generation logic circuit unit 3220 itself has the same configuration as the pulse generation logic circuit unit 2220 described with reference to FIG. 2B, and outputs from the inverters of each stage of the multi-stage inverter circuit unit 3210. Supplied to generate an intermittent template pulse P ₀ similar to that of FIG.
On the other hand, the multi-stage inverter circuit unit 3210 has a NAND circuit 323 that functions as an inverter when a positive voltage is applied to one input terminal, inverters 324 and 325 following the subsequent stage, and an output of the inverter 325 as a NAND circuit A feedback loop circuit 351 is provided so as to connect a closed loop to be fed back to the other input terminal of H.323, and a ring oscillation circuit 350 having substantially three stages of inverters is configured.
The feedback loop circuit 351 is provided with a switching circuit 352 that switches between switching of the feedback loop circuit 351 in response to a control signal CTL as an oscillation mode switching signal.

The operation of the template pulse generation circuit of FIG. 3B will be described below with reference to FIG. 3C, which is a timing chart of signals at various parts of the circuit of FIG.
As described above, the ring oscillation circuit 350 having substantially three stages of inverters has a clock pulse when the switching circuit 352 is connected to the contact b side and the feedback loop circuit 351 is closed in response to the oscillation mode switching signal CTL. In order to fix CLK to the high level, the input terminal of the NAND circuit 323 at the point D ₂ is held at the high level, the NAND circuit 323 functions as an inverter, and the ring oscillation circuit 350 performs the oscillation operation.

  The period of the output waveform of the ring oscillation circuit 350 is 6 × Td, where Td is the delay of the inverter at each stage. As described above, the ring oscillation circuit 350 includes a NAND circuit 323 and inverters 324 and 325 following the subsequent stage in the middle of the multi-stage inverter circuit unit 3210 configured by cascade connection of nine stages of inverters by the feedback loop circuit 351. When configured and the feedback loop circuit 351 is closed, it functions as a ring oscillation circuit.

For this reason, the ring oscillation circuit 350 outputs a 3-cycle pulse waveform and stops. However, since the output of the next inverter is fed back through the feedback loop circuit 351 just at the third pulse, the next pulse is output without interruption and the pulse waveform is repeated.
That is, when the switching circuit 352 is connected to the contact b side, the feedback loop circuit 351 is closed, and the clock pulse CLK is fixed to the high level, the mode variable oscillation circuit 300 operates in the continuous output mode.

On the other hand, when the switching circuit 352 is connected to the contact a side in accordance with the oscillation mode switching signal CTL, one input terminal of the NAND circuit 323 is fixed to a high level, and in this case, the NAND circuit 323 also functions as an inverter. As a result, a pulse is output at the timing of the rising edge of the clock pulse CLK.
The template pulse generation circuit of FIG. 3B uses the same inverter for continuous oscillation and intermittent pulse oscillation as compared with the circuit of FIG. 3A, and thus is caused by variations in circuit element characteristics of each inverter. There is an advantage that the difference in phase jitter and the frequency deviation between the oscillation in the continuous output mode and the oscillation in the intermittent output mode can be reduced.

FIG. 4 is a diagram showing a pulse generating circuit as still another embodiment of the present invention for generating the template pulse shown in FIG.
The pulse generation circuit 400 of FIG. 4 is different from the above-described one in that a template pulse having mutually inverted phases is output as a pair of differential outputs.
That is, a differential signal forming circuit 401 is provided as a first-stage circuit that receives a clock pulse CLK, and an input terminal on the upper side of the NAND circuit 402 is connected to a non-inverting output terminal of the differential signal forming circuit 401, The input terminal on the upper side of the NOR circuit 403 in the figure is connected to the inverting output terminal. The NAND circuit 402 and the NOR circuit 403 function as inverters when the clock pulse CLK is fixed at a high level, as in the example described above.

  On the output side of the NAND circuit 402 and the NOR circuit 403, there is provided a differential inverter 404 having the outputs of the NAND circuit 402 and the NOR circuit 303 as one input and the other input. The differential inverter 405 that receives the pair of outputs of the differential inverter 404 is connected in cascade, and thereafter, similarly, the differential inverters 406, 407, 408, 409, 410, and 411 are connected in cascade in the order described above. Yes.

  Of the cascade connection of these differential inverters, a closed loop is formed such that the other output of the differential inverter 406 is fed back to the other input terminal of the NAND circuit 402 through the feedback loop 451, and the NAND circuit 402, the differential inverter is connected. A ring oscillation circuit 461 is formed by cascade connection of 404, 405, and 406. In the feedback loop 451, a switching circuit 452 for switching the on / off state of the feedback loop 451 is interposed.

  Further, a closed loop is formed such that one output of the differential inverter 406 is fed back to the other input terminal of the NOR circuit 403 through the feedback loop 453, and the NOR circuit 403 and the differential inverters 404, 405, 406 are connected in cascade. A ring oscillation circuit 462 is configured. In the feedback loop 452, a switching circuit 454 for switching the on / off state of the feedback loop 452 is inserted.

The outputs of the inverters in the cascade connection of the differential inverters including the NAND circuit 402 and the NOR circuit 403 functioning as the first-stage differential inverter drive the corresponding switching element by the output to drive one of the differential output pulses. Supplied to the first pulse generation logic circuit unit 4221 for obtaining the template pulse P ₀₁ from the system and the second pulse generation logic circuit unit 4222 for obtaining the template pulse P ₀₂ from the other system of the differential output pulses The first pulse generation logic circuit unit 4221 and the second pulse generation logic circuit unit 4222 each function in substantially the same manner as described with reference to FIG.
That is, in the continuous output mode in which the template pulse is output continuously, the NAND circuit 402 and the NOR circuit 403 function as inverters by fixing the CLK to high level with the two switching circuits 452 and 453 on the b side. A ring oscillator having a waveform period of 8 * Td is configured.

Since the first pulse generation logic circuit unit 4221 and the second pulse generation logic circuit unit 4222 output a modulated waveform of 4 cycles, the template pulses P ₀₁ and P ₀₁ in the continuous output mode without interruption as a result. Continue to generate ₀₂ .
On the other hand, by connecting the two switching circuits 452 and 453 to the a side, the first pulse generation logic circuit unit 4221 and the second pulse generation logic circuit unit 4222 have the timing of the rising edge of the clock pulse CLK. The template pulses P ₀₁ and P ₀₂ in the intermittent output mode are output.

  FIG. 5 is a diagram showing a pulse generation circuit 500 as still another embodiment of the present invention. The differential inverter 501 and the differential inverter 502 are connected in cascade, and the feedback loop 551 for feeding back the other output of the differential inverter 502 at the rear stage to one input terminal of the differential inverter 501 at the front stage and one of the differential inverters 502 A feedback loop 552 that feeds back the output to the other input terminal of the differential inverter 501 in the previous stage is provided, and each ring oscillation circuit 561 and ring oscillation circuit 562 are configured.

  A plurality of switching elements whose opening / closing is controlled by respective outputs of the differential inverter 501 and the differential inverter 502 are included, and a predetermined output terminal is sequentially selected to the positive side or the negative side of the power source according to the opening / closing of the switching elements. Are provided with a first pulse generation logic circuit unit 5221 and a second pulse generation logic circuit unit 5222 that obtain a template pulse at the output end.

  Each output of ring oscillation circuit 561 and ring oscillation circuit 562 is supplied to counter 510 and counted, and the oscillation operation of ring oscillation circuit 561 and ring oscillation circuit 562 and the counting operation of counter 510 are controlled. Control is performed from an output mode switching circuit 520 that performs an output mode switching operation in accordance with the supply mode of the clock pulse CLK and the count of the counter 510 in response to the signal CTL.

That is, the output mode switching circuit 520 continuously oscillates the ring oscillation circuit 561 and the ring oscillation circuit 562 without depending on the count state of the counter 510 when the continuous output mode is set by the control signal CTL. Make it. In response to this continuous oscillation operation, template pulses P ₀₁ and P ₀₂ in the continuous output mode are obtained from the first pulse generation logic circuit unit 5221 and the second pulse generation logic circuit unit 5222.

When the intermittent output mode is set by the control signal CTL, the counter 510 is kept in a reset state until the rising edge of the clock pulse CLK is input, and the ring oscillation circuit 561 and the ring oscillation circuit 562 are also stopped.
When the rising edge of the clock pulse CLK is input, the reset of the counter 510 is canceled and the ring oscillation circuit 561 and the ring oscillation circuit 562 are operated simultaneously.

When the counter 510 counts a predetermined number of output pulses from the ring oscillation circuit 561 and the ring oscillation circuit 562, the counter 510 notifies the output mode switching circuit 520 of the result, and the output mode switching circuit 520 that has received the notification notifies the ring oscillation circuit. 561 and ring oscillation circuit 562 are stopped and counter 510 is reset.
By repeating the counting and resetting of the output pulses of the ring oscillation circuit 561 and the ring oscillation circuit 562 by the counter 510 as described above, intermittent output is performed from the first pulse generation logic circuit unit 5221 and the second pulse generation logic circuit unit 5222. Each template pulse P ₀₁ and P _{02 of the} mode is obtained.

In this case, the duration and phase of each template pulse are controlled with high accuracy by measuring the duration of each intermittent pulse in the intermittent output mode by the count operation by the counter 510 by the number of pulses.
Furthermore, it is possible to reduce the difference in phase jitter and the frequency deviation between the oscillation in the continuous output mode and the oscillation in the intermittent output mode due to the variation in the characteristics of the circuit elements of the differential inverters 501 and 502.
In this embodiment, a differential pulse is generated using a differential inverter, but a single-ended configuration can also be adopted.

  FIG. 6 is a diagram showing a pulse generation circuit as still another embodiment of the present invention. The difference between the template pulse generation circuit 600 in FIG. 6 and the template pulse generation circuit 500 in FIG. 5 described above is that the circuit in FIG. 5 obtains a template pulse as a pair of differential outputs. The circuit of FIG. 6 is configured so that a template pulse of an I-phase system and a template pulse of a Q-phase system can be obtained simultaneously.

A plurality of switching elements whose opening / closing is controlled by the output pulse of one of the output terminals of each of the odd-numbered (first and third) differential inverters 601 and 603 among the cascaded differential inverters 601 to 604; First to obtain a Q-phase positive (+) template pulse P ₀₁ at the output terminal by selectively connecting a predetermined output terminal to the positive electrode side or the negative electrode side of the power source sequentially according to the opening and closing of the plurality of switching elements. The pulse generation logic circuit 6221 and the other output terminals of the differential inverters 601 and 603 are similarly switched and driven to obtain the Q-phase negative (−) template pulse P ₀₂ at the output terminal. A second pulse generation logic circuit unit 6222 is provided.

Further, among the cascaded differential inverters 601 to 604, a plurality of differential inverters 602 and 604 whose opening / closing is controlled by an output pulse of one of the output terminals of the even-numbered (second and fourth) differential inverters 602 and 604. A template pulse P on the positive side (+) of the I phase is connected to the output terminal by selectively connecting a predetermined output terminal to the positive electrode side or the negative electrode side of the power source sequentially according to opening and closing of the plurality of switching elements. The third pulse generation logic circuit unit 6223 for obtaining ₀₃ and the output pulse at the other output terminal of the above-described differential inverters 602 and 604 are similarly switched and driven, and the I-phase negative (−) template at the output terminal A fourth pulse generation logic circuit unit 6224 for obtaining the pulse P ₀₄ is provided.

  Each force output from the ring oscillation circuit 661 and the ring oscillation circuit 662 is supplied to the counter 610 and counted, and the oscillation operation of the ring oscillation circuit 661 and the ring oscillation circuit 662 and the counting operation of the counter 610 are: Control is performed from an output mode switching circuit 620 that performs an output mode switching operation in accordance with the mode of supply of clock pulse CLK and the count of counter 610 in response to control signal CTL.

That is, when the continuous output mode is set by the control signal CTL, the output mode switching circuit 620 continuously oscillates the ring oscillation circuit 661 and the ring oscillation circuit 662 without depending on the count state of the counter 610. .
A template which is the above-described Q-phase differential pulse output in the continuous output mode from the first pulse generation logic circuit unit 6221 and the second pulse generation logic circuit unit 6222 in accordance with the continuous oscillation operation of the ring oscillation circuit. Pulses P ₀₁ and P ₀₂ are obtained, and the template pulse P which is the above-described I-phase differential pulse output in the continuous output mode from the third pulse generation logic circuit unit 6223 and the fourth pulse generation logic circuit unit 6224 ₀₃ and _P04 are obtained.

When the intermittent output mode is set by the control signal CTL, the counter 610 is kept in the reset state until the rising edge of the clock pulse CLK is input, and the ring oscillation circuit 661 and the ring oscillation circuit 662 are also stopped.
When the rising edge of the clock pulse CLK is input, the reset of the counter 610 is released and the ring oscillation circuit 661 and the ring oscillation circuit 662 are operated simultaneously.
When the counter 610 counts a predetermined number of output pulses from the ring oscillation circuit 661 and the ring oscillation circuit 662, the counter 610 notifies the output mode switching circuit 620 of the result, and the output mode switching circuit 620 that has received the notification counts the ring oscillation circuit. 661 and the ring oscillation circuit 662 are stopped, and the counter 610 is reset.

By repeating the counting and resetting of the output pulses of the ring oscillation circuit 661 and the ring oscillation circuit 662 by the counter 610 as described above, intermittent output is performed from the first pulse generation logic circuit unit 6221 and the second pulse generation logic circuit unit 6222. The template pulses P ₀₁ and P _{02 which} are the above-described Q-phase differential pulse outputs in the mode are obtained, and in the intermittent output mode from the third pulse generation logic circuit unit 6223 and the fourth pulse generation logic circuit unit 6224 The template pulses P ₀₃ and P _{04 which} are the above-mentioned I-phase differential pulse outputs are obtained.

In this case, the duration and phase of each template pulse are controlled with high accuracy by measuring the duration of each intermittent pulse in the intermittent output mode by the count operation by the counter 610 by the number of pulses.
Furthermore, it is possible to reduce the difference in phase jitter and the frequency deviation between the oscillation in the continuous output mode and the oscillation in the intermittent output mode due to the variation in the characteristics of the circuit elements of the differential inverters 601 to 604.

  FIG. 7 is a diagram showing a pulse generation circuit as still another embodiment of the present invention. The difference between the template pulse generation circuit 700 of FIG. 7 and the template pulse generation circuit 600 of FIG. 6 described above is that a pair of differential outputs of the template pulse of the I phase system and the template pulse of the Q phase system in FIG. In addition to the configuration capable of simultaneously obtaining the pair of differential outputs, the frequency deviation can be corrected in accordance with the control signal CTL2 as the frequency adjustment signal.

In this embodiment, in particular, the cascade connection circuit of the differential inverters 701 to 704 is configured as a variable delay type differential inverter in which the differential inverters 701 to 704 at each stage can adjust the delay time according to the control signal. The control signal CTL2 as a frequency adjustment signal is supplied to the differential inverters 701 to 704, respectively.
Therefore, the oscillation frequencies of the ring oscillation circuit 761 and the ring oscillation circuit 762 can be adjusted by the control signal CTL2.

FIG. 8 is a diagram showing a configuration of a communication apparatus as an embodiment of the present invention. A receiving device (including a case where it is a receiving function unit of a communication device) 810 that performs detection processing on a modulated pulse signal received by including any one of the template pulse generation circuits described above, and a pulse signal to the receiving device 810 And a transmission device (including a case where it is a transmission function unit of the communication device) 850, the communication system is configured.
However, there is no problem in thinking that the system of FIG. 8 represents an integrated communication apparatus 800 that includes the reception function unit 810 and the transmission function unit 850.

  The transmission function unit 850 forms a modulated pulse using the data as the baseband signal supplied from the system controller 870 and the clock pulse CLK in the modulation pulse generation circuit 860 and transmits the modulated pulse from the antenna 851. A RAM 871 is connected to the system controller 870 and used for temporary storage of data to be transmitted and data in the signal processing process, etc., and a ROM 872 is connected to information related to a predetermined communication protocol, parameters used for calculation, etc. Is held.

In the reception function unit 810, the transmitted pulse signal is received by the antenna 811, the received signal is amplified by the LNA (low noise amplifier) 813 through the BPF (bandpass filter) 812, and supplied to the multiplier 821.
The multiplier 821 is supplied with a template pulse from any one of the template pulse generation circuits 820 described with reference to FIGS. 1 to 7 and is multiplied by the received pulse signal amplified by the LNA 813.

The multiplied signal is subjected to detection processing by a detection circuit 822, and synchronization acquisition processing is performed in a synchronization acquisition processing unit 823 based on the output of the detection circuit 822. As a result, when synchronization acquisition is substantially established, the pulse position tracking processing unit 824 performs pulse position tracking processing based on the output of the detection circuit 822.
A system controller 830 that manages the operation of each unit for communication in the communication apparatus 800 (its reception function unit 810) is provided, and the system controller 830 performs synchronization acquisition processing and pulse position tracking processing in the above-described synchronization acquisition processing unit 823. The progress status of the pulse position tracking process in the unit 824 and the management of the processing timing are executed.

  That is, the system controller 830 operates the template pulse generation circuit 820 in the above-described continuous output mode in the synchronization acquisition mode in which synchronization acquisition is performed when detecting a received pulse, and when the synchronization acquisition is substantially established, A control signal CTL for switching the operation mode so as to operate in the intermittent output mode, and a clock pulse CLK serving as a basis for timing of the operation of each unit are supplied to the template pulse generation circuit 820.

For this reason, template pulses can be generated continuously at the beginning of pulse communication and synchronization acquisition can be established in a short time. After that, the template pulse generation circuit is switched to the intermittent output mode, reducing power consumption. Is done.
The system controller 830 is connected to the RAM 831 and used for temporary storage of demodulated data and data in the signal processing process. The ROM 832 is connected to the system controller 830 for information and computation on a predetermined communication protocol. The parameters used for are stored. The demodulated data temporarily stored in the RAM 831 can be provided to the user in the form of sound or image by an appropriate method as required.

  A reception circuit power supply control unit 833 that controls the power supply for operation of each part of the reception function unit 810 is provided to operate under the control of the system controller 830. The system controller 830 controls the reception circuit power supply control unit 833. Since the supply of operating power to the communication device 800 (reception function unit 810) is partially stopped during the period when the received pulse has not arrived, unnecessary standby power can be minimized.

FIG. 9 is a diagram illustrating a configuration of a communication device according to another embodiment of the present invention.
FIG. 10 is a timing chart regarding signals of the respective units of the communication apparatus of FIG.
A signal received by the antenna 901 is amplified by an LNA (low noise amplifier) 903 through a BPF (bandpass filter) 902 (“received waveform” in the upper part of FIG. 10), and the I-phase system multiplier 910 and the Q-phase system This is supplied to the multiplier 920.
Multipliers 910 and 920 include I-phase and Q-phase templates from template pulse generation circuit 930 that outputs two-phase template pulses of I-phase and Q-phase as described with reference to FIG. 6 or FIG. Each pulse is supplied and multiplied by the received pulse amplified by the LNA 903.

The I-phase multiplication output pulse and Q as a result of the multiplication as described above by the I-phase system multiplier (I-phase pulse multiplier) 910 and the Q-phase system multiplier (Q-phase pulse multiplier) 920, respectively. The phase multiplication output pulse includes a square circuit 911 as an I-phase envelope detection processing circuit and a square circuit as a Q-phase envelope detection processing circuit for performing envelope detection processing on the I-phase multiplication output pulse and the Q-phase multiplication output pulse, respectively. 921 is applied to the square calculation, and a value corresponding to the envelope of those pulses is obtained. Then, both the obtained values are added and synthesized by the envelope signal adding circuit 940, and synthesized as a result. An envelope signal (“I ² + Q ² waveform” in the lower part of FIG. 10) is obtained.
Based on the composite envelope signal, the synchronization acquisition processing unit 941 performs synchronization acquisition, and then the pulse position tracking processing unit 942 performs pulse position tracking processing to detect a baseband signal (data) that is a detection output related to the received pulse signal. )

In this case, the template acquisition circuit 930 is operated in the continuous output mode in the synchronization acquisition mode in which the synchronization acquisition processing unit 941 performs synchronization acquisition by the control signal CTL and the clock pulse CLK from the system controller 950, and synchronization acquisition is substantially established. Sometimes, the operation mode is switched so that the template pulse generation circuit 930 is operated in the intermittent output mode (“template pulse waveform” in the middle of FIG. 10).
Therefore, it is possible to continuously generate a template pulse at the beginning of pulse communication and establish synchronization acquisition in a short time, and thereafter, the template pulse generation circuit is switched to the intermittent output mode, thereby reducing power consumption. The

FIG. 11 is a diagram showing a configuration of a communication apparatus as still another embodiment of the present invention.
The embodiment shown in FIG. 11 differs from the embodiment shown in FIG. 9 in that, in the embodiment shown in FIG. 9, I-phase multiplication output pulse and Q-phase multiplication output pulse are individually subjected to envelope detection processing. The square circuit 911 is applied to the phase envelope detection process, and the square circuit 921 is applied to the Q phase envelope detection process to apply the square calculation separately to each other. In the embodiment of FIG. Rectification circuits 1111 and 1121 are applied to the I-phase envelope detection process and the Q-phase envelope detection process as means for performing the line detection process.

A signal received by the antenna 1101 is amplified by the LNA 1103 through the BPF 1102 and supplied to the I-phase system multiplier 1110 and the Q-phase system multiplier 1120.
Multipliers 1110 and 1120 include I-phase and Q-phase templates from template pulse generation circuit 1130 that outputs two-phase template pulses of I-phase and Q-phase as described with reference to FIG. Each pulse is supplied and multiplied by the received pulse amplified by the LNA 1103.

  The I-phase multiplication output pulse and the Q-phase multiplication output pulse resulting from the multiplication by the I-phase system multiplier 1110 and the Q-phase system multiplier 1120 as described above are the I-phase multiplication output pulse and Q-phase multiplication pulse, respectively. The phase multiplication output pulses are supplied to and rectified by a rectifier circuit 1111 as an I-phase envelope detection processing circuit and a rectifier circuit 1121 as a Q-phase envelope detection processing circuit for performing envelope detection processing separately for each phase (like half-wave rectification) The value corresponding to the envelope of these pulses is obtained, and then the obtained both values are added by the envelope signal adding circuit 1140. As a result, a composite envelope signal is obtained.

Based on the composite envelope signal, the synchronization acquisition processing unit 1141 performs synchronization acquisition, and then the pulse position tracking processing unit 1142 performs pulse position tracking processing to detect a baseband signal (data) that is a detection output related to the received pulse signal. )
In this case, the template acquisition circuit 1130 is operated in the continuous output mode in the synchronization acquisition mode in which the synchronization acquisition processing unit 1141 performs synchronization acquisition by the control signal CTL and the clock pulse CLK from the system controller 1150, and synchronization acquisition is substantially established. Sometimes the operation mode is switched so that the template pulse generation circuit 1130 operates in the intermittent output mode.
Therefore, it is possible to continuously generate a template pulse at the beginning of pulse communication and establish synchronization acquisition in a short time, and thereafter, the template pulse generation circuit is switched to the intermittent output mode, thereby reducing power consumption. The

FIG. 12 is a diagram illustrating a communication device similar to the communication device of FIG. 9 with a specific configuration example of the pulse position tracking processing unit.
In FIG. 12, the reference numerals of the respective parts are assigned again, and the layout of the synchronization acquisition processing unit and the pulse position tracking processing unit is shown with their upper and lower arrangements reversed.
A signal received by the antenna 1201 is amplified by the LNA 1203 through the BPF 1202 and supplied to the I-phase system multiplier 1210 and the Q-phase system multiplier 1220.
Multipliers 1210 and 1220 include I-phase and Q-phase templates from template pulse generation circuit 1230 that outputs two-phase template pulses of I-phase and Q-phase as described with reference to FIG. 6 or FIG. Each pulse is supplied and multiplied by the received pulse amplified by the LNA 1203.

  The I-phase multiplication output pulse and the Q-phase multiplication output pulse resulting from the multiplications in the I-phase system multiplier 1210 and the Q-phase system multiplier 1220 as described above are the I-phase multiplication output pulse and Q-phase multiplication pulse, respectively. The phase multiplication output pulses are supplied to a square circuit 1211 as an I-phase envelope detection processing circuit for performing envelope detection processing on each of them and a square circuit 1221 as a Q-phase envelope detection processing circuit, and are subjected to square calculation, and these pulses are supplied. Then, a value corresponding to the envelope curve of the envelope is obtained, and both of the obtained values are added and synthesized by the envelope signal addition circuit 1240, resulting in a synthesized envelope signal.

Based on the composite envelope signal, the synchronization acquisition processing unit 1241 performs synchronization acquisition, and then the pulse position tracking processing unit 1242 illustrated in FIG. A baseband signal (data) is obtained.
In the configuration described above, the pulse position tracking processing unit 1242 calculates the integration time in the integration processing unit 10 that integrates the input signal, the sampling hold processing unit 20 that samples and holds the output of the integration processing unit 10, and the integration time in the integration processing unit 10. An integration time control unit 30 controlled by a control signal from the system controller 1250 and an addition circuit 40 that adds and synthesizes the outputs of a plurality of systems of the sampling hold processing unit 20 and supplies the outputs to the system controller 1250. Lock loop).

  In other words, the pulse position tracking processing unit 1242 performs a DLL circuit that individually performs a phase advance process (Early) that advances the phase of the input, an in-phase process (Current) that maintains the phase, and a late phase process (Late) that delays the phase. A phase advance DLL circuit (integrator 11 + sampling hold circuit 21), an in-phase DLL circuit (integrator 12 + sampling hold circuit 22), and a slow phase DLL circuit (integrator 13 + sampling hold circuit 23). A pulse position tracking process is performed based on the output of the adder circuit 40, which is a comparison of the integrated values of the circuit and the slow-phase DLL circuit, and a demodulated output is obtained based on the output of the in-phase DLL circuit (integrator 12 + sampling hold circuit 22). It is configured as follows.

In this case, the template acquisition circuit 1230 is operated in the continuous output mode in the synchronization acquisition mode in which the synchronization acquisition processing unit 1241 performs synchronization acquisition by the control signal CTL and the clock pulse CLK from the system controller 1250, and synchronization acquisition is substantially established. Sometimes the operation mode is switched so that the template pulse generation circuit 1230 is operated in the intermittent output mode.
Therefore, it is possible to continuously generate a template pulse at the beginning of pulse communication and establish synchronization acquisition in a short time, and thereafter, the template pulse generation circuit is switched to the intermittent output mode, thereby reducing power consumption. The

FIG. 13 is a diagram showing a configuration of a communication apparatus as still another embodiment of the present invention.
Further, FIG. 14 is a timing chart regarding signals of respective units of the communication apparatus of FIG.
The embodiment of FIG. 13 differs from the embodiment of FIG. 9 (details are FIG. 12) and FIG. 11 and the like in the embodiment of FIG. 9 and FIG. When the envelope detection processing is performed on the pulse, in the embodiment of FIG. 13, synchronous detection is performed.
The signal received by the antenna 1301 is amplified by the LNA 1303 through the BPF 1302 (“received waveform” in FIG. 14) and supplied to the I-phase system multiplier 1310 and the Q-phase system multiplier 1320.

Multipliers 1310 and 1320 receive I-phase and Q-phase template pulses from template pulse generation circuit 1330 that outputs two-phase template pulses of I-phase and Q-phase as described with reference to FIG. The received pulse amplified by the LNA 1303 is multiplied by each.
The I-phase multiplication output pulse and the Q-phase multiplication output pulse as the result of multiplication by the I-phase system multiplier 1310 and the Q-phase system multiplier 1320 as described above are the I-phase multiplication output pulse and Q-phase multiplication pulse, respectively. The high frequency component is removed from the phase multiplication output pulse separately through LPF (low-pass filter) 1311 and LPF 1312, and through the corresponding rectifier circuit 1313 and rectifier circuit 1314 (FIG. 14 “I-phase rectification detection waveform” “Q-phase rectification detection waveform”). ”), And is supplied to the synchronization acquisition processing and frequency deviation detector 1341.

In addition to the synchronization acquisition process as described above, the synchronization acquisition process and frequency deviation detection unit 1341 detects the frequency deviation between the input pulse and the template pulse, and supplies the detection result to the system controller 1350.
The system controller 1350 generates the control signal CTL2 as the frequency adjustment signal described above with reference to FIG. 7 based on the frequency deviation, and relates to the template pulse output from the template pulse generation circuit 1330 according to the control signal CTL2. The frequency deviation is corrected.

The synchronization acquisition processing and frequency deviation detection unit 1341 performs synchronization acquisition, and then the pulse position tracking processing unit 1342 performs pulse position tracking processing to obtain a baseband signal (data) that is a detection output related to the received pulse signal.
In this case, the control signal CTL1 from the system controller 1350 causes the template pulse generation circuit 1330 to operate in the continuous output mode in the synchronous acquisition mode in which the synchronous acquisition process and the frequency deviation detector 1341 perform synchronous acquisition, and the synchronous acquisition is substantially established. Sometimes the operation mode is switched so that the template pulse generation circuit 1330 is operated in the intermittent output mode.
Therefore, it is possible to continuously generate a template pulse at the beginning of pulse communication and establish synchronization acquisition in a short time, and thereafter, the template pulse generation circuit is switched to the intermittent output mode (see “template pulse” in FIG. 14). Waveform "), power consumption is reduced.

FIG. 15 is a diagram showing a configuration of a communication apparatus as still another embodiment of the present invention.
The embodiment of FIG. 15 differs from the embodiment of FIG. 13 in that, in the embodiment of FIG. 13, the synchronous acquisition processing and the frequency deviation detector 1341 are operated to perform synchronous detection. In this embodiment, synchronous detection is performed using the Costas loop 1542 (multiplier 150 + LPF 151).

The signal received by the antenna 1501 is amplified by the LNA 1503 through the BPF 1502 and supplied to the I-phase system multiplier 1510 and the Q-phase system multiplier 1520.
Multipliers 1510 and 1520 receive I-phase and Q-phase template pulses from template pulse generation circuit 1530 that outputs two-phase template pulses of I-phase and Q-phase as described with reference to FIG. The received pulse amplified by the LNA 1503 is multiplied by each.

  The I-phase multiplication output pulse and the Q-phase multiplication output pulse resulting from the multiplication by the I-phase system multiplier 1510 and the Q-phase system multiplier 1520 as described above are the I-phase multiplication output pulse and Q-phase multiplication pulse, respectively. The phase-multiplied output pulse is supplied to a synchronous acquisition processing unit 1541 and a Costas loop 1542 after high frequency components are removed through an LPF (low-pass filter) 1511 and an LPF 1512 separately.

  The Costas loop 1542 includes a multiplier 150 that multiplies both outputs of the LPF 1511 and the LPF 1512 and an LPF 151 that removes a high-frequency component from the output of the multiplier 150. When the established state is reached, the frequency deviation between the input pulse and the template pulse is detected, and a control signal CTL2 as a frequency adjustment signal is generated based on the detection result, and the template pulse is generated according to the control signal CTL2. The frequency deviation of the template pulse output from the generation circuit 1530 is corrected.

The demodulated data obtained through the Costas loop 1542 is supplied to the system controller 1550, and the demodulated data is stored in the RAM 1551 connected to the system controller 1550.
In this case, the control signal CTL1 from the system controller 1550 causes the template pulse generation circuit 1530 to operate in the continuous output mode in the synchronization acquisition mode where the synchronization acquisition processing unit 1541 performs synchronization acquisition, and generates the template pulse when synchronization acquisition is substantially established. The operation mode is switched to operate the circuit 1530 in the intermittent output mode.
Therefore, it is possible to continuously generate a template pulse at the beginning of pulse communication and establish synchronization acquisition in a short time, and thereafter, the template pulse generation circuit is switched to the intermittent output mode, thereby reducing power consumption. The

FIG. 16 is a diagram illustrating a configuration of a communication apparatus as still another embodiment of the present invention.
The embodiment of FIG. 16 differs from the embodiment of FIG. 9 (details of which are shown in FIG. 12) and FIG. 11 in that the I-phase multiplication output pulse and the Q-phase multiplication output in the embodiment of FIGS. When the envelope detection processing is performed on the pulse, in the embodiment of FIG. 16, synchronous detection is performed.

A signal received by the antenna 1601 is amplified by an LNA (low noise amplifier) 1603 through a BPF 1602 and supplied to an I-phase system multiplier 1610 and a Q-phase system multiplier 1620.
Multipliers 1610 and 1620 receive I-phase and Q-phase template pulses from template pulse generation circuit 1630 that outputs two-phase template pulses of I-phase and Q-phase as described with reference to FIG. The received pulse amplified by the LNA 1603 is multiplied by each.

The I-phase multiplication output pulse and the Q-phase multiplication output pulse resulting from the multiplication by the I-phase system multiplier 1610 and the Q-phase system multiplier 1620 as described above are the I-phase multiplication output pulse and Q-phase multiplication pulse, respectively. The phase multiplication output pulses are supplied to a square circuit 1611 as an I-phase envelope detection processing circuit and a square circuit 1621 as a Q-phase envelope detection processing circuit for separately performing an envelope detection process, respectively, and subjected to square calculation, and these pulses are supplied. Then, a value corresponding to the envelope of the envelope is obtained, and then both of the obtained values are added and synthesized by the envelope signal adding circuit 1640, resulting in a synthesized envelope signal (ie, I ² + Q ² ). .

On the other hand, the I-phase multiplication output pulse and the Q-phase multiplication output pulse, which are the outputs of the I-phase system multiplier 1610 and the Q-phase system multiplier 1620, respectively correspond to their corresponding LPF (low-pass filter) 1612 and The high frequency component is removed through the LPF 1622 and then supplied to the pulse position tracking processing unit 1642.
Based on the composite envelope signal described above, synchronization acquisition processing unit 1641 performs synchronization acquisition, and then pulse position tracking processing unit 1642 performs pulse position tracking processing based on the I-phase multiplication output pulse and Q-phase multiplication output pulse. Thus, a baseband signal (data) which is a detection output related to the received pulse signal is obtained.

  In this case, the template acquisition circuit 1630 is operated in the continuous output mode in the synchronization acquisition mode in which the synchronization acquisition processing unit 1641 performs synchronization acquisition by the control signal CTL1 and the clock pulse CLK from the system controller 1650, and synchronization acquisition is substantially established. Sometimes the operation mode is switched so that the template pulse generation circuit 1630 is operated in the intermittent output mode.

Further, the frequency of the template pulse in the template pulse generating circuit 1630 is adjusted based on the control signal CTL2 issued from the system controller 1650 based on the output of the pulse position tracking processing unit 1642.
In this embodiment, as described above, it is possible to continuously generate a template pulse at the beginning of pulse communication and establish synchronization acquisition in a short time, and thereafter, the template pulse generation circuit enters the intermittent output mode. Since it is switched, power consumption is reduced.

The technical idea of the present invention described above is based on the selection of the continuous output mode in which the template pulse used for detection of the received pulse is continuously generated during the period of synchronization acquisition in pulse communication. The period can be summarized as a communication method characterized by switching to an intermittent output mode in which template pulses are generated intermittently.
In this communication method, synchronization acquisition is quickly established using a continuous template pulse in the synchronization acquisition mode at the beginning of pulse communication, and then the template pulse is output intermittently, so that the overall power consumption Can be greatly reduced.

It is a wave form diagram of the output signal of the pulse generation circuit as an embodiment of the present invention applied to the communication method of the present invention. It is a figure showing the pulse generation circuit as one embodiment of this invention. It is a figure showing the pulse generation circuit as other embodiment of this invention. It is a figure showing the pulse generation circuit as further another embodiment of this invention. It is a figure showing the pulse generation circuit as further another embodiment of this invention. It is a figure showing the pulse generation circuit as further another embodiment of this invention. It is a figure showing the pulse generation circuit as further another embodiment of this invention. It is a figure showing the structure of the communication apparatus as embodiment of this invention. It is a figure showing the structure of the communication apparatus as other embodiment of this invention. It is a timing chart regarding the signal of each part of the communication apparatus of FIG. It is a figure showing the structure of the communication apparatus as further another embodiment of this invention. It is a figure which shows the detailed structural example of the communication apparatus of FIG. It is a figure showing the structure of the communication apparatus as further another embodiment of this invention. It is a timing chart regarding the signal of each part of the communication apparatus of FIG. It is a figure showing the structure of the communication apparatus as further another embodiment of this invention. It is a figure showing the structure of the communication apparatus as further another embodiment of this invention.

Explanation of symbols

  200, 400, 500, 600, 700 ... Template pulse generation circuit 210 ... Continuous pulse generation times 220 ... Intermittent pulse generation circuit 230, 520, 620, 720 ... Output mode switching circuit 300 ... Mode variable oscillation circuit 352, 452, 453 ... Switching circuit 820, 930, 1130, 1230, 1330, 1530, 1630 ... Template pulse generation circuit 830, 950, 1150, 1250, 1350, 1550, 1650 ... System controller 823, 941, 1141, 1241, 1541, 1641 ... Synchronous acquisition Processing unit 824, 942, 1141, 1242, 1642 ... Pulse position tracking processing unit 833, 953, 1153, 1253, 1353, 1553, 1653 ... Reception circuit power supply control unit

Claims (18)

A template pulse generation circuit for generating a template pulse used for detection of a received pulse in pulse communication,
The template pulse is generated in any one of a continuous output mode in which the template pulse is continuously output according to the supplied control signal and an intermittent output mode in which the template pulse is intermittently output. A template pulse generation circuit comprising an output mode switching circuit for switching an output mode. A continuous pulse generating circuit for continuously generating the template pulse;
An intermittent pulse generation circuit for intermittently generating the template pulse,
2. The template pulse according to claim 1, wherein the output mode switching circuit switches the output mode by selecting an output of one of the continuous pulse generation circuit and the intermittent pulse generation circuit. Generation circuit. A mode variable pulse generating circuit for generating the template pulse continuously or intermittently according to an oscillation mode switching signal supplied to a mode control signal input terminal;
The template pulse generation circuit according to claim 1, wherein the output mode switching circuit supplies the oscillation mode switching signal to the mode control signal input terminal of the mode variable pulse generation circuit. The mode variable pulse generation circuit includes a multi-stage inverter circuit unit configured to include a cascade connection of a plurality of inverters, and a plurality of switching elements whose opening / closing is controlled by the output of the inverter of the multi-stage inverter circuit unit, Intermittent higher frequency than the clock pulse signal supplied to the input terminal of the first-stage inverter among the inverters by connecting a predetermined output terminal to the positive or negative side of the power supply according to the opening and closing of a plurality of switching elements And a pulse generation logic circuit part capable of generating the template pulse which is a typical pulse signal,
The multi-stage inverter circuit unit feeds back the output of the inverter at the final stage in a predetermined multi-stage part to the input terminal of the first stage of the multi-stage part according to the oscillation mode switching signal supplied to the mode control signal input terminal It is configured to switch the intermittent loop of the feedback loop circuit that forms the ring oscillation circuit by connecting the closed loop,
4. The template pulse generation circuit according to claim 3, wherein the pulse generation logic circuit unit generates the template pulse continuously or intermittently according to switching of the feedback loop circuit.   The template pulse generation circuit according to claim 4, wherein the multistage inverter circuit unit is configured by cascading a plurality of differential inverter circuits. A counter for counting oscillation pulses by the ring oscillation circuit;
The said output mode switching circuit is comprised so that the duration of the said template pulse in the said intermittent output mode may be prescribed | regulated according to the count value of the said counter. 2. A template pulse generation circuit according to 1.   The multi-stage inverter circuit unit is configured to open and close the corresponding switching element of the corresponding I-phase system pulse generation logic circuit unit according to the output of the even-stage inverter, thereby causing the I-phase system pulse generation logic circuit unit to open and close. The I-phase template pulse is generated from the output terminal of the Q-phase, and the corresponding switching element of the pulse generation logic circuit portion of the corresponding Q-phase system is opened and closed by the output of the odd-numbered inverters of the Q-phase. 7. The template pulse generation circuit according to claim 6, wherein the template pulse generation circuit is configured to generate the Q-phase template pulse from an output terminal of a system pulse generation logic circuit unit.   The template pulse generation circuit according to claim 6, wherein the ring oscillation circuit is configured such that an oscillation frequency can be adjusted according to a supplied frequency control signal. The template pulse generation circuit according to any one of claims 1 to 8,
A detection circuit that performs detection based on a correlation between an output pulse of the template pulse generation circuit and a reception pulse;
The template pulse generating circuit is operated in the continuous output mode in the synchronous acquisition mode for performing synchronous acquisition upon detection of the received pulse, and the template pulse generating circuit is operated in the intermittent output mode when the synchronous acquisition is established. A system controller for supplying a control signal for switching the operation mode to the template pulse generation circuit;
A communication apparatus comprising: A template pulse generation circuit according to any one of claims 7 to 8,
An I-phase pulse multiplier for multiplying the received pulse by the I-phase template pulse of the template pulse generating circuit;
A Q-phase pulse multiplier that multiplies the received pulse with the Q-phase template pulse of the template pulse generation circuit;
An I-phase envelope detection processing circuit that performs envelope detection processing on an I-phase multiplication output pulse that is an output of the I-phase pulse multiplier;
A Q-phase envelope detection processing circuit for performing envelope detection processing on a Q-phase multiplication output pulse that is an output of the Q-phase pulse multiplier;
An envelope signal adding circuit for adding and synthesizing an I-phase envelope signal that is an output of the I-phase envelope detection processing circuit and a Q-phase envelope signal that is an output of the Q-phase envelope detection processing circuit;
A synchronization acquisition processing unit that performs synchronization acquisition based on a composite envelope signal that is an output of the envelope signal addition circuit;
A pulse position tracking processing unit that performs a pulse position tracking process based on the composite envelope signal;
The template pulse generation circuit is operated in the continuous output mode in the synchronization acquisition mode in which the synchronization acquisition processing unit performs synchronization acquisition, and the template pulse generation circuit is operated in the intermittent output mode when the synchronization acquisition is established. A system controller for supplying a control signal for switching the operation mode to the template pulse generation circuit;
A communication apparatus comprising: The I-phase envelope detection processing circuit includes an I-phase pulse square circuit that squares the I-phase multiplication output pulse,
The communication apparatus according to claim 10, wherein the Q-phase envelope detection processing circuit includes a Q-phase pulse square circuit that squares the Q-phase multiplication output pulse. The I-phase envelope detection processing circuit includes an I-phase pulse rectifier circuit that rectifies the I-phase multiplication output pulse,
The communication apparatus according to claim 10, wherein the Q-phase envelope detection processing circuit includes a Q-phase pulse rectifier circuit that rectifies the Q-phase multiplication output pulse.   The pulse position tracking processing unit performs a pulse position tracking process based on a comparison between an integral value of a phase advance DLL circuit that performs a phase advance process for advancing the phase and an integral value of a delay phase DLL circuit that performs a phase delay process for delaying the phase. The communication apparatus according to claim 10, wherein the communication apparatus is configured to obtain a demodulated output based on an output of an in-phase DLL circuit that performs in-phase processing to perform phase in-phase processing.   The synchronous acquisition processing unit includes a synchronous detection function unit that performs a frequency adjustment process for matching frequencies together with a phase synchronization process between the template pulse and the reception pulse. 14. The communication device according to any one of 13.   The communication apparatus according to claim 9, further comprising a storage function unit that stores pulse position information acquired when the synchronization acquisition is established.   The system controller is configured to supply the template pulse generation circuit with a clock pulse used to operate the template pulse generation circuit in the intermittent output mode in accordance with the pulse position information stored in the storage function unit. The communication device according to claim 15, wherein Provided with a power control unit that controls the supply of power for operation,
17. The system controller according to claim 9, wherein the system controller controls the power supply control unit to partially stop power supply during a period when the reception pulse has not arrived. Communication device.   A continuous output mode in which a template pulse used for detection of a received pulse is continuously generated is selected during a period of synchronization acquisition in pulse communication, and the template pulse is generated intermittently during a period after the establishment of the synchronization acquisition. A communication method characterized by switching to an intermittent output mode.

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