JP2008244984A - Current mirror circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current mirror circuit capable of shortening a recovery time from a standstill state with simple circuit configuration. <P>SOLUTION: A switch SW1 (first switch means) is disposed between an input transistor 11 constituted of a P-channel type MOSFET and a reference current source 10 supplying a reference current Iin thereto. Furthermore, a switch SW2 (second switch means) is disposed between an output transistor 12 constituted of a P-channel type MOSFET and a constant current output terminal 13. The two switches SW1 and SW2 are inserted in series to drain terminals of the input transistor 11 and the output transistor 12, and a bias line B commonly connecting gate terminals of the input transistor 11 and the output transistor 12 is connected with the reference current source 10 directly without interposing the switch SW1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a current mirror circuit configured by connecting a control terminal of an input transistor to control terminals of one or more output transistors, and more particularly to a current mirror circuit having an output current stop function.

  Conventionally, current mirror circuits have been widely used as bias current sources for various analog circuits. When power is supplied from a current mirror circuit, the bias current of unused circuit blocks is often stopped in order to reduce the power consumption of the system (see, for example, Patent Document 1).

FIG. 4 is a diagram showing a current mirror circuit having a conventional output current stopping function.
This current mirror circuit includes a reference current source 10, an input transistor 11, an output transistor 12, and two switches SW10 and SW11. Each of the input transistor 11 and the output transistor 12 has a source terminal and a substrate connected to one power supply VDD, and a gate terminal connected to each other by a bias line B. The bias line B is configured to be connectable to one power supply VDD (the potential is also VDD) via the first switch SW10.

  The input transistor 11 is short-circuited between the drain terminal and the gate terminal by the second switch SW11, and the gate-source voltage (Vgs) can be set to a level at which the input transistor 11 is maintained in the saturation mode. The drain terminal of the input transistor 11 is grounded via a reference current source 10 realized by a resistor (not shown). Further, the drain terminal of the output transistor 12 is connected to the constant current output terminal 13, and a current mirror circuit is formed through which a constant current output current Iout flows.

  Each element of the current mirror circuit is configured by a P-channel MOSFET (metal oxide film field effect transistor), but may be an N-channel MOSFET.

  When the first switch SW10 is turned on (conductive), the gate terminal common to the input transistor 11 and the output transistor 12 is short-circuited with the source terminal, and the current flowing through the current mirror circuit is cut off. At this time, the second switch SW11 is turned off (shut off), thereby preventing unnecessary current from being consumed by the reference current source 10 from the power supply VDD via the first switch SW10.

FIG. 5 is a diagram showing another current mirror circuit having an output current stop function.
Here, in place of the second switch SW11, the third switch SW12 is interposed between the drain terminal of the input transistor 11 and the reference current source 10, thereby eliminating wasteful power consumption during non-operation. ing.

  In any current mirror circuit, the first switch SW10 can be turned off and the second switch SW11 (or the third switch SW12) can be turned on to return from the stopped state to the operating state. At this time, in order to shift the gate potentials of the input transistor 11 and the output transistor 12 having a common gate terminal from the previous VDD to a predetermined operating point, the parasitic capacitance between the gate and the source of the transistors 11 and 12 is set. Needs to be charged with the reference current Iin of the reference current source 10. Therefore, when the reference current Iin is small, or the size of the output transistor 12 is large or the number thereof is large, there is a problem that it takes a long time for the output current Iout to reach a predetermined value.

Therefore, a current mirror circuit is considered in which the rise time of the current is shortened by changing the mirror ratio transiently by a boost circuit or the like when switching between current output and non-output (for example, see Patent Document 2). .
Japanese Patent Laid-Open No. 7-275358 (paragraph numbers [0034] to [0038], FIG. 2) JP 2005-229505 A (paragraph numbers [0023] to [0046], FIG. 1)

  By the way, in the boost circuit as described above, when switching control from the state where the input current does not flow to the state where the input current flows using the start circuit, the timing is detected based on the control signal, and the transistor switch or the like The current path provided with is cut off for a predetermined period.

  However, in order to realize such a switching operation, it is necessary to provide a circuit for performing edge detection in addition to the boost circuit, and there is a problem that the circuit configuration becomes complicated.

  The present invention has been made in view of these points, and an object of the present invention is to provide a current mirror circuit capable of shortening the return time from a stopped state with a simple circuit configuration.

  In the present invention, in order to solve the above problem, in a current mirror circuit configured by connecting a control terminal of an input transistor to control terminals of one or more output transistors, a constant current for supplying a reference current to the input transistor is provided. A circuit, an output terminal for outputting the current flowing through the output transistor to the outside, a first switch means disposed between the input transistor and the constant current circuit, and disposed between the output transistor and the output terminal A second switch means, wherein the control terminal of the input transistor and the constant current circuit are connected without going through the first switch means, and a stop state in which the current to the output terminal is stopped Then, when the first and second switch means are turned off and a current is supplied to the output terminal, the first and second switches are operated. Current mirror circuit, wherein provided that switching the pitch means to the ON state.

  According to the present invention, a current mirror circuit having a short recovery time from a stopped state can be realized with a simple circuit configuration.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a circuit diagram showing a current mirror circuit according to the first embodiment.

  In the current mirror circuit of FIG. 1, a switch SW1 (first switch means) is arranged between an input transistor 11 made of a P-channel MOSFET and a reference current source 10 for supplying a reference current thereto. A switch SW2 (second switch means) is disposed between the output transistor 12 made of a P-channel MOSFET and the constant current output terminal 13.

  Here, the two switches SW 1 and SW 2 are inserted in series with respect to the drain terminals of the input transistor 11 and the output transistor 12. A bias line B that commonly connects the gate terminals of the input transistor 11 and the output transistor 12 is directly connected to the reference current source 10 without passing through the switch SW1. The input transistor 11 and the output transistor 12 have the same channel width W and channel length L ratio (W / L), and the reference current source 10 supplies the reference current Iin in a magnitude of 1 μA, for example.

  In the stop state in which the output current Iout flowing through the constant current output terminal 13 is stopped, both the switches SW1 and SW2 are in the off state. As a result, the reference current Iin and the output current Iout to the reference current source 10 do not flow, and unnecessary power consumption is saved. At that time, the reference current Iin of the reference current source 10 is used only for charging the parasitic capacitance between the gate and the source of the input transistor 11 and the output transistor 12, and the potential of the gate terminal commonly connected by the bias line B is used. Is pulled down to ground potential.

  Now, when the two switches SW1 and SW2 are turned on to switch the current mirror circuit to the activated state, both the input transistor 11 and the output transistor 12 generate a high voltage value between the gate and the source. Therefore, the output current Iout starts to flow excessively from the output transistor 12 immediately after the start-up, and the overcharged charge in the parasitic capacitance between the gate and the source of the input transistor 11 and the output transistor 12 passes through the diode-connected input transistor 11. Discharged. Therefore, the output current Iout from the constant current output terminal 13 converges to a steady state in a shorter time than that of the conventional circuit (FIGS. 4 and 5) even when the reference current Iin is small.

FIG. 2 is a diagram illustrating a startup waveform of the output current Iout. Here, the startup waveform of the present invention is shown in comparison with the conventional circuit (FIGS. 4 and 5).
In the startup waveform (broken line) in the conventional circuit, the period during which the output current Iout is 0 A is as long as about 200 ns, and then gradually rises and gradually stabilizes at about 1.0 μA after about 400 ns. On the other hand, the startup waveform (solid line) of the present invention has a waveform characteristic in which the output current Iout already shows a large current value at 100 ns and then decreases rapidly thereafter. As a result, as shown in the start-up waveform of the present invention, it can be seen that the target current value is reached in a short time of about 250 ns, which is about half of the conventional circuit.

  In the first embodiment described above, the input transistor 11 has the same size as the output transistor 12, and the reference current Iin and the output current Iout flow with the same size. However, the input transistor 11 and the output transistor 12 may have different sizes. In that case, the magnitude of the reference current Iin flowing through the input transistor 11 and the magnitude of the output current Iout flowing through the output transistor 12 are in a proportional relationship.

(Embodiment 2)
FIG. 3 is a circuit diagram showing a multi-output current mirror circuit according to the second embodiment.
The multi-output current mirror circuit includes three constant current output terminals 13, 15, and 17. A P-channel type MOSFET 21 is connected in series to the input transistor 11 as a switch SW 1, and is connected to the output transistor 12. Between the current output terminals 13, a P-channel MOSFET 22 is arranged as a switch SW2. Further, a P-channel type MOSFET 23 is arranged as a third switch SW3 between the second output transistor 14 and the constant current output terminal 15, and further between the third output transistor 16 and the constant current output terminal 17. The P-channel type MOSFET 24 is arranged as the fourth switch SW4.

  Here, the input transistor 11 and the three output transistors 12, 14, 16 constitute a current mirror unit 18, and the P-channel type MOSFETs 21 to 24 are supplied from the gate terminal connected to the control terminal 20. It functions as a switch circuit unit 25 that switches between an operating state and a stopped state of the current mirror unit 18 by an enable signal (enable).

  Now, the input transistor 11 and the three output transistors 12, 14, and 16 are configured by, for example, P-channel MOSFETs, and the ratio (W / L) of the channel width W to the channel length L is 8 μm / 6 μm. On the other hand, the same P-channel type MOSFETs 21 to 24 constituting the switch circuit unit 25 are formed at W / L = 2 μm / 0.6 μm. Further, for example, the reference current Iin is supplied in a magnitude of 1 μA from the reference current source 10 formed of an N-channel MOSFET, as in the first embodiment.

  Then, the potential of the enable signal supplied to the gate terminals of the MOSFETs 21 to 24 is changed from the power supply (VDD) level to the ground (GND) level, and the switch circuit unit 25 is switched from OFF to ON. The output currents Iout1 to Iout3 change as shown in FIG. 2 (FIG. 2 relates to the circuit of FIG. 3 to which the above W / L is applied and the conventional circuit under the same condition as one output from a plurality of output currents. The waveform is compared focusing on the current). Therefore, it is possible to realize a multi-output current mirror circuit that shortens the recovery time from the stopped state with a simple circuit configuration.

  Further, when the MOSFETs 21 to 24 of the switch circuit unit 25 are turned on, they may be controlled by an enable signal fixed to an appropriate potential level instead of the ground (GND) level. In that case, if the gate potential is applied so that the MOSFETs 21 to 24 operate in the saturation region, not only the recovery time from the stop state can be shortened, but also a cascode connection structure is made to function as a current mirror circuit with high output impedance. Can do.

  Although the circuit of FIG. 3 has been described with only a P-channel MOSFET, the current mirror circuit configured with an N-channel MOSFET can also be configured with the same function having an output current stop function. It is.

FIG. 3 is a circuit diagram showing a current mirror circuit according to the first embodiment. It is a figure which shows the starting waveform of the output electric current Iout. 6 is a circuit diagram showing a multi-output current mirror circuit according to a second embodiment; FIG. It is a figure which shows the current mirror circuit which has the conventional output current stop function. It is a figure which shows another current mirror circuit which has an output current stop function.

Explanation of symbols

10 reference current source 11 input transistor 12 output transistor 13 constant current output terminal B bias line SW1 switch (first switch means)
SW2 switch (second switch means)

Claims (5)

In a current mirror circuit configured by connecting a control terminal of an input transistor to control terminals of one or more output transistors,
A constant current circuit for supplying a reference current to the input transistor;
An output terminal for outputting the current flowing through the output transistor to the outside;
First switch means disposed between the input transistor and the constant current circuit;
Second switch means disposed between the output transistor and the output terminal;
With
The control terminal of the input transistor and the constant current circuit are connected without going through the first switch means, and the first and second switch means are in a stop state in which the current to the output terminal is stopped. A current mirror circuit characterized in that the first and second switch means are switched to an on state when the current is supplied to the output terminal while being turned off.   2. The current mirror circuit according to claim 1, wherein each of the input transistor and the output transistor is configured by a metal oxide film type field effect transistor (hereinafter referred to as a MOSFET).   2. The current mirror circuit according to claim 1, wherein each of the first switch means and the second switch means is constituted by a MOSFET.   4. The current mirror circuit according to claim 3, wherein when the MOSFET is on, the current mirror circuit operates in a saturation region thereof.   2. The current mirror circuit according to claim 1, wherein the input transistor, the output transistor, the first switch means, and the second switch means are all constituted by MOSFETs having the same conductivity type.

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