JP7227732B2 - clamp circuit - Google Patents

Description

The invention disclosed herein relates to clamp circuits.

FIG. 10 is a diagram showing a first conventional example of a current mirror. In the conventional current mirror 100, the transistor M1 corresponds to an input transistor to which the reference current I1 is input, and the transistors M2 to M4 are paired with the transistor M1 to output mirror currents Im1 to Im3. Corresponds to an output transistor.

When a high input voltage VIN (for example, 40V) is applied to the current mirror 100, each of the transistors M1 to M4 has a high withstand voltage element (for example, 50V withstand voltage) having a drain-source withstand voltage higher than the input voltage VIN. element) must be used.

As an example of conventional technology related to the above, Patent Document 1 can be cited.

JP-A-6-259032

However, if high-voltage elements are used as the transistors M1 to M4, relative variations (variation in size ratio) between the transistors M1 to M4 become large, and the output accuracy of the mirror currents Im1 to Im3 deteriorates. If the sizes of the transistors M1 to M4 are increased, the respective relative variations can be reduced, but the area of the current mirror 100 is increased.

11A and 11B are diagrams showing a second conventional example of a current mirror. 11A shows the state when the current mirror is in operation (when I1 is on), and FIG. 11B shows the state when the current mirror is stopped (when I1 is off).

The conventional current mirror 100 is of a cascode type having transistors M5 to M8 in addition to the transistors M1 to M4 described above. As the transistors M1 to M4, low withstand voltage elements (elements with sufficiently high withstand voltage against the substrate, for example, 5 to 7 V withstand voltage elements) are used. On the other hand, high voltage elements are used for the transistors M5 to M8.

Mirror currents Im1-Im3 are determined by the size ratio of transistors M1-M4. Since the transistors M1 to M4 are low withstand voltage elements, they have good relative accuracy and small area. However, since the transistors M2 to M4 each have a low withstand voltage between the drain and the source, it is necessary to suppress the voltage between the drain and the source of each of the transistors M2 to M4 using the transistors M6 to M8.

Specifically, as shown in FIG. 11A, when the current mirror 100 is in operation (=when the reference current I1 is on), the drain-source voltage of each of the transistors M2 to M4 is a predetermined bias voltage (= The on-threshold voltage Vth of each of the transistors M1 to M8 (assumed to be the same value for simplicity) is constant. Therefore, even if the transistors M2 to M4 are low withstand voltage elements, they can operate without problems.

The transistors M6 to M8 are provided for the purpose of clamping the voltages between the drain and source of the transistors M2 to M4, respectively, and the relative variation of each of them almost affects the output accuracy of the mirror currents Im1 to Im3. do not. Therefore, the transistors M6 to M8 can be small in size.

Further, by providing the transistors M6 to M8, in addition to the effect of clamping the voltage between the drain and source of each of the transistors M2 to M4 below the rated voltage, by fixing the voltage between the drain and source of each of the transistors M1 to M4, The effect of improving the power supply dependence of the mirror currents Im1 to Im3 can also be enjoyed.

As described above, the current mirror 100 of the conventional example does not cause any particular problem during operation (=when the reference current I1 is on), but as shown in FIG. 11B, when it is not in operation (=reference current When I1 is off), nodes A, B and C become high impedance. Therefore, the potentials of the nodes A, B and C are determined by the balance between the leakage currents flowing through the transistors M2 to M4 and the leakage currents flowing through the transistors M6 to M8.

If the leak current flowing through the transistors M6 to M8 is larger than the leak current flowing through the transistors M2 to M4, the potentials of the nodes A, B, and C will gradually decrease, so that the potential of the transistor M2 will eventually drop. There is a possibility that the withstand voltage between the drain and the source of each of ˜M4 will be exceeded, leading to destruction of the element.

12A and 12B are diagrams showing a third conventional example of a current mirror. 12A shows the state when the current mirror is in operation (when I1 is on), and FIG. 12B shows the state when the current mirror is stopped (when I1 is off).

In the conventional current mirror 100, Zener diodes D1 to D3 are inserted in parallel with the transistors M2 to M4 in order to solve the above problem (=destruction of the low withstand voltage element due to leakage current during non-operation). It is Note that the breakdown voltage Vz of the Zener diodes D1-D3 is lower than the drain-source breakdown voltage of each of the transistors M2-M4.

As a result, when the current mirror 100 is not operating (=when the reference current I1 is off), even if the drain-source voltages of the transistors M2 to M4 try to rise due to the leakage currents of the transistors M6 to M8, this can be kept below the rated voltage.

When the current mirror 100 is in operation (=when the reference current I1 is on), the drain-source voltages of the transistors M2 to M4 are fixed at the on-threshold voltage Vth by the functions of the transistors M5 to M8, as described above. be done. Therefore, the Zener diodes D1 to D3 do not operate, and the operation of the current mirror 100 is not affected.

However, in the conventional current mirror 100, it is necessary to provide a Zener diode for each mirror current output system. In FIGS. 12A and 12B, the current mirror 100 has three output systems, so at least three Zener diodes are required. If the number of output systems increases, the number of Zener diodes also needs to be increased. Zener diodes are by no means small elements, so if the number of them increases, it becomes a factor of increasing the area of the current mirror 100 .

SUMMARY OF THE INVENTION The invention disclosed in the present specification is intended to provide a clamp circuit having a small area and capable of preventing withstand voltage breakdown of an element to be protected.

The clamp circuit disclosed in this specification uses a first transistor of a first conductivity type connected between a first node and a second node as a component of an electronic circuit as an element to be protected. is connected between the second node and the third node as a clamp element for limiting the voltage across the first transistor when the electronic circuit is not operating, and the control end thereof is connected to the fourth node. a second transistor of a second conductivity type; the second node is a node that becomes high impedance when the electronic circuit is not in operation without the clamp circuit; , respectively, a voltage is applied to turn off the second transistor when the electronic circuit is in operation and to turn on the second transistor when the electronic circuit is not in operation (first configuration).

In addition, in the clamp circuit having the first configuration, the first transistor is a P-channel type or a pnp type, the second transistor is an N-channel type or an npn type, and when the electronic circuit operates, the second The voltage applied to the node is V2, the voltage applied to the third node is V3, the voltage applied to the fourth node is V4, the on-threshold voltage of the second transistor is Vth, and V4≦V2+Vth and V3>V4− A configuration (second configuration) that satisfies Vth is preferable.

Further, in the clamp circuit having the first configuration, the first transistor is an N-channel type or an npn type, the second transistor is a P-channel type or a pnp type, and the second The voltage applied to the node is V2, the voltage applied to the third node is V3, the voltage applied to the fourth node is V4, the on-threshold voltage of the second transistor is Vth, and V4≧V2−Vth and V3< A configuration (third configuration) in which V4+Vth is established is preferable.

Further, in the clamp circuit having any one of the first to third configurations, the electronic circuit is a current mirror that generates a mirror current corresponding to a reference current, and the first transistor receives the reference current. A configuration (fourth configuration) that is used as an output transistor that forms a pair with an input transistor and outputs the mirror current may be employed.

Further, in the clamp circuit having the fourth configuration, the current mirror is a multi-output type that uses a plurality of the first transistors to output the mirror currents to a plurality of systems, and the second transistor is the first transistor. and the control terminals of the second transistors are connected in common (fifth configuration).

Further, in the clamp circuit having the fourth or fifth configuration, the current mirror preferably has a configuration (sixth configuration) having a function of turning on/off the reference current.

Further, in the clamp circuit having the sixth configuration, if the current mirror is of a cascode type and the second node is fixed at a predetermined bias voltage when the reference current is turned on (seventh configuration), good.

Further, the clamp circuit having any one of the first to seventh configurations includes a diode or a diode-connected transistor that determines the voltage applied to the fourth node, and a current source that generates a drive current for the diode or the diode-connected transistor. It is preferable to adopt a configuration (eighth configuration) that further includes.

In the clamp circuit having any one of the first to seventh configurations, the fourth node may be connected to the control terminal of the first transistor (ninth configuration).

In the clamp circuit having any one of the first to ninth configurations, the third node may be connected to the first node or the fourth node (tenth configuration).

According to the invention disclosed in this specification, it is possible to provide a clamp circuit that can prevent breakdown of a device to be protected from breakdown with a small area.

The figure which shows 1st Embodiment (when I1 is ON) of a current mirror and a clamp circuit The figure which shows 1st Embodiment (when I1 is off) of a current mirror and a clamp circuit The figure which shows 2nd Embodiment (when I1 is on) of a current mirror and a clamp circuit The figure which shows 2nd Embodiment (when I1 is off) of a current mirror and a clamp circuit The figure which shows 3rd Embodiment (when I1 is ON) of a current mirror and a clamp circuit The figure which shows 3rd Embodiment (when I1 is off) of a current mirror and a clamp circuit The figure which shows 4th Embodiment (when I1 is on) of a current mirror and a clamp circuit The figure which shows 4th Embodiment (when I1 is off) of a current mirror and a clamp circuit The figure which shows 5th Embodiment (when I3 is ON) of a current mirror and a clamp circuit The figure which shows 5th Embodiment (when I3 is off) of a current mirror and a clamp circuit A diagram showing a sixth embodiment of the current mirror and clamp circuit (when I3 is on) A diagram showing a sixth embodiment of the current mirror and clamp circuit (when I3 is off) The figure which shows 7th Embodiment (when I3 is ON) of a current mirror and a clamp circuit The figure which shows 7th Embodiment (at the time of I3 OFF) of a current mirror and a clamp circuit The figure which shows 8th Embodiment (when I3 is ON) of a current mirror and a clamp circuit The figure which shows 8th Embodiment (when I3 is off) of a current mirror and a clamp circuit A diagram showing a ninth embodiment of the clamp circuit (generic concept of the first to fourth embodiments) A diagram showing a tenth embodiment of the clamp circuit (general concept of the fifth to eighth embodiments) FIG. 11 is a diagram showing a first conventional example of a current mirror; FIG. 4 shows a second conventional example of a current mirror (during operation); A diagram showing a second conventional example of a current mirror (when stopped) FIG. 10 is a diagram showing a third conventional example of a current mirror (during operation); A diagram showing a third conventional example of a current mirror (when stopped)

<First embodiment>
1A and 1B show a first embodiment of a current mirror and a clamping circuit implemented therein. FIG. 1A shows the state during current mirror operation (when I1 is on), and FIG. 1B shows the state when the current mirror is stopped (when I1 is off).

In this embodiment, the current mirror 10 is of a multi-output type that generates three systems of mirror currents Im1-Im3 according to the reference current I1, and includes P-channel MOS field effect transistors M1-M8 and a current source CS1.

The sources of the transistors M1 to M4 are all connected to the application terminal of the input voltage VIN (40 V, for example). Gates of the transistors M1 to M4 are all connected to the drain of the transistor M1. The drains of the transistors M1-M4 are connected to the sources of the transistors M5-M8, respectively. The gates of the transistors M5 to M8 are all connected to the drain of the transistor M5. The drain of transistor M5 is connected to a first end of a current source CS1 that produces a reference current I1. A second end of the current source CS1 is connected to the ground end. The drains of the transistors M6-M8 correspond to the output terminals of the mirror currents Im1-Im3.

As the transistors M1 to M4, low withstand voltage elements (elements with sufficiently high withstand voltage against the substrate, for example, 5 to 7 V withstand voltage elements) are used. On the other hand, high voltage elements are used for the transistors M5 to M8.

Thus, the current mirror 10 itself is no different from the cascode-type current mirror 100 shown in the second conventional example (FIGS. 11A and 12B). Therefore, redundant description of the operation of the current mirror 10 itself is omitted.

The clamp circuit 11 uses the transistors M2 to M4 that form the current mirror 10 as elements to be protected. to a rated voltage or less, and includes N-channel MOS field effect transistors M9 to M11 as clamping elements for each of the transistors M2 to M4. The clamp circuit 11 further includes a Zener diode D4 that determines the gate voltage of each of the transistors M9-M11, and a current source CS2 that generates a drive current I2 for the Zener diode D4.

The drains of the transistors M9 to M11 are connected to the application terminal of the input voltage VIN. The sources of the transistors M9-M11 are respectively connected to the drains (=nodes A, B and C) of the transistors M2-M4. Gates of the transistors M9 to M11 are all connected to the anode of the Zener diode D4 and the first end of the current source CS2. The cathode of the Zener diode D4 is connected to the application terminal of the input voltage VIN. A second end of the current source CS2 is connected to ground.

Thus, in the clamp circuit 11 of the present embodiment, by combining the single Zener diode D4 and the three transistors M9 to M11, the drain-source voltage of each of the transistors M2 to M4 is limited to the rated voltage or less. ing.

A specific description will be given below. When the current mirror 10 is not operating (=when the reference current I1 is off), the nodes A, B, and C, which would be high impedance if the clamp circuit 11 were not present, are connected to the sources of the transistors M9 to M11, respectively. there is An arbitrary bias voltage (=VIN-Vz) determined using a Zener diode D4 is applied to the gates of the transistors M9 to M11.

Therefore, when the current mirror 10 is not operating (=when the reference current I1 is off), even if a voltage drop occurs at the nodes A, B and C due to leakage currents of the transistors M6 to M8, the transistors M9 to M11 When the voltages of the nodes A, B and C drop to a voltage lower than the bias voltage (=VIN-Vz) applied to each gate by the ON threshold Vth, the transistors M9 to M11 are turned on.

As a result, it is possible to prevent a further voltage drop at the nodes A, B, and C, so that the voltage between the drain and source of each of the transistors M2 to M4 can be suppressed below the rated voltage. It is possible to prevent breakdown of each M4.

The drain-source voltage of each of the transistors M2 to M4 is clamped to the upper limit value (=Vz+Vth) determined using the Zener diode D4. Therefore, the breakdown voltage Vz of the Zener diode D4 should be selected so that the upper limit (=Vz+Vth) does not exceed the drain-source breakdown voltage of each of the transistors M2 to M4.

Further, when the current mirror 10 is in operation (=when the reference current I1 is on), the nodes A, B and C are fixed at a predetermined bias voltage (=VIN-Vth) by the action of the transistors M5 to M8. Therefore, the clamp circuit 11 does not operate and the operation of the current mirror 10 is not affected.

Further, with the clamp circuit 11 of the present embodiment, even if the number of output systems (and thus protection target elements) of the current mirror 10 increases, there is no need to increase the number of Zener diodes D4. Therefore, it is possible to prevent the withstand voltage breakdown of the element to be protected with a small area.

Also, the transistors M9 to M11 functioning as clamping elements do not require a very large current capability as long as they can supply the leakage current flowing through the transistors M6 to M8. Therefore, since the minimum size of each element is sufficient, even if it becomes necessary to increase the number of clamping elements as the number of output systems in the current mirror 10 increases, the area of the clamping circuit 11 hardly increases.

The transistors M9 to M11 corresponding to clamp elements may be replaced with npn bipolar transistors. Similarly, the transistors M1 to M8 (including the transistors M2 to M4 corresponding to the elements to be protected) forming the current mirror 10 may be replaced with pnp type bipolar transistors.

<Second embodiment>
2A and 2B show a second embodiment of the current mirror and the clamping circuit implemented therein. FIG. 2A shows the state when the current mirror is in operation (when I1 is on), and FIG. 2B shows the state when the current mirror is stopped (when I1 is off).

The clamp circuit 11 of this embodiment is based on the first embodiment (FIGS. 1A and 1B) and includes a diode-connected P-channel MOS field effect transistor M12 instead of the Zener diode D4. That is, the source of the transistor M12 is connected to the application terminal of the input voltage VIN, and the drain and gate of the transistor M12 are both connected to the gates of the transistors M9 to M11.

In this case, an arbitrary bias voltage (=VIN-Vth) determined using the transistor M12 is applied to each gate of the transistors M9 to M11.

Note that the on-threshold voltage Vth of the transistor M12 does not affect the operation of the current mirror 10, and when the current mirror 10 is not operating, the voltage between the drain and source of each of the transistors M2 to M4 is kept below the rated voltage. It may be arbitrarily adjusted within the limitable range.

Since the clamp circuit 11 of this embodiment does not use any Zener diodes, it is possible to make the area smaller than that of the first embodiment (FIGS. 1A and 1B).

Further, as shown in the balloon frame of this figure, the diode-connected transistor is not limited to the P-channel MOS field effect transistor, but may be an N-channel MOS field effect transistor, a pnp bipolar transistor, or an npn bipolar transistor. can be used.

<Third Embodiment>
3A and 3B illustrate a third embodiment of the current mirror and the clamping circuit implemented therein. FIG. 3A shows the state when the current mirror is in operation (when I1 is on), and FIG. 3B shows the state when the current mirror is stopped (when I1 is off).

The clamp circuit 11 of this embodiment is based on the first embodiment (FIGS. 1A and 1B) or the second embodiment (FIGS. 2A and 2B), and the gates of the transistors M9 to M11 are replaced by the transistor M1. . . . M4 (hereafter referred to as node D), the current source CS2 and Zener diode D4 (or transistor M12) are omitted.

Thus, it is possible to use the voltage applied to the node D of the current mirror 10 as the gate voltage of each of the transistors M9 to M11.

VIN-Vth is applied to the node D when the current mirror 10 is in operation (=when the reference current I1 is on). Therefore, in order to turn on the transistors M9 to M11, the voltage applied to each of the nodes A, B and C must drop to VIN-2Vth. However, since the voltages applied to the nodes A, B and C are all fixed at VIN-Vth by the action of the transistors M6-M8, the transistors M9-M11 are not turned on.

On the other hand, when the current mirror 10 is not operating (=when the reference current I1 is off), the potential of the node D becomes an indefinite value with a fluctuation range of VIN to (VIN-Vth). Therefore, even if a voltage drop occurs at the nodes A, B, and C due to the leak currents of the transistors M6 to M8, the on-state potential is higher than the indefinite potential of the node D applied to the gates of the transistors M9 to M11. When the voltages of the nodes A, B and C drop to a voltage lower than the threshold Vth, the transistors M9 to M11 are turned on. As a result, the voltage between the drain and the source of each of the transistors M2 to M4 is clamped within the voltage range of Vth to 2Vth, so that breakdown of the transistors M2 to M4 can be prevented.

<Fourth Embodiment>
4A and 4B are diagrams showing a fourth embodiment of the current mirror and the clamping circuit implemented therein. FIG. 4A shows the state when the current mirror is in operation (when I1 is on), and FIG. 4B shows the state when the current mirror is stopped (when I1 is off).

The clamp circuit 11 of this embodiment is based on the above-described third embodiment (FIGS. 3A and 3B), but the drains of the transistors M9 to M11 are connected to their respective gates instead of the input voltage VIN application terminal. ing. In this way, even when the drains of the transistors M9 to M11 are commonly connected to the respective gates, the same effects as above can be obtained.

In addition, in this embodiment, an example based on the third embodiment (FIGS. 3A and 3B) was given, but the first embodiment (FIGS. 1A and 1B) or the second embodiment (FIGS. 2A and 2B), the drains of the transistors M9 to M11 may be connected to their respective gates instead of the input voltage VIN application terminal.

<Fifth Embodiment>
5A and 5B are diagrams showing a fifth embodiment of a current mirror and a clamping circuit implemented therein. 5A shows the state when the current mirror is in operation (when I3 is on), and FIG. 5B shows the state when the current mirror is stopped (when I3 is off).

In this embodiment, the current mirror 20 is of a multi-output type that generates three systems of mirror currents Im4-Im6 according to the reference current I3, and includes N-channel MOS field effect transistors M13-M20 and a current source CS3.

The sources of the transistors M13 to M16 are all connected to the ground terminal. Gates of the transistors M13 to M16 are all connected to the drain of the transistor M13. The drains of the transistors M13-M16 are connected to the sources of the transistors M17-M20, respectively. The gates of the transistors M17 to M29 are all connected to the drain of the transistor M17. The drain of transistor M17 is connected to a first end of a current source CS3 that produces a reference current I3. The second end of the current source CS3 is connected to the application end of the input voltage VIN (eg 40V). The drains of the transistors M17-M20 correspond to the output terminals of the mirror currents Im4-Im6.

As the transistors M13 to M16, low withstand voltage elements (elements with sufficiently high withstand voltage against the substrate, for example, 5 to 7 V withstand voltage elements) are used. On the other hand, high voltage elements are used for the transistors M17 to M20.

In this way, the current mirror 20 itself is the cascode current mirror 100 shown in the second conventional example (FIGS. 11A and 12B) whose polarity is reversed (=flow direction of reference current I3 and mirror currents Im4 to Im6). is reversed). Therefore, redundant description of the operation of the current mirror 20 itself is omitted.

The clamp circuit 21 uses the transistors M14 to M16 that form the current mirror 20 as elements to be protected. to a rated voltage or less, and includes P-channel MOS field effect transistors M21 to M23 as clamping elements for each of the transistors M14 to M16. The clamp circuit 21 further includes a Zener diode D5 that determines the gate voltage of each of the transistors M21 to M23, and a current source CS4 that generates the drive current I4 for the Zener diode D5.

Each drain of the transistors M21 to M23 is connected to the ground terminal. The sources of the transistors M21 to M23 are respectively connected to the drains (=nodes E, F and G) of the transistors M14 to M16. Gates of the transistors M21 to M23 are all connected to the cathode of the Zener diode D5 and the first terminal of the current source CS4. The anode of Zener diode D5 is connected to the ground terminal. A second end of the current source CS4 is connected to the application end of the input voltage VIN.

Thus, in the clamp circuit 21 of the present embodiment, by combining the single Zener diode D5 and the three transistors M21 to M23, the drain-source voltage of each of the transistors M14 to M16 is limited to the rated voltage or less. ing.

A specific description will be given below. When the current mirror 20 is not operating (=when the reference current I3 is off), the sources of the transistors M21 to M23 are connected to the nodes E, F, and G, which would be high impedance if the clamp circuit 21 were not present. there is An arbitrary bias voltage (=Vz) determined using a Zener diode D5 is applied to the gates of the transistors M21 to M23.

Therefore, when the current mirror 20 is not in operation (=when the reference current I3 is off), even if the leakage currents of the transistors M18 to M20 cause voltage rises at the nodes E, F, and G, the transistors M21 to M23 When the voltages of the nodes E, F and G rise to a voltage higher than the bias voltage (=Vz) applied to each gate by the on-threshold Vth, the transistors M21 to M23 are turned on.

As a result, it is possible to prevent the voltages of the nodes E, F, and G from further rising, so that the voltage between the drain and the source of each of the transistors M14 to M16 can be suppressed below the rated voltage. It becomes possible to prevent breakdown of M16.

The drain-source voltage of each of the transistors M14 to M16 is clamped to the upper limit value (=Vz+Vth) determined using the Zener diode D5. Therefore, the breakdown voltage Vz of the Zener diode D5 should be selected so that the upper limit (=Vz+Vth) does not exceed the drain-source breakdown voltage of each of the transistors M14 to M16.

Further, when the current mirror 20 is in operation (=when the reference current I3 is on), the nodes E, F and G are fixed at a predetermined bias voltage (=Vth) by the functions of the transistors M18 to M20. Therefore, the clamp circuit 21 does not operate and the operation of the current mirror 20 is not affected.

Further, with the clamp circuit 21 of the present embodiment, even if the number of output systems (and thus protection target elements) of the current mirror 20 increases, there is no need to increase the number of Zener diodes D5. Therefore, it is possible to prevent the withstand voltage breakdown of the element to be protected with a small area.

Also, the transistors M21 to M23 functioning as clamping elements need not have a very large current capability because they only need to draw in the leakage current flowing through the transistors M18 to M20. Therefore, since the minimum size of each element is sufficient, even if it becomes necessary to increase the number of clamping elements as the number of output systems in the current mirror 20 increases, the area of the clamping circuit 21 hardly increases.

The transistors M21 to M23 corresponding to clamp elements may be replaced with pnp type bipolar transistors. Similarly, the transistors M13-M20 (including the transistors M14-M16 corresponding to the elements to be protected) forming the current mirror 20 may be replaced with npn-type bipolar transistors.

Thus, the present embodiment (FIGS. 5A and 5B) corresponds to the first embodiment (FIGS. 1A and 1B) with the polarity reversed, but can enjoy the same effects as above. be.

<Sixth embodiment>
6A and 6B are diagrams showing a sixth embodiment of the current mirror and the clamping circuit implemented therein. FIG. 6A shows the state when the current mirror is in operation (when I3 is on), and FIG. 6B shows the state when the current mirror is stopped (when I3 is off).

The clamp circuit 21 of this embodiment is based on the fifth embodiment (FIGS. 5A and 5B) and includes a diode-connected N-channel MOS field effect transistor M24 in place of the Zener diode D5. That is, the source of the transistor M24 is connected to the ground terminal, and the drain and gate of the transistor M24 are all connected to the gates of the transistors M21 to M23.

In this case, an arbitrary bias voltage (=Vth) determined using the transistor M24 is applied to each gate of the transistors M21 to M23.

Note that the on-threshold voltage Vth of the transistor M24 does not affect the operation of the current mirror 20, and when the current mirror 20 is not operating, the voltage between the drain and source of each of the transistors M14 to M16 is kept below the rated voltage. It may be arbitrarily adjusted within the limitable range.

Since the clamp circuit 21 of this embodiment does not use any Zener diodes, it is possible to make the area smaller than that of the fifth embodiment (FIGS. 5A and 5B).

Further, as shown in the balloon frame of this drawing, the diode-connected transistor is not limited to the N-channel MOS field effect transistor, but may be a P-channel MOS field effect transistor, an npn bipolar transistor, or a pnp bipolar transistor. can be used.

Thus, the present embodiment (FIGS. 6A and 6B) corresponds to the second embodiment (FIGS. 2A and 2B) with the polarity reversed, but can enjoy the same effects as above. be.

<Seventh embodiment>
7A and 7B are diagrams showing a seventh embodiment of a current mirror and a clamping circuit implemented therein. FIG. 7A shows the state when the current mirror is in operation (when I3 is on), and FIG. 7B shows the state when the current mirror is stopped (when I3 is off).

The clamp circuit 21 of this embodiment is based on the fifth embodiment (FIGS. 5A and 5B) or the sixth embodiment (FIGS. 6A and 6B), and the gates of the transistors M21 to M23 are replaced by the transistor M13. ˜M16 (hereafter referred to as node H), the current source CS4 and Zener diode D5 (or transistor M24) are omitted.

Thus, it is possible to use the voltage applied to the node H of the current mirror 20 as the gate voltage of each of the transistors M21 to M23.

Vth is applied to the node H when the current mirror 20 is in operation (=when the reference current I3 is on). Therefore, in order to turn on the transistors M21 to M23, the voltage applied to each of the nodes E, F and G must rise to 2Vth. However, since the voltages applied to the nodes E, F, and G are all fixed at Vth by the action of the transistors M18-M20, the transistors M21-M23 are not turned on.

On the other hand, when the current mirror 20 is not operating (=when the reference current I3 is off), the potential of the node H becomes an indefinite value having a fluctuation range of GND to Vth. Therefore, even if the leakage currents of the transistors M18 to M20 cause voltage rises at the nodes E, F, and G, the on-threshold potential is higher than the indefinite potential of the node H applied to the gates of the transistors M21 to M23. When the voltages of the nodes E, F and G rise to a voltage higher by Vth, the transistors M21 to M23 are turned on. As a result, the voltage between the drain and source of each of the transistors M14 to M16 is clamped within the voltage range of Vth to 2Vth, so that breakdown of the transistors M14 to M16 can be prevented.

Thus, the present embodiment (FIGS. 7A and 7B) corresponds to the third embodiment (FIGS. 3A and 3B) with the polarity reversed, but can enjoy the same effects as above. be.

<Eighth embodiment>
8A and 8B are diagrams showing an eighth embodiment of a current mirror and a clamping circuit implemented therein. FIG. 8A shows the state when the current mirror is in operation (when I3 is on), and FIG. 8B shows the state when the current mirror is stopped (when I3 is off).

The clamp circuit 21 of this embodiment is based on the seventh embodiment (FIGS. 7A and 7B), but the drains of the transistors M21 to M23 are connected to their respective gates instead of being grounded. In this manner, even when the drains of the transistors M21 to M23 are commonly connected to the respective gates, the same effects as above can be obtained.

In addition, in this embodiment, an example based on the seventh embodiment (FIGS. 7A and 7B) was given, but the fifth embodiment (FIGS. 5A and 5B) or the sixth embodiment (FIGS. 6A and 6B), the drains of the transistors M21 to M23 may be connected to their respective gates instead of being grounded.

Thus, the present embodiment (FIGS. 8A and 8B) corresponds to the fourth embodiment (FIGS. 4A and 4B) with the polarity reversed, but can enjoy the same effects as above. be.

<Generic conceptualization (ninth and tenth embodiments)>
FIG. 9A is a diagram showing a ninth embodiment of the clamp circuit (=corresponding to the general concept of the first to fourth embodiments). FIG. 9B is a diagram showing a tenth embodiment of the clamp circuit (=corresponding to the general concept of the fifth to eighth embodiments).

First, the ninth embodiment (FIG. 9A) will be described. In the clamp circuit 12 of this embodiment, a P-channel MOS field effect transistor MP1 constituting an electronic circuit is used as an element to be protected. The source of transistor MP1 is connected to node n11. Also, the drain of the transistor MP1 is connected to the node n12. Note that the node n12 is a node that becomes high impedance when the electronic circuit is not in operation if the clamp circuit 12 is not present.

When applied to the first to fourth embodiments described above, the electronic circuit including the transistor MP1 corresponds to the current mirror 10, the transistor MP1 corresponds to each of the transistors M2 to M4, and the node n11 is applied to the input voltage VIN. , and node n12 corresponds to nodes A, B, and C, respectively.

The clamp circuit 12 also has an N-channel MOS field effect transistor MN1 as a clamp element for limiting the voltage between the drain and source of the transistor MP1 when the electronic circuit described above is not in operation. The source of transistor MN1 is connected to node n12. The drain of transistor MN1 is connected to node n13. The gate of transistor MN1 is connected to node n14.

When applied to the first to fourth embodiments described above, the transistor MN1 corresponds to the transistors M9 to M11, respectively. Note that the node n13 may be connected to the node n11, or may be connected to the node n14, for example. The former connection form corresponds to the above-mentioned first to third embodiments, and the latter connection form corresponds to the above-mentioned fourth embodiment. Also, the node n14 may be connected to a bias voltage application terminal determined by using, for example, a Zener diode or a diode-connected transistor, or may be connected to the gate of the transistor MP1. The former connection form corresponds to the above-mentioned first or second embodiment, and the latter connection form corresponds to the above-mentioned third or fourth embodiment.

Appropriate voltages must be applied to the nodes n13 and n14 to turn off the transistor MN1 when the electronic circuit is in operation and to turn on the transistor MN1 when the electronic circuit is not in operation.

Regarding the above application conditions, the voltage applied to the node n11 is V1, the voltage applied to the node n12 during the operation of the electronic circuit is V2, the voltage applied to the node n13 is V3, the voltage applied to the node n14 is V4, Assuming that the on-threshold voltage of the transistor MN1 is Vth and the breakdown voltage between the drain and source of the transistor MP1 is Vmax, (1) V4≦V2+Vth, (2) V3>V4−Vth, and (3) V1−(V4−Vth) )<Vmax holds.

By satisfying the conditional expression (1), the transistor MN1 is turned off during the operation of the electronic circuit, so that the clamp circuit 12 does not affect the operation of the electronic circuit.

Further, by satisfying the conditional expression (2), the transistor MN1 is turned on when the electronic circuit is not in operation, so the node n12 does not become high impedance.

Further, by satisfying the conditional expression (3), breakdown of the transistor MP1 can be prevented even when the electronic circuit is not in operation.

For example, in the first embodiment described above, V1=VIN, V2=VIN-Vth, V3=VIN, and V4=VIN-Vz, which satisfy all of the above conditional expressions (1) to (3). . Also in the second to fourth embodiments, all conditional expressions (1) to (3) are established.

Next, a tenth embodiment (FIG. 9B) will be described. The clamp circuit 22 of this embodiment uses the N-channel MOS field effect transistor MN2 that constitutes an electronic circuit as an element to be protected. The source of transistor MN2 is connected to node n21. Also, the drain of the transistor MN2 is connected to the node n22. It should be noted that the node n22 is a node that becomes high impedance when the electronic circuit is not in operation if the clamp circuit 22 is not present.

When applied to the above fifth to eighth embodiments, the electronic circuit including the transistor MN2 corresponds to the current mirror 20, the transistor MN2 corresponds to each of the transistors M14 to M16, the node n21 corresponds to the ground terminal, and the node n22 correspond to nodes E, F and G, respectively.

The clamp circuit 22 also has a P-channel MOS field effect transistor MP2 as a clamp element for limiting the voltage between the drain and source of the transistor MN2 when the electronic circuit is not in operation. The source of transistor MP2 is connected to node n22. The drain of transistor MP2 is connected to node n23. The gate of transistor MP2 is connected to node n24.

When applied to the fifth to eighth embodiments, the transistor MP2 corresponds to each of the transistors M21 to M23. Note that the node n23 may be connected to the node n21, or may be connected to the node n24, for example. The former connection form corresponds to the previously mentioned fifth to seventh embodiments, and the latter connection form corresponds to the previously mentioned eighth embodiment. Also, the node n24 may be connected to a bias voltage application terminal determined by using, for example, a Zener diode or a diode-connected transistor, or may be connected to the gate of the transistor MN2. The former connection form corresponds to the above fifth or sixth embodiment, and the latter connection form corresponds to the above seventh or eighth embodiment.

Appropriate voltages must be applied to the nodes n23 and n24 so that the transistor MP2 is turned off when the electronic circuit is in operation and the transistor MP2 is turned on when the electronic circuit is not in operation.

Regarding the above application conditions, the voltage applied to the node n21 is V1, the voltage applied to the node n22 during the operation of the electronic circuit is V2, the voltage applied to the node n23 is V3, the voltage applied to the node n24 is V4, Assuming that the on-threshold voltage of the transistor MP2 is Vth and the breakdown voltage between the drain and source of the transistor MN2 is Vmax, (1) V4≧V2−Vth, (2) V3<V4+Vth, and (3) (V4+Vth)−V1< Vmax is established.

By satisfying the conditional expression (1), the transistor MP2 is turned off during the operation of the electronic circuit, so that the clamp circuit 22 does not affect the operation of the electronic circuit.

Further, by satisfying the conditional expression (2), the transistor MP2 is turned on when the electronic circuit is not in operation, so the node n22 does not become high impedance.

Further, by satisfying the conditional expression (3), breakdown of the transistor MN2 can be prevented even when the electronic circuit is not in operation.

For example, in the fifth embodiment described above, V1=GND, V2=Vth, V3=GND, and V4=Vz, satisfying all of the above conditional expressions (1) to (3). Also in the sixth to eighth embodiments, all conditional expressions (1) to (3) are established.

In this way, the application of the clamp circuits 12 and 22 is not limited to the current mirrors 10 and 20 described above, but general electronic circuits (such as cascode circuits) having nodes that can become high impedance without the clamp circuits. It can be widely applied to

Moreover, the elements to be protected (transistors MP1 and MN2) and the clamp elements (transistors MN1 and MP2) are not limited to MOS field effect transistors, and may be replaced with bipolar transistors. That is, the transistors MP1 and MP2 may each be a pnp bipolar transistor. Also, the transistors MN1 and MN2 may each be an npn-type bipolar transistor.

<Other Modifications>
In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is not limited to the above-described embodiments. It is to be understood that a range and equivalents are meant to include all changes that fall within the range.

The invention disclosed in this specification is applicable to products for various applications (in particular, products that require high withstand voltage), such as in-vehicle products, desktop PCs, notebook PCs, tablet terminals, white goods, industrial equipment, and office equipment. general electronic circuits).

10, 20, 100 Current mirror 11, 21 Clamp circuit A to E, n11 to n14, n21 to n24 Node CS1 to CS4 Current source D1 to D5 Zener diode M1 to M8, M12, M21 to M23, MP1, MP2 PMOSFET
M9-M11, M13-M20, M24, MN1, MN2 NMOSFETs

Claims (10)

A clamp circuit in which a first transistor of a first conductivity type connected between a first node and a second node as a component of an electronic circuit is an element to be protected,
a second conductivity type second transistor connected between the second node and the third node as a clamp element for limiting the voltage across the first transistor when the electronic circuit is not in operation;
a control end of the second transistor is connected to a fourth node;
the second node is a node that becomes high impedance when the electronic circuit is not operating when the clamp circuit is not operating, that is, is not conducting;
Voltages are applied to the third node and the fourth node, respectively, to turn off the second transistor when the electronic circuit is in operation and to turn on the second transistor when the electronic circuit is not in operation. A clamp circuit characterized by: The first transistor is of P-channel type or pnp type, the second transistor is of N-channel type or npn type, the voltage applied to the second node during operation of the electronic circuit is V2, and the third node is and V3 is the applied voltage of the fourth node, V4 is the applied voltage of the fourth node, Vth is the on-threshold voltage of the second transistor, and V4≤V2+Vth and V3>V4-Vth are satisfied. clamp circuit described in . The first transistor is an N-channel type or an npn type, the second transistor is a P-channel type or a pnp type, the voltage applied to the second node during operation of the electronic circuit is V2, and the third node is V3 is the applied voltage of the fourth node, V4 is the applied voltage of the fourth node, Vth is the on-threshold voltage of the second transistor, and V4≧V2−Vth and V3<V4+Vth are satisfied. clamp circuit described in . The electronic circuit is a current mirror that generates a mirror current corresponding to a reference current, and the first transistor is an output transistor that is paired with an input transistor to which the reference current is input and outputs the mirror current. 4. The clamp circuit according to any one of claims 1 to 3, which is used. The current mirror is of a multi-output type that uses a plurality of the first transistors to output the mirror current to a plurality of systems, and the second transistor is provided for each of the first transistors. 5. A clamp circuit according to claim 4, wherein the control terminals are connected in common. 6. A clamp circuit according to claim 4, wherein said current mirror has a function of turning on/off said reference current. 7. The clamp circuit according to claim 6, wherein said current mirror is of a cascode type, and said second node is fixed at a predetermined bias voltage when said reference current is on. 8. The device according to any one of claims 1 to 7, further comprising a diode or a diode-connected transistor that determines the applied voltage of the fourth node, and a current source that generates a drive current for the diode or the diode-connected transistor. or the clamp circuit according to claim 1. 8. The clamp circuit according to claim 1, wherein said fourth node is connected to a control terminal of said first transistor. 10. The clamp circuit according to claim 1, wherein said third node is connected to said first node or said fourth node.

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