JP2009044304A - Semiconductor element controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element controller capable of properly controlling a semiconductor element to be controlled even when power supply voltage decreases. <P>SOLUTION: A voltage providing circuit 18 compares a power supply voltage Vcc with a predetermined threshold voltage Vth. If Vcc≤Vth, the circuit 18 provides a virtual ground voltage Vcp as a voltage near a ground level to a ground side terminal of a pre-drive circuit 2, and if Vcc>Vth, the circuit 18 provides a difference voltage between the power supply voltage Vcc and a clamp control voltage Vgs to the ground side terminal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor element control apparatus that controls a voltage-driven semiconductor element connected between a DC power supply and a load.

For example, in a power supply circuit such as a step-down DC / DC converter, when a semiconductor switching element such as a power MOSFET is connected between the power supply and the ground, and the FET is controlled at high speed, the gate voltage is the gate voltage. -Clamp control is performed so as not to exceed the withstand voltage of the source-to-source voltage. One example of such a prior art is disclosed in Patent Document 1 (see FIG. 14).
JP-A-11-205123 (FIG. 2)

In this circuit, the gate voltage when the P-channel MOSFET M5 to be controlled is turned on is controlled to be always lower than the power supply voltage by the threshold voltage VT (2 VT) of the FETs M8 and M6. The As a result, even when the power supply voltage Vdd is lowered, the gate voltage is subjected to the above-described restrictions, and thus there is a problem that the FET: M5 cannot be sufficiently turned on.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor element control device capable of appropriately controlling a semiconductor element to be controlled even when a power supply voltage is lowered. .

  According to the semiconductor element control device of claim 1, when the power supply voltage is equal to or lower than the threshold, the voltage application circuit applies a voltage near the ground level to the ground side terminal of the drive circuit, and the power supply voltage exceeds the threshold. If there is, a difference voltage between the power supply voltage and the clamp control voltage is applied to the ground side terminal. That is, if the power supply voltage exceeds the threshold value, the voltage difference between the power supply side terminal and the conduction control terminal of the semiconductor element to be controlled becomes the clamp control voltage, and if the power supply voltage is less than the threshold value, the voltage difference is The value is close to the power supply voltage. Therefore, when the clamp control becomes unnecessary as a result of the power supply voltage being lowered, the semiconductor element to be controlled can be sufficiently turned on.

  According to the semiconductor element control device of the second aspect, the voltage generation circuit switches and outputs the voltage near the ground level and the difference voltage according to the relationship between the power supply voltage and the threshold, and the voltage buffer circuit includes: A voltage corresponding to the output voltage of the voltage generation circuit is applied to the ground side terminal of the drive circuit. Therefore, the voltage applied to the ground side terminal can be switched by the output voltage of the voltage generation circuit.

  According to the semiconductor element control device of claim 3, if the power supply voltage does not reach the operation start voltage of the constant current circuit, the potential at the common connection point with the resistance element becomes a voltage near the ground level, and the power supply voltage is the operation voltage. When the start voltage is reached, the potential at the common connection point becomes a value obtained by subtracting the voltage drop in the resistance element from the power supply voltage. Therefore, the threshold can be set according to the operation start voltage of the constant current circuit, and the clamp control voltage can be set by the resistance value of the resistance element and the current value of the constant current circuit.

  According to the semiconductor element control device of the fourth aspect, when the power supply voltage reaches the operation start voltage of the constant current circuit, the potential at the common connection point with the Zener diode becomes a value obtained by subtracting the Zener voltage from the power supply voltage. Therefore, the clamp control voltage can be set by the Zener voltage.

  According to the semiconductor element control device of claim 5, the operational amplifier constituting the voltage buffer circuit is connected to the semiconductor element connected between the ground-side terminal of the drive circuit and the ground according to the output voltage of the voltage generation circuit. Since the potential of the ground side terminal is controlled by controlling the state, the potential of the ground side terminal can be set according to the output voltage of the voltage generation circuit.

  According to the semiconductor element control device of the sixth aspect, the conduction of the second semiconductor element constituting the voltage buffer circuit is controlled by the output voltage of the voltage generation circuit, and the first semiconductor element according to the conduction state of the second semiconductor element. Is controlled. Therefore, the potential of the ground-side terminal can be controlled to the potential obtained by adding the constant voltage applied by the second semiconductor element to be conducted to the output voltage.

  According to the semiconductor element control device of the seventh aspect, when the power supply voltage falls below a lower limit value set to a level equal to or lower than the threshold value, the conduction control circuit is interposed between the ground side terminal of the drive circuit and the ground. The connected semiconductor element is made conductive. Therefore, even when the voltage applying circuit cannot apply a sufficiently low voltage, a sufficiently low voltage can be applied to the ground side terminal of the drive circuit by the action of the auxiliary voltage applying circuit.

  According to the semiconductor element control device of claim 8, since the conduction control circuit has a hysteresis characteristic in the conduction control of the semiconductor element constituting the auxiliary voltage application circuit, when the power supply voltage fluctuates near the lower limit value, The semiconductor element can be prevented from being frequently interrupted.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 schematically shows the overall configuration of a semiconductor element control apparatus. A series circuit of a P-channel MOSFET (semiconductor element, transistor) 1 and a load (not shown) is connected between the power supply Vcc and the ground. In this case, the load is a DC motor, a lamp, other inductors, or the like. A gate voltage is applied to the gate (conduction control terminal) of the FET 1 by a pre-drive circuit (drive circuit) 2 to control ON / OFF of the FET 1, that is, energization to the load.

  The power supply side terminal of the pre-drive circuit 2 is connected to the power supply Vcc, and the ground side terminal is connected to the ground via a voltage variable clamp circuit 3 (hereinafter simply referred to as a clamp circuit). The clamp circuit (voltage buffer circuit) 3 applies a virtual ground voltage Vcp to the ground side terminal of the pre-drive circuit 2. A series circuit of a resistance element 4, an N-channel MOSFET 5, and a resistance element 6 is connected between the power source Vcc and the ground. The drain of the FET 5 is connected to the input terminal of the pre-drive circuit 2.

  A zener diode 7 for overvoltage protection is connected between the power supply Vcc and the ground side terminal of the pre-drive circuit 2, and a clamping diode is connected between the anode of the zener diode 7 and the drain of the FET 5. 8 is connected. A control signal Vin is supplied to the gate of the FET 5 from the outside. When the control signal Vin becomes a high level, the FET 5 is turned on, the input terminal of the pre-drive circuit 2 becomes a low level, and the FET 1 is turned on.

  A voltage monitor circuit (voltage generation circuit) 9 is connected between the power supply Vcc and the ground. The voltage monitor circuit 9 changes the reference voltage Vref output to the clamp circuit 3 according to the voltage level of the power supply Vcc. The clamp circuit 3 responds to the reference voltage Vref. The virtual ground voltage Vcp applied to the ground side terminal is changed.

  FIG. 2 shows a specific configuration example of the pre-drive circuit 2. The pre-drive circuit 2 is configured by connecting in series a CMOS inverter composed of P and N channel MOSFETs 10P and 10N and a CMOS inverter composed of P and N channel MOSFETs 11P and 11N. The sources of the FETs 10P and 11P are connected to the power supply Vcc, and the virtual ground voltage Vcp is applied to the sources of the FETs 10N and 11N by the clamp circuit 3. The gates of the FETs 10P and 10N are connected to the drain of the FET 5, and the drains of the FETs 11P and 11N are connected to the gate of the FET 1.

3A and 3B show specific configuration examples of the voltage monitor circuit 9 (a, b). In FIG. 3A, a series circuit of a resistance element 12 and a constant current circuit 13 is connected between a power source Vcc and the ground, and a reference voltage Vref applied to the clamp circuit 3 by a common connection point between them is shown in FIG. Become. FIG. 3B is a diagram in which the resistance element 12 of FIG. 3A is replaced with a Zener diode 14. These voltage monitor circuits 9 set the threshold voltage Vth to 8 V when the maximum voltage of the power supply Vcc is about 16 V, for example.
Vcc> Vth → Vref = Vcc−Vgs (1)
Vcc ≦ Vth → Vref ≒ 0 (2)
The reference voltage Vref is changed so that Here, the voltage Vgs is a voltage applied as the gate-source voltage of the FET 1 when the pre-drive circuit 2 turns on the FET 1, and exceeds the gate-source breakdown voltage Vgs (max) (for example, 10 V) of the FET 1. A voltage for clamping the gate voltage (clamp control voltage) so as not to be set, for example, 8V.

  That is, in the configuration of FIG. 3, when Vcc ≦ Vth, the constant current circuit 13 is configured not to pass current, and as a result, the reference voltage Vref≈0. When Vcc> Vth, in (a), the voltage drop generated in the resistance element 12 by the constant current flowing through the constant current circuit 13 is determined to correspond to the voltage Vgs. In (b), the zener diode 14 Zener voltage Vz = Vgs.

4A and 4B show specific configuration examples of the clamp circuit 3 (a, b). FIG. 4A shows a configuration in which the non-inverting input terminal and the output terminal of the operational amplifier 16 are connected to the drain and gate of the N-channel MOSFET 15, and the voltage monitoring circuit is connected to the inverting input terminal of the operational amplifier 16. 9 gives a reference voltage Vref. FIG. 4B shows an NPN transistor 17 connected in place of the FET 15 in FIG.
In the above configuration, the clamp circuit 3 and the voltage monitor circuit 9 constitute a voltage application circuit 18. Further, the semiconductor device control device 19 is configured by removing the FET 1 from the above configuration.

  Next, the operation of the present embodiment will be described with reference to FIG. FIG. 5 shows changes in the virtual ground voltage Vcp applied by the clamp circuit 3 when the power supply voltage Vcc changes in the range of 16V to 0V. When the power supply voltage Vcc exceeds the threshold voltage Vth set in the voltage monitor circuit 9, the reference voltage Vref applied to the clamp circuit 3 is Vref = Vcc−Vgs as shown in the above equation (1). The reference voltage Vref is output as a virtual ground voltage Vcp by the operation of the operational amplifier 16 of the clamp circuit 3.

As a result, when the control signal Vin becomes high level and the input terminal of the pre-drive circuit 2 becomes low level, the internal output side FETs 11P and 11N are turned OFF and ON, respectively, so that the gate voltage of the FET 1 (M1) is almost virtual. It becomes equal to the ground voltage Vcp. At this time, the gate-source (power supply side terminal) voltage of the FET 1 is Vcc− (Vcc−Vgs) = Vgs, and the FET 1 is turned on while being clamped at a voltage difference of 8V.
Since the above state is always maintained when the FET 1 is turned on while Vcc> Vth is established, the source-gate voltage of the FET 1 is always Vcp = 8 V, and the voltage clamping function is effective.

  When the power supply voltage Vcc becomes equal to or lower than the threshold voltage Vth, the reference voltage Vref becomes Vref≈0 as shown in the above equation (2), so that the virtual ground voltage Vcp is also output as Vcp≈0. At this time, the source-gate voltage when the FET 1 is turned on is substantially the power supply voltage Vcc.

  As a result, the relationship between the power supply voltage Vcc and the virtual ground voltage Vcp is as shown in FIG. In FIG. 5, the virtual ground voltage Vcp is shown to rise while the power supply voltage Vcc is in the vicinity of 0V to 1.5V. In this section, the operational amplifier 16 is shown in FIG. This indicates that the voltage VT necessary to turn on the FET 15 cannot be output, and the virtual ground voltage Vcp is in a high impedance state. Therefore, in the case of FIG. 4B, the voltage range for the high impedance state is around 0V to 0.6V.

  As described above, according to this embodiment, the voltage applying circuit 18 compares the power supply voltage Vcc with the predetermined threshold voltage Vth, and if Vcc ≦ Vth, the ground side terminal of the pre-drive circuit 2 is near the ground level. A virtual ground voltage Vcp, which is a voltage of the above, is applied, and if Vcc> Vth, a difference voltage between the power supply voltage Vcc and the clamp control voltage Vgs is applied to the ground side terminal. Accordingly, when the FET 1 is turned on under the condition that the active clamp control is not required due to the drop of the power supply voltage Vcc, the clamp control is invalidated and the gate-source voltage can be made substantially equal to the power supply voltage Vcc. The FET 1 can be sufficiently turned on.

  Further, the voltage applying circuit 18 is constituted by the voltage monitor circuit 9 and the clamp circuit 3, and the virtual ground voltage Vcp applied to the ground side terminal of the pre-drive circuit 2 is switched according to the voltage output from the voltage monitor circuit 9. did. If the voltage monitor circuit 9a is constituted by a series circuit of the resistance element 12 and the constant current circuit 13, the threshold voltage Vth is set according to the operation start voltage of the constant current circuit 13, and the resistance value of the resistance element 12 is set. And the current value of the constant current circuit 13 can set the clamp control voltage Vgs. If the voltage monitor circuit 9b is constituted by a series circuit of the Zener diode 14 and the constant current circuit 13, the clamp control voltage Vgs can be set by the Zener voltage Vz.

  Then, the clamp control circuit 3 controls the conduction state of the FET 15 or the transistor 17 connected between the ground side terminal of the pre-drive circuit 2 and the ground according to the reference voltage Vref to control the ground side terminal. Since the potential is controlled, the potential of the ground-side terminal can be set according to the reference voltage Vref.

(Second embodiment)
6 to 9 show a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof will be omitted. Hereinafter, different parts will be described. As shown in FIG. 6, in the semiconductor element control device 21 of the second embodiment, the clamp circuit 3 and the voltage monitor circuit 9 are composed of a clamp circuit (voltage application circuit, voltage buffer circuit) 22, a voltage monitor circuit (voltage generation circuit, Auxiliary voltage application circuit) 23 is replaced with an N-channel MOSFET (semiconductor element, auxiliary voltage application circuit) 24 in parallel with the clamp circuit 22. Further, the voltage monitor circuit 9 is replaced with a voltage monitor circuit 23, and ON / OFF of the FET 24 is controlled by the voltage monitor circuit 23. Other configurations are the same as those in the first embodiment.

  FIGS. 7A and 7B show a specific configuration of the voltage monitor circuit 23 (a, b). The portion for generating and outputting the reference voltage Vref is configured in the same manner as the voltage monitor circuit 9, and the FET 24 (M2 ) Has been added. In FIG. 7A, a series circuit of resistance elements 25 and 26 is connected between the power source Vcc and the ground, and the common connection point between them is connected to the inverting input terminal of the comparator 27. A reference voltage Vref1 for comparison is applied to the non-inverting input terminal of the comparator 27, and the FET 24 is controlled by the output signal of the comparator 27. In FIG. 7B, a Zener diode 28 is disposed in place of the resistance element 25.

  FIGS. 8A and 8B show a specific configuration example of the clamp circuit 22 (a, b). In FIG. 8A, a parallel circuit of a P-channel MOSFET 30 (second semiconductor element) and a resistance element 31 is connected in parallel to an N-channel MOSFET 29 (first semiconductor element). Connected to the gate. A reference voltage Vref is applied to the gate of the FET 30. When the FET 1 is turned off by the pre-driver circuit 2, the gate voltage is substantially the power supply voltage Vcc. When the pre-driver circuit 2 turns on the FET 1 from that state, the ground-side voltage of the pre-driver circuit 2 maintains a high voltage to some extent due to the gate capacitance of the FET 1.

  Therefore, when the reference voltage Vref applied to the clamp circuit 22 (a) is ≈0, the FET 30 is turned on and the FET 29 is also turned on, but the virtual ground voltage Vcp at this time is almost equal if it is assumed that the FET 22 does not exist. It becomes the threshold voltage VT of the FET 30. Even when the reference voltage Vref is given by (Vcc−Vgs), the virtual ground voltage Vcp becomes (Vcc−Vgs + VT).

  FIG. 8B is a diagram in which an NPN transistor 32 (first semiconductor element) and a PNP transistor 33 (second semiconductor element) are connected in place of the FETs 29 and 30 in FIG. In this case, the virtual ground voltage Vcp is obtained by replacing the threshold voltage VT with the base-emitter voltage VF. In any case, the FET 24 is controlled to turn on when the power supply voltage Vcc is equal to or lower than the threshold voltage Vth (= lower limit value).

Next, the operation of the second embodiment will be described with reference to FIG. For example, assuming that the FET 1 is subjected to PWM control with a carrier frequency on the order of several hundred kHz, the clamp circuit 3 using the operational amplifier 16 as in the first embodiment has a limitation in high-speed operation and is difficult to follow. There is a case.
Therefore, in the second embodiment, an operational amplifier is not used for the clamp circuit 22, but FETs 29 and 30 or bipolar transistors 32 and 33 are used to sufficiently cope with high-speed operation. However, on the other hand, since the minimum level of the virtual ground voltage Vcp applied to the pre-drive circuit 2 is the voltage VT or VF as described above, when the clamp control is invalidated in the voltage range of Vcc ≦ Vth, the FET 1 The drive voltage range is narrowed.

  In order to improve the above problem, the FET 24 is connected in parallel to the clamp circuit 22 and is turned on in the voltage range of Vcc ≦ Vth, so that the minimum level of the virtual ground voltage Vcp is near the ground level as in the first embodiment. It is trying to become. As a result, the relationship between the power supply voltage Vcc and the virtual ground voltage Vcp is as shown in FIG. 9, and in the voltage range of Vcc> Vth, the gate-source voltage when the FET 1 is turned on is [Vgs−VT (or VF)].

As described above, according to the second embodiment, the clamp circuit 22 is configured to be able to operate at a higher speed, and the voltage monitor circuit 23 sets the FET 24 when the power supply voltage Vcc becomes equal to or lower than the threshold value Vth. I tried to turn it on. Therefore, even if the configuration of the clamp circuit 22 is difficult to apply a sufficiently low voltage, a sufficiently low voltage can be applied to the ground-side terminal of the pre-drive circuit 2 by the action of the FET 24, and the FET 1 It can be avoided that the drive voltage range is narrowed.
In addition, the clamp circuit 22 controls the conduction of the FET 30 (or the transistor 33) with the reference voltage Vref, and controls the conduction of the FET 29 (or the transistor 32) according to the conduction state of the FET 30, so that in the voltage range of Vcc> Vth. The potential of the ground side terminal can be controlled to a potential obtained by adding the constant voltage VT (or VF) generated at the time of conduction to the reference voltage Vref.

(Third embodiment)
FIG. 10 is a third embodiment of the present invention and shows a different configuration example of the voltage monitor circuit. The voltage monitor circuit (voltage applying circuit, voltage generating circuit, auxiliary voltage applying circuit) 41 does not use the comparator 27 as in the second embodiment, and outputs the gate drive signal of the FET 24 and the circuit portion that outputs the reference voltage Vref. And a circuit portion to be integrated. A series circuit of a resistance element 42, a Zener diode 43, and a constant current circuit 44 is connected between the power source Vcc and the ground. The common connection point between the Zener diode 43 and the constant current circuit 44 is the NPN transistor 45. Connected to the base. The collector of the transistor 45 is connected to the power source Vcc, and the emitter is connected to the ground via the constant current circuit 46 and outputs the reference voltage Vref.

  A series circuit of a PNP transistor 47 and resistance elements 48 and 49 is connected between the power source Vcc and the ground, and the base of the transistor 47 is connected to a common connection point between the resistance element 42 and the Zener diode 43. Has been. Further, a series circuit of a constant current circuit 50 and an NPN transistor 51 is connected between the power supply Vcc and the ground, and the base of the transistor 51 is connected to a common connection point of the resistance elements 48 and 49. The gate drive signal of the FET 24 is output from the collector of the transistor 51.

Next, the operation of the third embodiment will be described. When Vcc ≦ Vth, the Zener diode 43 is not turned on, so that the transistors 45, 47, and 51 are all turned off. Therefore, the reference voltage Vref becomes ≈0, the gate drive signal of the FET 24 becomes high level, and the FET 24 is turned on. On the other hand, when Vcc> Vth, the Zener diode 43 is turned on, so that the transistors 45, 47, and 51 are all turned on. Therefore, the reference voltage Vref becomes [Vcc−Vgs (voltage drop of the resistance element 42)], the gate drive signal of the FET 24 becomes low level, and the FET 24 is turned off. In this case, the clamp control voltage Vgs is the sum of the voltage drop of the resistance element 42, the Zener voltage Vz of the Zener diode 43, and the base-emitter voltage VF of the transistor 45.
Also in the case of the third embodiment configured as described above, the same effect as in the first and second embodiments can be obtained.

(Fourth embodiment)
FIGS. 11 and 12 show a fourth embodiment of the present invention, and different parts from the third embodiment will be described. The voltage monitor circuit (voltage application circuit, auxiliary voltage application circuit, conduction control circuit) 52 of the fourth embodiment gives the voltage monitor circuit 41 of the third embodiment a hysteresis characteristic for the output of the gate drive signal of the FET 24. It is comprised as follows.

  A resistance element 53 is inserted between the common connection point of the resistance elements 48 and 49 and the base of the transistor 51, and between the common connection point and the ground, the resistance element 54 and the NPN transistor 55 are inserted. Are connected in series. A series circuit of a resistor element 56 and an NPN transistor 57 is connected between the power supply Vcc and the ground. The base of the transistor 57 is connected to the common connection point via the resistance element 58.

Next, the operation of the fourth embodiment will be described with reference to FIG. In the voltage monitor circuit 41 of the third embodiment, the current I1 to be turned on to turn on the transistor 51 is [I1 = VF / R1] where the resistance value of the resistance element 49 is R1. On the other hand, in the voltage monitor circuit 52, the current I2 that flows to turn on the transistor 51 is turned on at the same time because the transistors 57 and 55 are turned on at the same time. / (R1 // R2)] (for example, about several tens of mA). Therefore, the voltage for turning on the transistor 51 and turning off the FET 24 increases as the current increases.
As a result, as shown in FIG. 12, a hysteresis characteristic is given to the voltage range in which the FET 24 is turned on. By giving such characteristics, when the power supply voltage Vcc changes near the threshold Vth, it is possible to prevent the ON / OFF of the FET 24 from being frequently switched according to the change.

(5th Example)
FIG. 13 shows a fifth embodiment of the present invention. The fifth embodiment assumes that the clamp circuit 22 used in the semiconductor element control device 21 of the second embodiment is replaced with a clamp circuit (voltage application circuit, voltage buffer circuit) 61. As shown in FIGS. 13A and 13B, the clamp circuit 61 (a, b) is composed of a combination of an operational amplifier 62 and a P-channel MOSFET (semiconductor element) 63 or a PNP transistor (semiconductor element) 64. The

  When the clamp circuit 61 is combined with the semiconductor element control device 21 of the second embodiment, since the operational amplifier 62 is included, the adaptability to high speed operation is slightly lowered. However, unlike the case where the clamp circuit 22 is used, the virtual clamp voltage Vcp does not become [+ VT (or VF)] with respect to the reference voltage Vref. Therefore, in FIG. 9, since the virtual clamp voltage Vcp matches the reference voltage Vref indicated by the broken line, the drive voltage range of the FET 1 can be expanded.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
The protective Zener diode 7 and the clamping diode 8 of the FET 5 may be provided as necessary.
The power supply voltage Vcc, the withstand voltage of the semiconductor element to be controlled, the threshold voltage Vth, and the like may be appropriately changed according to individual designs.
When the threshold voltage Vth and the clamp control voltage are set to the same voltage, the low current circuit 13 in FIG. 3B may be replaced with a resistance element.
In the second embodiment, the lower limit value for turning on the FET 24 may be set to be lower than the threshold voltage Vth.

1 is a diagram schematically illustrating an entire configuration of a semiconductor element control apparatus according to a first embodiment of the present invention. Diagram showing a specific configuration example of the pre-drive circuit The figure which shows the concrete structural example of the voltage monitor circuit The figure which shows the concrete structural example of a clamp circuit The figure which shows the change of the virtual ground voltage Vcp accompanying the change of the power supply voltage Vcc. FIG. 1 equivalent view showing a second embodiment of the present invention. 3 equivalent figure 4 equivalent diagram Figure equivalent to FIG. FIG. 3 equivalent view showing a third embodiment of the present invention. FIG. 10 equivalent view showing the fourth embodiment of the present invention. Fig. 9 equivalent FIG. 8 equivalent view showing the fifth embodiment of the present invention. 1 equivalent diagram showing the prior art

Explanation of symbols

  In the drawings, 1 is a P-channel MOSFET (semiconductor element), 2 is a pre-drive circuit (drive circuit), 3 is a voltage variable clamp circuit (voltage buffer circuit), 9 is a voltage monitor circuit (voltage generation circuit), and 12 is a resistor Element, 13 is a constant current circuit, 14 is a Zener diode, 15 is an N-channel MOSFET (semiconductor element), 16 operational amplifier, 17 is an NPN transistor (semiconductor element), 18 is a voltage applying circuit, 19 and 21 are semiconductor element control devices, 22 is a voltage variable clamp circuit (voltage application circuit, voltage buffer circuit), 23 is a voltage monitor circuit (auxiliary voltage application circuit), 24 is an N channel MOSFET (semiconductor element, auxiliary voltage application circuit), and 29 is an N channel MOSFET ( First semiconductor element), 30 is a P-channel MOSFET (second semiconductor element), 31 is a resistance element, 32 is PN transistor (first semiconductor element), 33 is a PNP transistor (second semiconductor element), 41 is a voltage monitor circuit (voltage application circuit, auxiliary voltage application circuit), 52 is a voltage monitor circuit (voltage application circuit, auxiliary voltage application circuit) , 61 is a voltage variable clamp circuit (voltage application circuit, voltage buffer circuit), 62 is an operational amplifier, 63 is a P-channel MOSFET (semiconductor element), and 64 is a PNP transistor (semiconductor element).

Claims (8)

For controlling a voltage-driven semiconductor element connected between a DC power source and a load, and when the semiconductor element is in a conductive state, in a semiconductor element control device that performs clamp control as necessary,
A driving circuit for applying a driving voltage to a conduction control terminal of the semiconductor element in accordance with a control signal given from the outside;
The voltage of the power supply is compared with a predetermined threshold value. When the power supply voltage is less than or equal to the threshold value, a voltage near the ground level is applied to the ground side terminal of the drive circuit, and the power supply voltage exceeds the threshold value. And a voltage applying circuit for applying a voltage difference between the power supply voltage and the clamp control voltage to the ground side terminal. The voltage application circuit is:
According to the relationship between the power supply voltage and the threshold, a voltage generation circuit that switches and outputs the voltage near the ground level and the difference voltage;
2. The semiconductor element control device according to claim 1, further comprising a voltage buffer circuit that applies a voltage corresponding to an output voltage of the voltage generation circuit to a ground-side terminal of the drive circuit.   3. The semiconductor element control device according to claim 2, wherein the voltage generation circuit is configured by a series circuit of a resistance element and a constant current circuit connected between the power source and the ground.   3. The semiconductor element control device according to claim 2, wherein the voltage generation circuit is configured by a series circuit of a Zener diode connected between the power source and the ground and a constant current circuit. The voltage buffer circuit includes:
A semiconductor element connected between the ground side terminal of the drive circuit and the ground;
5. The operational amplifier according to claim 2, further comprising: an operational amplifier that controls a potential of the ground-side terminal by controlling a conduction state of the semiconductor element according to an output voltage of the voltage generation circuit. The semiconductor element control apparatus described in 1. The voltage buffer circuit includes:
A first semiconductor element connected between a ground side terminal of the drive circuit and the ground;
A series circuit of a second semiconductor element and a resistance element, which are connected in parallel to the first semiconductor element and are complementary to the element,
The common connection point of the series circuit is connected to a conduction control terminal of the first semiconductor element, and an output voltage of the voltage generation circuit is applied to the conduction control terminal of the second semiconductor element. The semiconductor element control apparatus in any one of thru | or 4. A semiconductor element connected between the ground side terminal of the drive circuit and the ground;
7. An auxiliary voltage applying circuit comprising: a conduction control circuit for conducting the semiconductor element when the power supply voltage falls below a lower limit value set to a level equal to or lower than the threshold value. The semiconductor element control apparatus in any one of.   8. The semiconductor element control device according to claim 7, wherein the conduction control circuit is configured to give hysteresis characteristics to conduction control of the semiconductor element.

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