JP2008244348A - Ceramic material used for protection to electrically excess stress, and low capacitance multilayer chip varistor using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low capacitance multilayer chip varistor lower in capacitance than 0.5 pF at 1 MHz. <P>SOLUTION: The low capacitance multilayer chip varistor is characterized in that it comprises a ceramic body, external electrodes arranged in 2 ends of the ceramic body, and internal electrodes arranged in it, in that the ceramic body includes an inorganic glass of 3-50% weight percentage, and a semi-conductive particle or a conductive particle of 50-97 weight percentage over 0.1 μm in particle size, in that a layer of inorganic glass film covers the surface of the semi-conductive particle or the conductive particle, in that the inorganic glass film contains the semi-conductive particle or the conductive particle sized in submicron smaller than 1 micron or nanometer, and in that a content of the semi-conductive particle or the conductive particle is less than 20 weight percentage of content of the inorganic glass. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a low capacitance multilayer chip varistor, and more particularly, a low capacitance multilayer chip varistor having a capacitance of less than 0.5 pF at 1 MHz to suppress electrical overstress and electrostatic shock and protect electronic circuits. About.

  The electronics industry trend is towards higher working frequencies and smaller sizes. Therefore, the need to use varistors to protect ICs from damage due to electrical overstress is increasing for high frequency applications.

Conventional varistors are mainly composed of ZnO or SrTiO ₃ and are completed by sintering after the oxide is added. Taking a ZnO varistor as an example, it is composed of ZnO and Bi, Sb, Si, Co, Mn, Co, Mn, Cr and the like. At high temperatures exceeding 1000 ° C., Bi ₂ O ₃ and oxides such as Co, Mn, and Cr form grain boundaries between ZnO particles having a microstructure such as a grain boundary barrier capacitor. Therefore, varistors composed of such materials have higher capacitances ranging from tens of pF to thousands of pF. The material is also used in multilayer chip varistors, where the varistor capacitance ranges from about 3 pF to several hundred pF at 1 MHz. In high frequency circuits, the signal is distorted when the capacitance of the component to provide protection exceeds 3 pF. Therefore, the components for providing protection are not suitable for high frequency circuits.

Similarly, varistor components composed of SrTiO ₃ have capacitances in excess of several thousand pF and are not suitable for high frequency circuits. In addition, as the transmission frequency increases, the capacitance must be further reduced to prevent the signal from distortion.

US Pat. No. 5,976,420 discloses at least two oxidations selected from SiO ₂ , Bi ₂ O ₃ , PbO, B ₂ O ₃ and ZnO in an amount of 0.1 mol% to 20 mol%. Low capacitance, mainly composed of SiC containing the material, then combined with toluene and binder agent, mixed by using a ball mill to obtain a slurry, and then becomes a ceramic green sheet by using a doctor blade process And a chip-type multilayer varistor having a high nonlinear coefficient. A paste was printed on the surface of the green sheet to form internal electrodes thereon. A predetermined number of ceramic green sheets are stacked to form a layered body. The resulting layered body was bonded by pressing with constant pressure. The resulting green compact was cut into small chips. The green chip is baked at a temperature in the range of 700 ° C. to 1100 ° C. to withstand an electrostatic shock and complete a ceramic multilayer chip varistor having a surge voltage suppressing power and a high nonlinear coefficient of 10 to 20. The chip has a capacitance in the range of 10 pF to 40 pF which is not very high but much higher than 3 pF and is therefore not suitable for use in high frequency circuits.

  U.S. Patent No. 6,251,513 disclosed components for providing protection. The constituent material comprises conductive particles and semiconductive particles having a particle size of less than 10 μm, which are mixed with a polymer insulating binder to form a paste-like material. The left and right conductive electrodes are printed on the same surface of the insulating substrate, and the paste-like substance is filled in the gap between the two conductive electrodes and then baked. Its capacitance is low and less than 0.25 pF at 1 MHz, but the components are suitable for providing protection for high frequency circuits. The insulating material is composed of a polymer material, and heat generated by electrostatic shock or surge electrical overstress carbonizes the polymer material, making the component conductive and losing its protective effect on the electronic circuit or component. Is meant. Therefore, this component does not have good electrostatic shock withstandability and its lifetime is short. When static electricity of direct contact 8KV is applied, a failure occurs only after 500 electrostatic shocks.

  One object of the present invention is to provide a low capacitance multilayer chip varistor with a capacitance of less than 0.5 pF at 1 MHz. The varistor has surge resistance and protective effect against static electricity, and more specifically, has the characteristics to withstand electrostatic shock over thousands of 8KV, and maintains its original function even after thousands of electrostatic shocks To do.

  Another object of the present invention is to provide a protective material against electrical overstress with small holes, said material between the positive and negative electrodes to suppress surge voltage and electrostatic shock. Used in. The material comprises 3 to 50 weight percent inorganic glass and 50 to 97 weight percent semiconductive or conductive particles having a particle size greater than 0.1 μm. In the composition, the layer of the inorganic glass film covers the surface of the semiconductive particles or the conductive particles. The inorganic glass film is composed of semi-conductive or conductive sub-micron particles, that is, nanometer particles having a size of less than 1 micron. The content of semiconductive particles or conductive particles is less than 20 weight percent of the content of inorganic glass.

  Yet another object of the present invention is to provide a low capacitance multilayer chip varistor with a capacitance of less than 0.5 pF at 1 MHz. The varistor includes a ceramic body, a pair of external electrodes disposed at two ends of the ceramic body, and a plurality of internal electrodes disposed therein. The ceramic body is made of a protective material against electrical overstress with small holes. The material comprises 3 to 50 weight percent inorganic glass and 50 to 97 weight percent semiconductive or conductive particles having a particle size greater than 0.1 μm. In the composition, the layer of inorganic glass film covers the surface of the semiconductive particles or conductive particles. The inorganic glass film is made of sub-micron or nanometer particle semi-conducting or conductive material that is less than 1 micron in size. The content of semiconductive particles or conductive particles is less than 20 weight percent of the content of inorganic glass.

  Yet another object of the present invention is to provide a multilayer chip varistor with low capacitance and low breakdown voltage. The trigger voltage of the varistor is the thickness of the ceramic green sheet, the sintering temperature of the ceramic compact, the glass layer thickness of the grain boundary, the size of the conductive particles or semiconductive particles, and the nanometer-sized conductivity for sub-dispersion. It can be controlled by the amount of particles or semiconductive particles added.

  That is, the first invention of the present application is a protective material having a small hole for protecting against electrical overstress, and the material is positive for suppressing transient surge voltage and electrostatic shock. Applied between an electrode and a negative electrode, the material comprises 3 to 50 weight percent inorganic glass and 50 to 97 weight percent semiconductive or conductive particles having a particle size greater than 0.1 microns. It is a gist that the layer of the inorganic glass film is a protective material against electrical overstress, which covers the surface of the semiconductive particles or conductive particles.

  In the second invention of the present application, the inorganic glass film contains sub-micron or nanometer semiconductive particles or conductive particles smaller than 1 micron, and the content of the semiconductive particles or conductive particles is The gist is that the material is a protective material against electrical overstress according to the first invention of the present application, which is less than 20 weight percent of the content of the inorganic glass.

  In addition, according to a third invention of the present application, the inorganic glass includes one or more of silicate glass, aluminosilicate glass, borate glass, phosphate glass, lead acid glass and other inorganic acid salt glasses. The gist of the present invention is a material for protecting against electrical overstress according to the first or second invention of the present application.

According to a fourth invention of the present application, the semiconductive particles are ZnO, TiO ₂ , SnO ₂ , Si, Ge, SiC, Si—Ge alloy, InSb, GaAs, InP, GaP, ZnS, ZnSe, ZnTe, SrTiO. ₃ and BaTiO ₃ , and the conductive particles are selected from one or more of Pt, Pd, W, Au, Al, Ag, Ni, Cu and alloys thereof. 2 Summary of the invention is a protective material against electrical overstress described in the invention.

  The fifth invention of the present application is a low-capacitance multilayer chip varistor having a capacitance lower than 0.5 pF at 1 MHz, wherein the varistor includes a ceramic body and external electrodes disposed at two ends of the ceramic body. The ceramic body comprises 3 to 50 weight percent inorganic glass and 50 to 97 weight percent semi-conductive or conductive particles having a particle size greater than 0.1 μm The layer of the inorganic glass film is a low-capacitance multilayer chip varistor that covers the surface of the semiconductive particles or the conductive particles.

  Further, the sixth invention of the present application is that the inorganic glass film includes sub-micron or nanometer semiconductive particles or conductive particles smaller than 1 micron, and the content of the semiconductive particles or conductive particles is The gist is the low capacitance multilayer chip varistor according to the fifth invention of the present application, which is less than 20 weight percent of the content of the inorganic glass.

  In addition, according to a seventh aspect of the present invention, the inorganic glass comprises one or more of silicate glass, aluminosilicate glass, borate glass, phosphate glass, lead acid glass and other inorganic acid salt glass. The gist of the invention is the low capacitance multilayer chip varistor according to the fifth or sixth invention of the present application.

In the eighth invention of the present application, the semiconductive particles are ZnO, TiO ₂ , SnO ₂ , Si, Ge, SiC, Si—Ge alloy, InSb, GaAs, InP, GaP, ZnS, ZnSe, ZnTe, SrTiO _3. And BaTiO ₃ , wherein the conductive particles are selected from one or more of Pt, Pd, W, Au, Al, Ag, Ni, Cu and alloys thereof. The gist of the invention is the low capacitance multilayer chip varistor described in the invention.

  As illustrated in FIG. 1, the low capacitance multilayer chip varistor 10 in one preferred embodiment of the present invention is made by a multilayer technology process. The varistor 10 is made by a multilayer ceramic process including high-temperature sintering and the like, and includes a ceramic body 11, an external electrode 13 disposed at two ends of the ceramic body 11, and an internal electrode 12 disposed therein. Is provided.

  The ceramic body 11 is made of a protective material against electrical overstress with small holes, and its microstructure is shown in FIG. The test sample material comprises 3 to 50 weight percent inorganic glass and 50 to 97 weight percent semi-conductive or conductive particles 14 having a particle size greater than 0.1 μm. The layer of the inorganic glass film 15 that can withstand high temperatures covers the surface of the semiconductive particles or conductive particles 14.

  The inorganic glass film 15 is composed of sub-micron or nanometer semiconductive particles or conductive particles 16 smaller than 1 micron due to sub-dispersion. The content of semiconductive particles or conductive particles is less than 20 weight percent of the content of inorganic glass.

  In accordance with the low capacitance multilayer chip varistor 10 of the preferred embodiment of the present invention, the microstructure of the ceramic body 11 has a high hole ratio and low capacitance that is less than 0.5 pF at 1 MHz.

  In addition, according to the low capacitance multilayer chip varistor 10 of the preferred embodiment of the present invention, the inorganic glass film 15 that withstands high temperatures resists the heat generated when suppressing electrostatic shock or surge electrical overstress. , Present in the semiconductive particles or conductive particles 14 of the ceramic body 11. In particular, the inorganic glass film 15 comprises 0.1 micron or nanometer semiconductive particles or conductive particles due to sub-dispersion, and the voids between the particles 16 are very small, resulting in abnormal electrical overload. When stress is generated, a tunnel effect occurs. As a result, the low-capacitance multilayer chip varistor 10 disclosed in the present invention suppresses electrical overstress, withstands electrostatic shock, and has a long life.

  The process of making a low capacitance multilayer chip varistor 10 according to a preferred embodiment of the present invention comprises:

(1) In order to uniformly disperse nanometal particles or semiconductive particles in a solution composed of glass components, the glass components are silicate glass, aluminosilicate glass, borate glass, phosphate glass, lead acid salt. Using a solution made of a glass component comprising glass or the like and made by a sol-gel process.
The nanoparticles have a particle size of less than 1000 nanometers, and include metal conductive particles including Pt, Pd, Au, Ag, Ni, Cu, or the like, or SiC, ZnO, TiO ₂ , SnO ₂ , SrTiO ₃ , BaTiO _3. And the like.

(2) Semiconductive particles or conductive particles are uniformly mixed in the above solution in which metal nanoparticles or semiconductor nanoparticles are dispersed, dried, and fired at an appropriate temperature (less than 1000 ° C.). And then crushing them into composite materials.
The size of the semiconductive particles or conductive particles is submicron or micron greater than 0.1 μm. The semiconductive particles comprise SiC, ZnO, TiO ₂ , SnO ₂ , SrTiO ₃ , BaTiO ₃ etc. or the particles of the semiconductive particles described above, while the conductive particles are Pt, Pd, Au, Ag, Ni, Cu etc. are provided.

(3) Using a conventional multi-layer technique to obtain a slurry by adding a binder agent to the composite material described above, a doctor blade process used to become a ceramic green sheet with a thickness of 10 to 50 μm.
Next, a multi-layer chip process is used to print two or more staggered internal electrodes. The internal electrode comprises a metal comprising Pt, Pd, Au, Ag, Ni or the like. After laminating and cutting the upper cover layer and the lower cover layer, sintering is performed at 700 to 1200 ° C. The two ends of the component are sintered and silver plaster is deposited to become the external electrode. As a result, a low capacitance multilayer chip varistor that suppresses static electricity and surge is completed. In addition, the material of the external electrode includes Ag, Cu, Ag—Pd alloy and the like.

  The low capacitance multi-layer chip varistor of the preferred embodiment of the present invention made by the above process has a capacitance of less than 0.5 pF and can therefore be used to protect high frequency electronic circuits, while having low capacitance and low insulation. It has advantages such as breakdown voltage and suppresses electrostatic shock several thousand times that of 8KV.

  The following paragraphs describe some preferred embodiments of a low capacitance multilayer chip varistor according to the present invention, said varistor having the property of 0.5 pF capacitance at 1 MHz and several thousand times the electrostatic shock of 8 KV. Suppresses electrical overstress, suppresses electrostatic shock, and protects the high-frequency electric circuit.

  In addition, the following preferred embodiment takes a multilayer chip varistor as an example. However, the process of the present invention can also be used to produce disk-type varistors, or the material according to the present invention is placed between any two electrodes to suppress transient surge voltages or electrostatic shock. Can be used for.

[Example 1]
SiC powder having a particle size in the range of 0.1 to 20 μm and nanometal Pt having a particle size in the range of 0.01 to 2 μm are formed by a sol-gel process and are made of a nanosilicate glass in which the mixed solution is sufficiently stirred To the solution. In this way, the SiC powder uniformly surrounded the organic film layer containing the glass component. Eight samples of different solutions are obtained according to the SiC powder, nano-Pt and glass weight ratio as shown in Table 1 below.

Table 1

  The mixed solution as shown in Table 1 is dried to become a powder, and calcined at 700 ° C. or put into a calcining furnace to become a SiC powder coated with a glass film.

  The calcined powder is then roughly crushed and a solution (such as toluene or butanol), a binder (such as polyvinyl butyral), and a dispersant are placed together in a ball mill and ground to obtain a slurry. The Thereafter, it becomes a 30 μm thick ceramic green sheet by using a doctor blade process.

  As shown in Table 1, these types of eight sheets are stacked and pressed to form a lower cover having a thickness of about 200 μm. After the internal electrode is printed on the lower cover and dried, a thin sheet having a thickness of 30 μm is disposed, and then the internal electrode is printed again. This internal electrode and the internal electrode on the lower cover are alternately connected to the right end and the left end of the component. The material of the internal electrode comprises Pt, Ag, Pd or any two alloys of these metals.

  Eight sheets of these types are stacked and pressed to form an upper cover with a thickness of about 200 μm. The upper cover and the above-described lower cover with internal electrodes are stacked together and pressed, and then cut into ceramic sheet chips of size 1.2 mm * 0.6 mm * 0.6 mm. The ceramic sheet chip is placed in a sintering furnace for sintering, and the sintering temperature is about 800 to 1000 ° C. After sintering, the chip size is 1.0 mm * 0.5 mm * 0.5 mm. The two ends of the chip are immersed in an external electrode that is heated to be deposited thereon at about 600 to 900 ° C., resulting in a low capacitance, low voltage, surge or static suppression multilayer chip varistor. Complete.

Table 2 shows the breakdown voltage of the multilayer chip varistor and the breakdown voltage after an electrostatic test of 8 KV.

Table 2

  As shown in Table 2, the greater the glass content, the higher the dielectric breakdown voltage and the lower the capacitance. This phenomenon is related to the high resistance of glass. When the glass contained is large, the grain boundary insulating layer becomes thick, so that the breakdown voltage of the multilayer chip varistor is higher and the capacitance is further reduced.

  In addition, when the weight ratio of SiC to glass is from 100: 15 to 100: 20, the multilayer chip varistor has a favorable electrostatic discharge inhibiting power. When the glass content is small, the insulation resistance is not sufficient, and the variation of the dielectric breakdown voltage at 1 mA is larger than 10% in the case of the multilayer chip varistor after ESD. Thus, the electrical properties are even better when the glass contained is greater than 15 weight percent. However, if the glass contained exceeds 20 weight percent, the grain boundary becomes thick, so the breakdown voltage and trigger voltage become too high (trigger voltage is over 800V) and is not suitable for protective components. Accordingly, the glass addition is preferably controlled between 15 weight percent and 20 weight percent.

  As shown in Table 2, whatever the ratio of SiC to added glass, the added nanometal particles have the effect of reducing the trigger voltage and improving the breakdown voltage variation after electrostatic shock. However, the capacitance is relatively high.

  As shown in Table 2, when the contained glass is 10 to 40 weight percent, the capacitance of each multilayer chip is small, less than 0.5 pF.

[Example 2]
ZnO powder with a particle size in the range of 0.1 to 20 μm, oxides such as Bi ₂ O ₃ , CoO and nanometal Pd with a particle size in the range of 0.01 to 2 μm were made from the sol-gel process and mixed as described above The solution is added to the gelled solution consisting of well-stirred nanosilicate glass. In this way, the SiC powder uniformly surrounded the layer of the organic film containing the glass component. The weight ratios of ZnO, Bi ₂ O ₃ , CoO, nanometal Pt particles and nanoglass are shown in Table 3.

Table 3

Next, as in Example 1, the powder described above is processed into a multilayer chip varistor. Table 4 shows the breakdown voltage of the components, the variation of the breakdown voltage after the 8 KV electrostatic shock, and the capacitance.

Table 4

  Table 4 shows that when an oxide such as ZnO is taken as semiconductive particles and the process of the present invention is used, a low capacitance, static suppressing multilayer chip varistor is made.

Table 4 also shows that multilayer chip varistors using ZnO as the material have a higher trigger voltage. To lower the trigger voltage, the sheet thickness between the electrodes was changed from 30 μm to 15 μm, and the results are shown in Table 5.

Table 5

  Comparing the results in Table 4 and Table 5, the thinner the sheet used, the lower the trigger voltage and the higher the capacitance. This result is similar to a typical multilayer ZnO varistor. Thus, within a predetermined range, the sheet thickness can be adjusted to control the trigger voltage.

[Example 3]
SiC powder with a particle size in the range of 2 to 7 μm and nanometal Pt with a particle size in the range of 0.03 to 0.5 μm are made from a sol-gel process and consist of nanosilicate glass with well-stirring the aforementioned mixed solution It is added to the gel solution. In this way, the SiC powder uniformly surrounded the layer of the organic film containing the glass component. A multilayer chip varistor is completed in the same manner as in the first preferred embodiment. The electrical characteristics of the multilayer chip varistor were measured and are shown in Table 6.

Table 6

  As shown in Table 6, the multilayer chip varistor has a lower breakdown voltage when the particle size for subdispersion is reduced. However, the capacitance is relatively high.

[Example 4]
The multilayer chip varistor sheet made in Example 1 was sintered at 850 to 1000 ° C., and the effect of different sintering conditions is shown in Table 7. As the sintering temperature increases, the breakdown voltage decreases, but the capacitance increases and the leakage current decreases. Similarly, the breakdown voltage decreases as the sintering time increases.

Table 7

[Example 5]
Changing the overlapping area of the internal electrodes of the multilayer chip varistor sheet made by the same method as in the first preferred embodiment completes a 0.02 pF varistor as shown in Table 8. Thus, the size of the overlapping area of the internal electrodes can be used to significantly adjust the capacitance.

Table 8

  As shown in the above-described embodiments, after adjusting various parameters, the multilayer chip varistor according to the present invention has a very low capacitance and protects against electrical overstress such as static electricity or transient surges for high frequency circuits. It is particularly suitable to be applied in.

1 is a schematic diagram of a low capacitance multilayer chip varistor in one preferred embodiment of the present invention. FIG. FIG. 2 is a schematic microstructure diagram of a ceramic body of a low capacitance multilayer chip varistor in region A of FIG. 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Varistor 11 Ceramic body 12 Internal electrode 13 External electrode 14 Semiconductive particle or conductive particle 15 Inorganic glass film 16 Submicron or nanometer semiconductive particle or conductive particle

Claims (8)

A protective material with small holes to protect against electrical overstress,
The material is applied between positive and negative electrodes to suppress transient surge voltage and electrostatic shock,
The material comprises 3 to 50 weight percent inorganic glass and 50 to 97 weight percent semiconductive or conductive particles having a particle size greater than 0.1 microns,
A layer of inorganic glass film covers the surface of the semiconductive particles or conductive particles,
Protective material against excessive electrical stress.   The inorganic glass film contains submicron or nanometer semiconductive particles or conductive particles smaller than 1 micron, and the content of the semiconductive particles or conductive particles is 20 weight percent of the content of the inorganic glass. The protective material against electrical overstress according to claim 1, wherein   3. The inorganic glass comprises one or more of silicate glass, aluminosilicate glass, borate glass, phosphate glass, lead acid glass and other inorganic acid salt glass. Protective material against excessive electrical stress. The semi-conductive particles, one of _{ZnO, TiO 2, SnO 2,} Si, Ge, SiC, Si-Ge alloy, InSb, GaAs, InP, GaP , ZnS, ZnSe, ZnTe, SrTiO 3 and BaTiO ₃ The protection against electrical overstress according to claim 2, wherein the conductive particles are selected from one or more of Pt, Pd, W, Au, Al, Ag, Ni, Cu and alloys thereof. material. A low capacitance multilayer chip varistor having a capacitance of less than 0.5 pF at 1 MHz,
The varistor includes a ceramic body, an external electrode disposed at two ends of the ceramic body, and an internal electrode disposed therein,
The ceramic body comprises 3 to 50 weight percent inorganic glass and 50 to 97 weight percent semiconductive or conductive particles having a particle size greater than 0.1 μm;
A layer of inorganic glass film covers the surface of the semiconductive particles or the conductive particles;
Low capacitance multilayer chip varistor.   The inorganic glass film includes sub-micron or nanometer semiconductive particles or conductive particles smaller than 1 micron, and the content of the semiconductive particles or conductive particles is 20 weight percent of the content of the inorganic glass The low capacitance multilayer chip varistor of claim 5, wherein   7. The inorganic glass of claim 5 or 6, wherein the inorganic glass comprises one or more of silicate glass, aluminosilicate glass, borate glass, phosphate glass, lead acid glass and other inorganic acid salt glass. Low capacitance multilayer chip varistor. The semi-conductive particles are _{ZnO, TiO 2, SnO 2,} Si, Ge, SiC, Si-Ge alloy, InSb, GaAs, InP, GaP , ZnS, ZnSe, ZnTe, from one of SrTiO ₃ and BaTiO ₃ The low capacitance multilayer chip varistor of claim 6, wherein the selected and conductive particles are selected from one or more of Pt, Pd, W, Au, Al, Ag, Ni, Cu and alloys thereof.

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