JP2008277818A - Surge absorbing material with double functions - Google Patents

Surge absorbing material with double functions Download PDF

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JP2008277818A
JP2008277818A JP2008112539A JP2008112539A JP2008277818A JP 2008277818 A JP2008277818 A JP 2008277818A JP 2008112539 A JP2008112539 A JP 2008112539A JP 2008112539 A JP2008112539 A JP 2008112539A JP 2008277818 A JP2008277818 A JP 2008277818A
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surge absorber
particles
glass
conductive particles
semiconductive
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JP4750150B2 (en
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Gyokubun Tan
譚玉▲ぶん▼
Jie-An Zhu
朱頡安
Li-Yun Zhang
章麗雲
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KOKI NABEI KAGI KOFUN YUGENKOS
KOKI NABEI KAGI KOFUN YUGENKOSHI
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a surge absorbing material with double functions. <P>SOLUTION: The surge absorbing material with the double functions has one property out of capacitance, inductance, voltage suppression, and a thermister, and includes a high resistance glass substrate and conductive particles or semiconductive particles with the low resistance of three kinds of a micron, a sub-micron and a nano meter that are uniformly distributed in the glass substrate so that a microscopic composite may have excellent surge absorbing properties. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明はサージ吸収材に関し、より具体的には、サージ吸収特性に加えキャパシタンス、インダクタンス、電圧抑制性、及びサーミスタ中の特性の内の１つを有する、二重機能を備えたサージ吸収材に関する。   The present invention relates to a surge absorber, and more specifically, to a surge absorber having a dual function having one of the characteristics of capacitance, inductance, voltage suppression, and thermistor in addition to surge absorption characteristics. .

サージ、または落雷、切り替え動作または他のパーツの損傷により生じる電気的な過大応力は、電子部品または他の敏感な電気機器に支障を来たす、あるいは損傷を与える可能性がある。したがって、優れたサージ吸収能力を有するサージアブソーバ（またはバリスタと呼ばれている）が、電気的な過大応力つまり電子部品、電子回路または電子機器のサージに対して保護策を講じるための部品として幅広く使用されている。   Electrical overstress caused by surges or lightning strikes, switching operations or other part damage can interfere with or damage electronic components or other sensitive electrical equipment. Therefore, surge absorbers (or varistors) with excellent surge absorption capability are widely used as parts to protect against electrical overstress, that is, surges in electronic components, electronic circuits or electronic devices. in use.

さらに、積層工程により単一の構造体としてさまざまな機能の２つの部品を組み合わせることがよく知られている傾向である。例えば、インダクタンス及びキャパシタンスは単一のＳＭＤ型（表面実装デバイス）の部品として組み合わされ、フィルター機能を有するインダクタンス−キャパシタンスフィルタ（ＬＣフィルタ）になる。あるいは、抵抗及びキャパシタンスは単一のＳＭＤ型の部品として組み合わされ、フィルター機能を有する抵抗−キャパシタンスフィルター（ＲＣフィルター）になる。   Furthermore, it is a well-known tendency to combine two parts having various functions as a single structure by a lamination process. For example, the inductance and capacitance are combined as a single SMD type (surface mount device) component, resulting in an inductance-capacitance filter (LC filter) having a filter function. Alternatively, the resistance and capacitance are combined as a single SMD type component, resulting in a resistance-capacitance filter (RC filter) having a filter function.

しかしながら、異なる機能の２つの部品が積層工程によって単一の構造体として組み合わされるとき、２つの部品の焼結温度及び収縮速度は異なるため、２つの部品間に残留応力が容易に生じ、その結果、異なる機能の２つの部品がともに単一の構造体に焼結され、分離及び無効果性の問題が生じる。   However, when two parts with different functions are combined as a single structure by the lamination process, the two parts have different sintering temperatures and shrinkage rates, so residual stress easily arises between the two parts, resulting in Two parts with different functions are both sintered into a single structure, resulting in separation and inefficiency issues.

前述の問題を解決するために、いくつかの従来技術は２つの材料の接続を強化するためにサージアブソーバとセラミックコンデンサ間に配置される低温ガラスを開示している。中国公開番号第１，８５８，９９５号は、材料にサージアブソーバ及びインダクタの機能を与えるために、亜鉛酸化物と更に異なる要素から主に構成されるバリスタ層を開示しており、２つの層は積層工程によって組み合わされ、ともに焼結されている。   In order to solve the aforementioned problems, some prior art discloses low temperature glasses that are placed between a surge absorber and a ceramic capacitor to enhance the connection of the two materials. China Publication No. 1,858,995 discloses a varistor layer composed mainly of elements different from zinc oxide to give the material the function of a surge absorber and inductor, the two layers being They are combined by the lamination process and sintered together.

また、いくつかの研究では、２つの材料の焼結工程中の相互拡散性に起因する不良電気特性の問題を改善するために、容量が変化する絶縁層を２つの部品間に配置する。   Some studies have also placed an insulating layer of varying capacitance between the two parts to improve the problem of poor electrical properties due to interdiffusion during the sintering process of the two materials.

しかしながら、前述の方法は多機能の部品を製造できるが、工程は相対的に複雑である。例えば、部品に電気特性を与えるためには、部品の２つの材料の中にガラスまたは容量が変化する絶縁層を追加する必要がある。さらに、このような工程では、異なる焼結大気を要する２つの部品をともに焼結することはできないため、製品が優れた電気特性を有することはない。   However, the method described above can produce multi-functional parts, but the process is relatively complex. For example, in order to impart electrical properties to a component, it is necessary to add an insulating layer of varying glass or capacitance in the two materials of the component. Further, in such a process, two parts that require different sintering atmospheres cannot be sintered together, so that the product does not have excellent electrical properties.

本発明の１つの目的は、二重機能を有するサージ吸収材を製造する方法を提供することである。一次分散方法、二次分散方法、または三次分散方法によって、ミクロン、サブミクロン及びナノメートルサイズの導電性粒子または半導電性粒子がガラス相の適切な材料に包まれ、その後、優れたサージ吸収特性を有するために焼結される。さらにガラス相の材料がキャパシタンス、インダクタンス、電圧抑制性及びサーミスタ中の特性の内の１つを備えた材料から選択されると、サージ吸収材は、サージ吸収特性に加え、キャパシタンス、インダクタンス、電圧抑制性、及びサーミスタ中の特性の１つを有する二重機能のある材料になり、異なる特性の２つの材料がともに単一の構造体に焼結さるときに生じる分離及び無効果性の問題を解決することができる。   One object of the present invention is to provide a method of manufacturing a surge absorber having a dual function. By primary dispersion method, secondary dispersion method, or tertiary dispersion method, conductive particles or semiconductive particles of micron, submicron and nanometer size are encased in a suitable material of glass phase, and then excellent surge absorption characteristics Sintered to have In addition, if the glass phase material is selected from materials with one of capacitance, inductance, voltage suppression and thermistor properties, the surge absorber will have capacitance, inductance, and voltage suppression in addition to the surge absorption properties. And a dual function material with one of the properties in the thermistor, solving the separation and inefficiency problems that arise when two materials with different properties are both sintered into a single structure can do.

本発明の他の目的は、材料組成が、ガラス基板中で分散されるミクロン、サブミクロン、及びナノメートルサイズを含む高抵抗及び低抵抗の導電性粒子または半導電性粒子を有するガラス基板を含む二重機能のサージ吸収材を提供することであり、特にサブミクロンサイズの導電性粒子または半導電性粒子はミクロンサイズの導電性粒子または半導電性粒子中で均一に分散され、ナノメートルサイズの導電性または半導電性粒子はサブミクロンサイズの導電性粒子または半導電性粒子中で均一に分散される。   Another object of the present invention includes a glass substrate having high and low resistance conductive or semiconductive particles, including micron, submicron, and nanometer sizes, whose material composition is dispersed in the glass substrate. Providing a dual function surge absorber, in particular, submicron sized conductive particles or semiconductive particles are uniformly dispersed in micron sized conductive particles or semiconductive particles, and nanometer sized The conductive or semiconductive particles are uniformly dispersed in the submicron sized conductive particles or semiconductive particles.

本発明のこのようなサージ吸収材が積層部品の製造に使用されるとき、単一の構造体として異なる材料を共燃焼する問題は必ずしもそれ以上検討されず、積層工程は相対的に簡略且つ容易である。   When such a surge absorber of the present invention is used in the manufacture of laminated parts, the problem of co-combusting different materials as a single structure is not necessarily considered any further, and the lamination process is relatively simple and easy. It is.

図１から図４に示されているように、本発明の積層チップサージアブソーバ２０を作るために適用されるサージ吸収材１０の微視的な組成は、ガラス基板１１中に均一に分散される、高抵抗及び低抵抗のミクロンの導電性粒子または半導電性粒子１２と、サブミクロンの導電性粒子または半導電性粒子１４、及びナノメートルの導電性粒子または半導電性粒子１６とを有するガラス基板１１を含む。   As shown in FIGS. 1 to 4, the microscopic composition of the surge absorber 10 applied to make the multilayer chip surge absorber 20 of the present invention is uniformly dispersed in the glass substrate 11. , High resistance and low resistance micron conductive particles or semiconductive particles 12, submicron conductive particles or semiconductive particles 14, and nanometer conductive particles or semiconductive particles 16 A substrate 11 is included.

ミクロンの導電性粒子または半導電性粒子１２の粒子直径は０．１μｍより大きく、サブミクロンの導電性粒子または半導電性粒子１４の粒子直径は０．１から０．０１μｍの間であり、導電性粒子または半導電性粒子１６のナノメートルの粒子直径は０．０１μｍより小さい。   The particle diameter of the micron conductive particles or semiconductive particles 12 is larger than 0.1 μm, and the particle diameter of the submicron conductive particles or semiconductive particles 14 is between 0.1 and 0.01 μm. The nanometer particle diameter of the conductive particles or semiconductive particles 16 is less than 0.01 μm.

導電性粒子は、Ｐｔ、Ｐｄ、Ｗ、Ａｕ、Ａｌ、Ａｇ、Ｎｉ、Ｃｕ、Ｆｅおよびその合金の１つまたは複数から選択される。   The conductive particles are selected from one or more of Pt, Pd, W, Au, Al, Ag, Ni, Cu, Fe and alloys thereof.

半導電性粒子は、ＺｎＯ、ＴｉＯ2、ＳｎＯ2、Ｓｉ、Ｇｅ、ＳｉＣ、Ｓｉ−Ｇｅ合金、ＩｎＳｂ、ＧａＡｓ、ＩｎＰ、ＧａＰ、ＺｎＳ、ＺｎＳｅ、ＺｎＴｅ、ＳｒＴｉＯ3、及びＢａＴｉＯ3の内の１つから選択される。 Semiconductive particles, ZnO, TiO 2, SnO 2 , Si, Ge, SiC, Si-Ge alloy, InSb, GaAs, InP, GaP , ZnS, ZnSe, ZnTe, SrTiO 3, and one of BaTiO 3 Selected from.

図１に示すように、本発明のサージ吸収材１０は、３から６０重量％で、ミクロンの導電性粒子または半導電性粒子１２のガラス基板１１を含み、粒子直径はサージ吸収材１０の総重量に基づき、４０から９７重量％の０．１μｍを超えている。   As shown in FIG. 1, the surge absorber 10 of the present invention comprises a glass substrate 11 of 3 to 60% by weight of micron conductive particles or semiconductive particles 12, and the particle diameter is the total of the surge absorber 10 Based on weight, it exceeds 40 μm to 97% by weight of 0.1 μm.

また、図２に示すように、サージ吸収材１０の微視的な組成において、二次分散されたサブミクロンの導電性粒子または半導電性粒子１４は、一次分散されたミクロンの導電性粒子または半導電性粒子１２中で均一に分散されている。図３に示すように、三次分散されたナノメートルの導電性粒子または半導電性粒子１６は二次分散されたサブミクロンの導電性粒子または半導電性粒子１４中で均一に分散されている。   In addition, as shown in FIG. 2, in the microscopic composition of the surge absorber 10, the secondary dispersed submicron conductive particles or semiconductive particles 14 are converted into primary dispersed micron conductive particles or It is uniformly dispersed in the semiconductive particles 12. As shown in FIG. 3, the tertiary dispersed nanometer conductive particles or semiconductive particles 16 are uniformly dispersed in the secondary dispersed submicron conductive particles or semiconductive particles 14.

したがって、サージ吸収材１０の微視的組成は、ガラス基板１１中に均一に分散された異なる粒子直径の三種類の低抵抗導電性粒子または半導電性粒子１２、１４、及び１６を含み、このような組成はサージ吸収材１０にサージアブソーバの特性を与える。   Therefore, the microscopic composition of the surge absorber 10 includes three types of low-resistance conductive particles or semiconductive particles 12, 14, and 16 having different particle diameters that are uniformly dispersed in the glass substrate 11. Such a composition gives the surge absorber 10 the characteristics of a surge absorber.

図４に示すように、積層チップサージアブソーバ２０のセラミック層２１は、本発明によるサージ吸収材１０により作られており、セラミック層２１は耐熱ガラス材料から作られ、セラミック層２１の微視的組成中に分散されているミクロンの導電性粒子または半導電性粒子１２及びサブミクロンの導電性粒子または半導電性粒子１４があるため、積層チップサージアブソーバ２０は静電ショック及びサージ過大応力から生じる熱に耐えられる。   As shown in FIG. 4, the ceramic layer 21 of the multilayer chip surge absorber 20 is made of the surge absorber 10 according to the present invention. The ceramic layer 21 is made of a heat-resistant glass material, and the microscopic composition of the ceramic layer 21. Because of the micron conductive particles or semiconductive particles 12 and the submicron conductive particles or semiconductive particles 14 dispersed therein, the laminated chip surge absorber 20 is subject to heat generated from electrostatic shock and surge overstress. Can withstand.

とりわけ、二次分散されたサブミクロンの導電性粒子または半導電性粒子１４及び三次分散されたナノメートルの導電性粒子または半導電性粒子１６はセラミック層２１の中にさらに包含され、ナノメートルの導電性粒子または半導電性粒子１６の粒子距離は非常に小さいので、異常過大応力がかけられるとトンネル効果が発生する。したがって、積層チップサージアブソーバ２０は、優れた寿命だけではなく優れた電気的な過大応力抑制能力及び静電ショック抵抗も有する。   In particular, secondary dispersed submicron conductive particles or semiconductive particles 14 and tertiary dispersed nanometer conductive particles or semiconductive particles 16 are further included in the ceramic layer 21, Since the particle distance of the conductive particles or the semiconductive particles 16 is very small, a tunnel effect occurs when an abnormally excessive stress is applied. Therefore, the multilayer chip surge absorber 20 has not only an excellent lifetime but also an excellent electrical overstress suppressing ability and electrostatic shock resistance.

要するに、サージ吸収材１０は、キャパシタンスガラス状態部品、インダクタンスガラス状態部品、電圧抑制性ガラス状態部品、及びサーミスタガラス状態部品の内の１つからガラス基板１１を選ぶことによりサージ吸収特性に加えキャパシタンス、インダクタンス、電圧抑制性及びサーミスタ中の特性の内の１つを有する。すなわち、サージ吸収材１０は二重機能を有する材料である。   In short, the surge absorber 10 has a capacitance, in addition to surge absorption characteristics, by selecting the glass substrate 11 from one of a capacitance glass state component, an inductance glass state component, a voltage suppressing glass state component, and a thermistor glass state component. It has one of inductance, voltage suppression and characteristics in the thermistor. That is, the surge absorber 10 is a material having a dual function.

本発明の好適な実施形態によるサージ吸収材１０を製造する方法は、以下のステップを含む。   The method of manufacturing the surge absorber 10 according to a preferred embodiment of the present invention includes the following steps.

（１）サージ吸収材１０のガラス基板１１に、キャパシタンス、インダクタンス、電圧抑制性、及びサーミスタ中の特性の内の１つを与えるために適切なガラス相組成を選択し、ガラス相組成の溶液を作り出すためにゾルゲル法を使用する。   (1) An appropriate glass phase composition is selected to give the glass substrate 11 of the surge absorber 10 one of capacitance, inductance, voltage suppression, and thermistor characteristics, and a glass phase composition solution is prepared. Use sol-gel method to produce.

ガラス基板１１がキャパシタンスガラス状態組成であるとき、ガラス基板１１は、一般的なキャパシタンス特性、及び高誘電率のＢａＴｉＯ3、ＳｒＴｉＯ3、ＣａＴｉＯ3及びＴｉＯ２を有する、ケイ酸塩ガラス、アルミノケイ酸塩ガラス、ホウ酸塩ガラス、及びリン酸塩ガラスから選択できる。 When the glass substrate 11 has a capacitance glass state composition, the glass substrate 11 has general capacitance characteristics and high dielectric constant BaTiO 3 , SrTiO 3 , CaTiO 3 and TiO 2, silicate glass, aluminosilicate glass. , Borate glasses, and phosphate glasses.

ガラス基板１１がインダクタンスガラス状態組成であるとき、ガラス基板１１は、一般的なインダクタンス特性の一連のＮｉ−ＺｎまたはＮｉ−Ｃｕ−Ｚｎインダクタンス材料、あるいは高周波数インダクタンス特性のＬＴＣＣ材料から選択できる。   When the glass substrate 11 has an inductance glass state composition, the glass substrate 11 can be selected from a series of Ni—Zn or Ni—Cu—Zn inductance materials with general inductance characteristics, or LTCC materials with high frequency inductance characteristics.

ガラス基板１１が電圧抑制性ガラス状態組成であるとき、ガラス基板１１は、ＢａＴｉＯ3、ＰＺＴ及びＰＬＺＴ等の電気的な過大応力抑制材料であるはずである。 When the glass substrate 11 has a voltage-suppressing glass state composition, the glass substrate 11 should be an electrical overstress suppressing material such as BaTiO 3 , PZT, and PLZT.

ガラス基板１１がサーミスタガラス状態組成であるとき、ガラス基板１１は、ＮＴＣ特性のＭｎ−Ｎｉ系またはＭｎ−Ｃｏ−Ｎｉ系、あるいはＣＴＲ特性のＶ−Ｐ−Ｆｅ系等の一般的なサーミスタ特性を有するサーミスタ材料であるはずである。   When the glass substrate 11 has a thermistor glass state composition, the glass substrate 11 has a general thermistor characteristic such as NTC characteristic Mn-Ni or Mn-Co-Ni, or CTR characteristic VP-Fe. Should have a thermistor material.

（２）ナノメートルサイズの金属粒子または半導電性粒子をステップ（１）のガラス溶液中に均一に分散する。   (2) Disperse nanometer-sized metal particles or semiconductive particles uniformly in the glass solution of step (1).

ナノメートル粒子は０．０１μｍより小さい粒子直径を有し、Ｐｔ、Ｐｄ、Ａｕ、Ａｇ、Ｎｉ、Ｃｕ等を備える金属導電性粒子、あるいはＳｉＣ、ＺｎＯ、ＴｉＯ2、ＳｎＯ2、ＳｒＴｉＯ3、ＢａＴｉＯ3等を備える半導電性粒子であるはずである。 Nanometer particles have a particle diameter of less than 0.01 μm and are metal conductive particles comprising Pt, Pd, Au, Ag, Ni, Cu, or the like, or SiC, ZnO, TiO 2 , SnO 2 , SrTiO 3 , BaTiO 3. Should be semi-conductive particles.

（３）ステップ（２）でその中に分散されたナノメートルの金属粒子または半導電性粒子を有する溶液中に、サブミクロンサイズの導電性粒子または半導電性粒子を均一に分散する。   (3) Disperse the submicron sized conductive particles or semiconductive particles uniformly in the solution having nanometer metal particles or semiconductive particles dispersed therein in step (2).

（４）ステップ（３）でその中に分散されたサブミクロン及びナノメートルの金属粒子及び半導電性粒子を有する溶液中に、ミクロンサイズの導電性粒子または半導電性粒子を均一に分散する。   (4) Disperse micron-sized conductive particles or semiconductive particles uniformly in a solution having submicron and nanometer metal particles and semiconductive particles dispersed therein in step (3).

（５）適切な温度（１０００℃より低い）でのステップ（４）の後に溶液を着色し、か焼し、次いで、本発明の好適な実施形態によるサージ吸収材１０になるために、それを複合材料に引き延ばす。   (5) After step (4) at an appropriate temperature (below 1000 ° C.), the solution is colored and calcined and then it is converted into a surge absorber 10 according to a preferred embodiment of the present invention. Stretch to composite material.

本発明のサージ吸収材１０は、サージ吸収特性に加えキャパシタンス、インダクタンス、電圧抑制性、及びサーミスタ中の特性の１つを有する。このように、多様な部品をサージ吸収材１０から作り出すとき、サージ吸収特性に加え、キャパシタンス、インダクタンス、電圧抑制性、及びサーミスタ間のどの特性が部品に提供されなければならないのか検討すべきである。   The surge absorber 10 of the present invention has one of capacitance, inductance, voltage suppression, and thermistor characteristics in addition to surge absorption characteristics. Thus, when various parts are created from the surge absorber 10, it is necessary to consider which characteristics among capacitance, inductance, voltage suppression, and thermistor must be provided to the parts in addition to the surge absorption characteristics. .

例えば、サージ吸収材１０がサージ吸収特性に加えてインダクタンス特性を有する材料であるとき、サージ吸収材１０は、電磁波妨害（ＥＭＩ）防止能力及び静電放電（ＥＳＤ）防止能力の両方を有するサージアブソーバまたはフィルタリング部品として作り出されてよい。さらに、このようなフィルタリング部品の材料は優れたサージ吸収能力及び静電吸収能力を有し、材料は複数回のサージ及び静電衝撃の後にも元の特性を保持する。   For example, when the surge absorber 10 is a material having an inductance characteristic in addition to the surge absorption characteristic, the surge absorber 10 is a surge absorber having both an electromagnetic interference (EMI) prevention capability and an electrostatic discharge (ESD) prevention capability. Or it may be produced as a filtering component. In addition, such filtering component materials have excellent surge and electrostatic absorption capabilities, and the materials retain their original properties after multiple surges and electrostatic shocks.

本発明の好適な一実施形態によるサージ吸収材の微視的組成を示す概略図である。It is the schematic which shows the microscopic composition of the surge absorber by one suitable embodiment of this invention. 図１のＡ領域の拡大図である。It is an enlarged view of the A area | region of FIG. 図２のＢ領域の拡大図である。FIG. 3 is an enlarged view of a region B in FIG. 2. 積層されたチップサージアブソーバを示す概略図である。It is the schematic which shows the chip | tip surge absorber laminated | stacked.

Claims (9)

ガラス基板中で分散されているミクロン、サブミクロン、及びナノメートルサイズを含む高抵抗及び低抵抗の導電性粒子または半導電性粒子を有するガラス基板を備えるサージ吸収材であって、
総重量に基づいたサージ吸収材は、
３から６０重量％のガラス基板と、
４０から９７重量％の０．１μｍを超える粒子直径の導電性粒子及び半導電性粒子と、を含み、
サブミクロンサイズの導電性粒子または半導電性粒子はミクロンサイズの導電性粒子または半導電性粒子中で分散され、
ナノメートルサイズの導電性粒子または半導電性粒子はサブミクロンサイズの導電性粒子または半導電性粒子中で分散されることを特徴とする、
サージ吸収材。 A surge absorber comprising a glass substrate having high and low resistance conductive or semiconductive particles including micron, submicron, and nanometer sizes dispersed in a glass substrate,
Surge absorber based on total weight is
3 to 60% by weight of a glass substrate;
40 to 97% by weight of conductive particles and semiconductive particles having a particle diameter of more than 0.1 μm,
Submicron sized conductive particles or semiconductive particles are dispersed in micron sized conductive particles or semiconductive particles;
Nanometer-sized conductive particles or semiconductive particles are dispersed in submicron sized conductive particles or semiconductive particles,
Surge absorber. ミクロンの導電性粒子または半導電性粒子の粒子直径が０．１μｍより大きく、サブミクロンの導電性粒子または半導電性粒子の粒子直径が０．１と０．０１μｍの間であり、ナノメートルの導電性粒子または半導電性粒子の粒子直径が０．０１μｍより小さいことを特徴とする、請求項１に記載のサージ吸収材。   The particle diameter of the micron conductive particles or semiconductive particles is greater than 0.1 μm, the particle diameter of the submicron conductive particles or semiconductive particles is between 0.1 and 0.01 μm, and the nanometer The surge absorber according to claim 1, wherein the particle diameter of the conductive particles or the semiconductive particles is smaller than 0.01 μm. ガラス基板が、キャパシタンスガラス状態部品、インダクタンスガラス状態部品、電圧抑制性ガラス状態部品、及びサーミスタガラス状態部品からなる群より選択されることを特徴とする、請求項１または２に記載のサージ吸収材。   The surge absorber according to claim 1 or 2, wherein the glass substrate is selected from the group consisting of a capacitance glass state component, an inductance glass state component, a voltage suppressing glass state component, and a thermistor glass state component. . キャパシタンスガラス状態部品が、キャパシタンス特性、及び高誘電率のＢａＴｉＯ3、ＳｒＴｉＯ3、ＣａＴｉＯ3及びＴｉＯ2を有するケイ酸塩ガラス、アルミノケイ酸塩ガラス、ホウ酸塩ガラス、及びリン酸塩ガラスを備えることを特徴とする、請求項３に記載のサージ吸収材。 Capacitance glass state component comprises capacitance characteristics and silicate glass, aluminosilicate glass, borate glass, and phosphate glass with high dielectric constant BaTiO 3 , SrTiO 3 , CaTiO 3 and TiO 2 The surge absorber according to claim 3, wherein インダクタンスガラス状態部品がインダクタンス特性の一連のＮｉ−Ｚｎ、Ｎｉ−Ｃｕ−Ｚｎインダクタンス材料と、高周波数インダクタンス特性のＬＴＣＣ材料とを備えることを特徴とする、請求項３に記載のサージ吸収材。   Surge absorber according to claim 3, characterized in that the inductance glass state component comprises a series of Ni-Zn, Ni-Cu-Zn inductance materials with inductance characteristics and LTCC materials with high frequency inductance characteristics. 電圧抑制性ガラス状態部品が、電気的な過大応力抑制特性のあるＢａＴｉＯ3、ＰＺＴ及びＰＬＺＴを備えることを特徴とする、請求項３に記載のサージ吸収材。 The surge absorbing material according to claim 3, wherein the voltage-suppressing glass state component comprises BaTiO 3 , PZT and PLZT having electrical overstress suppressing properties. サーミスタガラス状態部品が、ＮＴＣ特性のあるＭｎ−Ｎｉ、Ｍｎ−Ｃｏ−Ｎｉ系、及びＣＴＲ特性のあるＶ−Ｐ−Ｆｅ系を備えることを特徴とする、請求項３に記載のサージ吸収材。   The surge absorber according to claim 3, wherein the thermistor glass state component comprises Mn-Ni, Mn-Co-Ni system having NTC characteristics, and VP-Fe system having CTR characteristics. 導電性粒子が、Ｐｔ、Ｐｄ、Ｗ、Ａｕ、Ａｌ、Ａｇ、Ｎｉ、Ｃｕ及びその合金の１つまたは複数からなる群より選択されることを特徴とする、請求項３に記載のサージ吸収材。   The surge absorber according to claim 3, wherein the conductive particles are selected from the group consisting of one or more of Pt, Pd, W, Au, Al, Ag, Ni, Cu and alloys thereof. . 半導電性粒子が、ＺｎＯ、ＴｉＯ2、ＳｎＯ2、Ｓｉ、Ｇｅ、ＳｉＣ、Ｓｉ−Ｇｅ合金、ＩｎＳｂ、ＧａＡｓ、ＩｎＰ、ＧａＰ、ＺｎＳ、ＺｎＳｅ、ＺｎＴｅ、ＳｒＴｉＯ3及びＢａＴｉＯ3の１つまたは複数からなる群より選択されることを特徴とする、請求項３に記載のサージ吸収材。 Semiconductive particles, ZnO, TiO 2, SnO 2 , Si, Ge, SiC, Si-Ge alloy, InSb, GaAs, InP, GaP , ZnS, ZnSe, ZnTe, from one or more of SrTiO 3 and BaTiO 3 The surge absorber according to claim 3, wherein the surge absorber is selected from the group consisting of:
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