KR100897390B1 - Ceramic material used for protection against electrical overstress and low-capacitance multilayer chip varistor using the same - Google Patents

Abstract

The present invention relates to a low-capacity multilayer chip varistor, and more particularly, the low-capacitance multilayer chip varistor has a capacity of less than 0.5 pF at 1 MHz, has a resistance to thousands of times of shock of 8KV electrostatic shock, ceramic body, An external electrode disposed at two ends of the ceramic body and an internal electrode disposed therein, wherein the ceramic body has a 50 to 97 weight percent peninsula having an inorganic glass of 3 to 50 weight percent and a particle size larger than 0.1 µm. Comprising electrically conductive or conductive particles, covering the surface of the semiconductive or conductive particles with a layer of an inorganic glass film, wherein the inorganic glass film comprises submicron or nanometer semiconductive or conductive particles of less than 1 micron, and is semiconductive or Content of the conductive particles is less than 20% by weight of the content of the inorganic glass ceramic material for preventing electrical overload And a low capacity multilayer chip varistor using the same.

Ceramic, Microporous Ceramic, Chip Varistor

Description

Ceramic material for low electrical overload and low-capacity multilayer chip varistor using the same. {CERAMIC MATERIAL USED FOR PROTECTION AGAINST ELECTRICAL OVERSTRESS AND LOW-CAPACITANCE MULTILAYER CHIP VARISTOR USING THE SAME}

1 is a schematic diagram of a low capacity multilayer chip varistor according to one preferred embodiment of the present invention,

FIG. 2 is a schematic microstructure diagram of a ceramic body of a low capacitance multilayer chip varistor in region A of FIG. 1.

<Description of the symbols for the main parts of the drawings>

10: low capacity multilayer chip varistor 11: ceramic body

12: internal electrode 13: external electrode

14, 16: conductive particles 15: inorganic glass film

FIELD OF THE INVENTION The present invention relates to low capacity multilayer chip varistors and, more particularly, to low capacity multilayer chip varistors having a capacity of less than 0.5 pF at 1 MHz, which suppresses electrical overload and electrostatic shock and protects electronic circuits.

In the electronics industry, there is a trend toward larger operating frequencies and smaller sizes. Thus, the need for the use of a varistor to protect the IC from damage due to electrical overload is increasingly required for high frequency applications.

Conventional varistors mainly consist of ZnO or SrTiO _{3 and} are completed by adding an oxide and then sintering. Taking ZnO varistors as an example, these consist of ZnO and oxides such as Bi, Sb, Si, Co, Mn, Cr and the like. At high temperatures above 1,000 ° C., Bi ₂ O ₃ and oxides such as Co, Mn, Cr, etc., form grain boundaries between ZnO particles having a fine structure such as grain boundary barrier capacitors. Thus, varistors made of such materials have high capacities ranging from tens of pF to thousands of pF. Even when this material is used in multilayer chip varistors, the varistor capacity is in the range of about 3 pF to several hundred pF at 1 MHz. In high frequency circuits, the signal is distorted when the capacitance of the component providing protection exceeds 3 pF. Thus, the above components providing protection are not suitable for high frequency circuits.

Similarly, a varistor component made of SrTiO ₃ has a capacity of over several thousand pF and is not suitable for high frequency circuits. In addition, when the transmission frequency is high, the capacity must be lowered to prevent the signal from being distorted.

U.S. Patent No. 5,976,420 discloses a chip-type multilayer varistor, which has a low capacity and a high nonlinear coefficient, and which contains at least two oxides selected from SiO ₂ , Bi ₂ O ₃ , PbO, B ₂ O ₃ and ZnO. Consisting mainly of SiC in an amount of 0.1 to 20 mol%, the slurry is obtained by combining with toluene and a binder and mixing using a ball mill, after which the slurry is obtained by using a doctor blade process. It becomes a ceramic green sheet. Paste is printed on the surface of this green sheet, and internal electrodes are formed thereon. A predetermined number of ceramic green sheets are stacked to form a layered body. The layered body is bonded by pressing at a constant pressure. The compressed green body is cut into chips of small size. The green chip is baked at a temperature in the range of 700 to 1,100 ° C. to resist electrostatic shock, thereby completing a ceramic multilayer chip varistor having a surge voltage suppression capability and a high nonlinear coefficient of 10 to 20. Although the chip is not very high in capacity, it has a capacity in the range of 10 to 40 pF, which is much higher than 3 pF, making it unsuitable for use in high frequency circuits.

U. S. Patent No. 6,251, 513 discloses a component that provides protection. The material of this component comprises conductive and semiconductive particles having a particle size of less than 10 μm, which are mixed with a polymer insulating binder to form a paste material. The left and right conductive electrodes are printed on the same side of the insulated substrate and the paste material is filled in the gap between the two conductive electrodes and then baked. Although its capacity is less than 0.25pF at 1MHz, the component is well suited to provide protection for high-frequency circuits. This insulating material consists of a polymeric material, which means that the heat generated by electrostatic shock or surge electrical overload carbonizes the polymeric material and the component becomes conductive and loses the protective effect of the electrical circuit or component. Thus, this component does not have good electrostatic shock resistance and shortens its life. When the static electricity of the direct contact 8KV is applied, there is a problem that a defect occurs immediately after 500 electrostatic shocks.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and an object thereof is to provide a low capacity multilayer chip varistor having a capacity of less than 0.5 pF at 1 MHz.

The varistor of the present invention has a protective effect against static electricity and a surge resistance, and in particular, has the property of withstanding thousands of times of 8KV electrostatic shock, and maintains its original function even after thousands of electrostatic shocks.

It is another object of the present invention to provide a protective material against electrical overload, with micropores, which is used between positive and negative electrodes to suppress surge voltages and electrostatic shock. This material comprises 3-50% by weight inorganic glass and 50-97% by weight semiconductive or conductive particles having a particle size greater than 0.1 μm. In said component, the layer of an inorganic glass film | membrane covers the surface of semiconductive or electroconductive particle. This inorganic glass membrane consists of semiconductive or conductive submicron or nanometer particles of less than 1 micron in size. Content of this semiconductive or electroconductive particle is 20 weight% less than content of an inorganic glass.

It is still another object of the present invention to provide a low capacity multilayer chip varistor having a capacity of less than 0.5 pF at 1 MHz. The varistor includes a ceramic body, a pair of external electrodes disposed at two ends of the ceramic body, and several internal electrodes disposed therein. This ceramic body has fine holes and is made of a protective material against electrical overload. The material comprises 3-50% by weight of inorganic glass and 50-97% by weight of semiconductive or conductive particles having a particle size of greater than 0.1 μm. In said component, the layer of an inorganic glass film | membrane covers the surface of semiconductive or electroconductive particle. This inorganic glass film consists of semi-conductive or conductive material of submicron or nanometer particles smaller than 1 micron in size. Content of this semiconductive or electroconductive particle is 20 weight% less than content of inorganic glass.

It is still another object of the present invention to provide a multilayer chip varistor of low capacitance and low breakdown voltage. The trigger voltage of this varistor is based on the thickness of the ceramic green sheet, the sintering temperature of the ceramic compact, the thickness of the glass layer at the grain boundary, the size of the conductive or semiconductive particles, and the amount of the conductive or semiconductive particles of nanometer size for secondary dispersion. The present invention provides a ceramic material for preventing electrical overload and a low-capacity multilayer chip varistor using the same.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, a low capacity multilayer chip varistor 10 according to one preferred embodiment of the present invention is made by a multilayer technology process. The varistor 10 is made by a multilayer ceramic process including high temperature sintering and the like, and has a ceramic body 11, an external electrode 13 disposed at two ends of the ceramic body 11, and disposed therein. Internal electrode 12 is included.

The ceramic body 11 has fine pores, is made of a protective material against electrical overload, and its fine structure is shown in FIG. 2, and has a high hole ratio. The material of this example comprises 3-50% by weight of inorganic glass and 50-97% by weight of semiconductive or conductive particles 14 having a particle size greater than 0.1 μm. The layer of the inorganic glass film 15 having high temperature resistance covers the surface of the semiconductive or conductive particles 14.

The inorganic glass film 15 further includes semiconductive or conductive particles 16 of submicron or nanometers smaller than 1 micron for secondary dispersion. Content of semiconductive or electroconductive particle is 20 weight% less than content of inorganic glass.

According to the low capacity multilayer chip varistor 10 in the preferred embodiment of the present invention, the microstructure of the ceramic body 11 has a high hole ratio and has a low capacity of less than 0.5 pF at 1 MHz.

Further, according to the low-capacity multilayer chip varistor 10 in the preferred embodiment of the present invention, the semiconductive or conductive particles 14 of the ceramic body 11 to withstand the heat generated when suppressing electrostatic shock or surge electric overload There is an inorganic glass film 15 having high temperature resistance. Above all, the inorganic glass film 15 contains 0.1 micron or nanometer semiconductive or conductive particles 16 for secondary dispersion, and the gap between the particles 16 is so small that abnormal electrical overload occurs. Tunnel effect occurs. As a result, the low capacity multilayer chip varistor 10 disclosed in the present invention suppresses electrical overload, is resistant to electrostatic shock, and has a long life time.

The process of manufacturing the low capacity multilayer chip varistor 10 according to one preferred embodiment of the present invention includes the following steps.

(1) a step of using a solution made of a glass component and made by a sol-gel process to uniformly disperse nano-metal particles or semiconductive particles in a solution composed of a glass component, wherein the glass component is silicate glass, Aluminosilicate glass, borate glass, phosphate glass, lead acid glass and the like. The nanoparticles have a particle size of less than 1,000 nanometers, and metal conductive particles containing Pt, Pd, Au, Ag, Ni, Cu, or the like or ZnO, TiO ₂ , SnO ₂ , Si, Ge, SiC, Si— Semi-conductive particles containing Ge alloy, InSb, GaAs, InP, GaP, ZnS, ZnSe, ZnTe, SrTiO ₃ , BaTiO ₃ and the like.

(2) Uniformly mix the semiconductive or conductive particles with the above-mentioned solution with dispersed metal or semiconductive nanoparticles, dry and fire at an appropriate temperature (less than 1,000 ° C) and mill them into the composite material. Wherein the semiconductive or conductive particle size is submicron or micron greater than 0.1 μm. Conductive particles of the Pt, Pd, Au, Ag, Ni, containing Cu or the like, and semi-conductive particles or ZnO, TiO _2, SnO _2, Si, Ge, SiC, Si-Ge alloy, InSb, GaAs, InP , GaP, ZnS, ZnSe, ZnTe, SrTiO ₃ and BaTiO ₃ or the like, or the semiconductive particles described above.

(3) It is a step using the conventional multilayer technique for obtaining a slurry by adding a binder to the said composite material, and a doctor blade process is used to form the ceramic green sheet of thickness of 10-50 micrometers. The multilayer chip process is then used to print two or more staggered internal electrodes. The internal electrode includes a metal including Pt, Pd, Au, Ag, Ni, and the like. After laminating and cutting into the upper and lower cover layers, sintering is performed at 700 to 1200 ° C. At both ends of this component a silver paste to be sintered is attached to form an external electrode. In this way, a low-capacity multilayer chip varistor that suppresses static electricity and surges is completed. In addition, the material of the external electrode includes Ag, Cu, Ag-Pd alloy or the like.

The low capacitance multilayer chip varistor in the preferred embodiment of the present invention made by the above process has a low capacitance and a low breakdown voltage, and suppresses thousands of shocks of 8 KV electrostatic shock when its capacity is less than 0.5 pF, It can thus be used to protect high frequency electronic circuits.

(desirable Example )

Hereinafter, preferred embodiments of the low capacity multilayer chip varistor according to the present invention will be described. Here the varistor has a capacity of 0.5 pF at 1 MHz, suppressing thousands of shocks of 8 KV electrostatic shock, suppressing electrical overload, suppressing electrostatic shock, and protecting high frequency electronic circuits.

In addition, the following preferred embodiments take a multi-layer chip varistor as an example. However, the process in the present invention can also be used to make disc-shaped varistors, or the material according to the present invention can be used to place between any two electrodes to suppress transient surge voltages or electrostatic shock.

    ( Example  One)

SiC powder having a particle size in the range of 0.1 to 20 μm and nano-metal Pt having a particle size in the range of 0.01 to 2 μm are added to a gel-like solution consisting of nano-silicate glass made by the sol-gel process and mixed Stir well. Thus, the SiC powder is uniformly surrounded by the layer of the organic film containing the glass component. As shown in Table 1, eight different sample solutions were obtained depending on the weight ratio of SiC powder, nano-Pt and glass.

Sample SiC (% by weight) Pt particles (% by weight) Glass (wt%) One 100 0 10 2 100 One 10 3 100 0 15 4 100 One 15 5 100 0 20 6 100 One 20 7 100 0 40 8 100 One 40

The mixed solution shown in Table 1 is dried to a powder and then fired at 700 ° C. in a baking oven to be a SiC powder coated with a glass film.

The calcined powder is roughly milled and then milled finely, and the solution (a solution such as toluene or butanol), a binder (binder such as polyvinyl butyral) and a dispersant are put together in a ball mill and milled to obtain a slurry. Get This slurry is then turned into a ceramic green sheet having a thickness of 30 µm by using a doctor blade process.

As shown in Table 1, these eight kinds of sheets were laminated and pressed to have a lower cover having a thickness of about 200 μm. After printing and drying the inner electrode on the lower cover, a thin film sheet having a thickness of 30 mu m is placed and the inner electrode is printed again. This inner electrode and the inner electrode on the lower layer are connected to the left and right ends of the component in a staggered manner. The material of this internal electrode comprises Pt, Ag, Pd or any two alloys of these metals.

These eight kinds of sheets are laminated and pressed to form an upper cover having a thickness of about 200 mu m. The above-described lower cover with the upper cover and the inner electrode are laminated and pressed together and then cut into ceramic sheet chips having a size of 1.2 mm x 0.6 mm x 0.6 mm. The ceramic sheet chip is placed in a baking oven and fired, and the firing temperature is about 800 to 1,000 ° C. After firing, the chip size is 1.0 mm x 0.5 mm x 0.5 mm. When the two ends of the chip are placed on an external electrode and heated at 600 to 900 ° C., a low capacitance, low voltage, and surge or static suppression multilayer chip varistor are completed.

The breakdown voltages of the multilayer chip varistors and the breakdown voltages after the 8 KV blackout test are shown in Table 2.

Sample Breakdown Voltage (V1mA) Capacity (pF at 1 MHz) Trigger voltage (V) % Change in breakdown voltage after 1000 shocks of blackout shock One 67 0.25 120 -23.0 2 54 0.28 110 -15.1 3 110 0.14 205 -9.0 4 75 0.12 154 -7.2 5 234 0.09 422 -7.5 6 137 0.08 257 -6.0 7 415 0.08 1032 -11.4 8 343 0.07 730 -8.6

As can be seen from Table 2, the more glass is contained, the higher the breakdown voltage and the smaller the capacity. This phenomenon is associated with the high resistance of the glass. In the case of a large amount of glass contained, the grain boundary insulating layer becomes thick, so that the multilayer chip varistor has a high breakdown voltage and a small capacity.

In addition, when the weight ratio of SiC to glass is from 100: 15 to 100: 20, the multilayer chip varistor has a desirable resistance to electro-static discharge (ESD). If the glass is small, the insulation resistance is not sufficient, so that the breakdown voltage variation at 1 mA exceeds 10% for the multilayer chip varistor after electrostatic discharge. Thus, the electrical properties are good when the glass contained exceeds 15% by weight. However, when the contained glass is more than 20% by weight, the grain boundaries become thick, and the breakdown voltage and the trigger voltage become excessively high (the trigger voltage exceeds 800 V), making it unsuitable as a protective component. Therefore, the glass addition amount is preferably controlled between 15% and 20% by weight.

As can be seen from Table 2, irrespective of the ratio of SiC to glass added, the added nano-metal particles have the effect of lowering the trigger voltage and improving the variation of the breakdown voltage after electrostatic shock, but the capacity is relatively high.

As can be seen in Table 2, when the glass contained is 10% to 40% by weight, the capacity of the multilayer chip varistor is less than 0.5 pF.

( Example  2)

ZnO powders having a particle size in the range of 0.1-20 μm, oxides such as Bi ₂ O ₃ , CoO and the like, and nano-metal Pds having a particle size in the range of 0.01-2 μm are made by the sol-gel process, and nano-silicates It is added to a gelled solution made of glass and the mixed solution is well wetted. Thus, the SiC powder is uniformly surrounded by the layer of the organic film containing the glass component. The weight ratios of ZnO, Bi ₂ O ₃ , CoO, nano-metal Pd particles and nano-glass are shown in Table 3.

ZnO Bi ₂ O ₃ CoO Pd Glass weight % 100 5 2 One 20

Thereafter, the powder is treated in the same manner as in Example 1 to form a multilayer chip varistor. The breakdown voltage of this component, the breakdown voltage variation after 8 KV electrostatic shock, and the capacity are shown in Table 4.

Sheet thickness (㎛) Breakdown Voltage (V1mA) Capacity (pF at 1 MHz) Trigger voltage (V) % Change in breakdown voltage after 1,000 shocks of blackout shock 30 206 0.27 420 10

Table 4 shows that low capacitance and static suppression multilayer chip varistors can be made when the process of the invention is taken with oxides such as ZnO and the like as semiconductive particles.

Table 4 also shows that multilayer chip varistors using ZnO as the material have high trigger voltages. In order to lower the trigger voltage, the thickness of the inter-electrode sheet was changed from 30 µm to 15 µm and the results are shown in Table 5.

Sheet thickness (㎛) Breakdown Voltage (V1mA) Capacity (pF at 1 MHz) Trigger voltage (V) % Change in breakdown voltage after 1000 shocks of blackout shock 15 143 0.43 257 15

Comparing the results of Table 4 and Table 5, when thinner sheets are used, the trigger voltage is lower and the capacity is higher. This result is similar to a general multilayer ZnO varistor. Therefore, it is possible to control the trigger voltage by adjusting the thickness of the sheet in a predetermined range.

( Example  3)

In addition, SiC powder having a particle size in the range of 2 to 7 μm and nano-metal Pt having a particle size in the range of 0.03 to 0.5 μm are added to a gel-type solution made of nano-silicate glass made by a sol-gel process. Wet the mixed solution well. Thus, the SiC powder is uniformly surrounded by the layer of the organic film containing the glass component. Then, in the same manner as in the first preferred embodiment, the multilayer chip varistor is completed. The electrical properties of this multilayer chip varistor were measured and shown in Table 6.

Particle Size for Secondary Dispersion (μm) Breakdown Voltage (V1 mA) Capacity (pF at 1 MHz) Trigger voltage (V) SiC (30 μm Sheet) 0.5 58 0.26 124 0.03 45 0.29 68

As can be seen from Table 6, multilayer chip varistors have a low breakdown voltage when the particle size for secondary dispersion is small, but the capacity is relatively large.

( Example  4)

The multilayer chip varistor sheet made in Example 1 is sintered at 850 to 1000 ° C, and the effects of different sintering conditions are shown in Table 7. It can be seen that as the sintering temperature is increased, the breakdown voltage is lowered, but the capacity increases and the leakage current decreases. Likewise, as the sintering time increases, the breakdown voltage lowers.

Sintering Temperature (℃) Sintering Time (hr) Breakdown Voltage (V1mA) Capacity (pF at 1 MHz) Leakage Current (㎂ at 24 V) 850 2 265 0.10 0.67 850 5 228 0.11 0.53 950 2 185 0.13 0.50

( Example  5)

When changing the overlapping area of the internal electrodes of the multilayer chip varistor sheet made in the same manner as in the first preferred embodiment described above, a varistor of 0.02 pF is completed as shown in Table 8. Thus, the size of the overlapping region of the inner electrode can be used to substantially adjust the capacitance.

Overlap area of the inner electrode (mm ² ) 0.12 0.06 0.03 Capacity (pF at 1 MHz) 0.12 0.07 0.03

As can be seen in the above-described embodiments, after adjusting various parameters, the multilayer chip varistor according to the present invention has a very low capacity, and particularly protects the high frequency circuit against electric overloads such as electrostatic or transient surges. It is suitable for application.

As described above, according to the low-capacity multilayer chip varistor, the present invention has an inorganic glass film having high temperature resistance in the semiconductive or conductive particles of the ceramic body to withstand the heat generated when suppressing electrostatic shock or surge electric overload. It contains 0.1 micron or nanometer semiconducting or conductive particles for secondary dispersion, and the gap between particles is very small, which has a tunnel effect in case of abnormal electrical overload, low capacity multilayer chip varistors suppress electrical overload, It is resistant to electrostatic shock and has a long life time effect.

Claims (8)

delete A material with micropores for electrical overload protection, used between positive and negative electrodes to suppress transients, surge voltages and electrostatic shocks, 50-97 with inorganic glass of 3-50% by weight and particle size larger than 0.1 micron In a ceramic material for preventing electrical overload, comprising a semi-conductive or conductive particle by weight, and covering the surface of the semi-conductive or conductive particle with a layer of an inorganic glass film, The inorganic glass film comprises semi-conductive or conductive particles of less than 1 micron or nanometer, the content of the semi-conductive or conductive particles is less than 20% by weight of the content of the inorganic glass, the ceramic for preventing electrical overload material. delete The method of claim 2, The semiconductive particles are one selected from ZnO, TiO ₂ , SnO ₂ , Si, Ge, SiC, Si-Ge alloy, InSb, GaAs, InP, GaP, ZnS, ZnSe, ZnTe, SrTiO ₃ and BaTiO ₃ , The conductive particles are selected from Pt, Pd, W, Au, Al, Ag, Ni, Cu, and alloys thereof. delete A low capacitance multi-layer chip varistor having a capacitance of less than 0.5 pF at 1 MHz, comprising a ceramic body, external electrodes disposed at two ends of the ceramic body and internal electrodes disposed therein, wherein the ceramic body has three to An electrical overload ceramic comprising 50 wt% inorganic glass and 50 wt% to 97 wt% semiconductive or conductive particles having a particle size greater than 0.1 μm and covering the surface of the semiconductive or conductive particles with a layer of an inorganic glass film In low-capacity multilayer chip varistors using materials, The inorganic glass film contains semiconducting or conductive particles of submicron or nanometer smaller than 1 micron, and the content of the semiconducting or conductive particles is 20 wt% less than the content of the inorganic glass. Low capacity multilayer chip varistors using materials. delete The method of claim 6, The semiconductive particles are one selected from ZnO, TiO ₂ , SnO ₂ , Si, Ge, SiC, Si-Ge alloy, InSb, GaAs, InP, GaP, ZnS, ZnSe, ZnTe, SrTiO ₃ and BaTiO ₃ , The conductive particles are Pt, Pd, W, Au, Al, Ag, Ni, Cu and alloys of low capacity multilayer chip varistor using a ceramic material for preventing electrical overload, characterized in that at least one of them.

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