JP2008243582A - 有機薄膜トランジスタ基板及びその製造方法、並びに、画像表示パネル及びその製造方法 - Google Patents
有機薄膜トランジスタ基板及びその製造方法、並びに、画像表示パネル及びその製造方法 Download PDFInfo
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- JP2008243582A JP2008243582A JP2007082278A JP2007082278A JP2008243582A JP 2008243582 A JP2008243582 A JP 2008243582A JP 2007082278 A JP2007082278 A JP 2007082278A JP 2007082278 A JP2007082278 A JP 2007082278A JP 2008243582 A JP2008243582 A JP 2008243582A
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Abstract
【解決手段】 基板上の第1領域に有機薄膜トランジスタが形成され、第1領域に隣接して発光素子を形成するための第2領域を有しており、第2領域の周縁部にバンク部が形成された有機薄膜トランジスタ基板の製造方法であって、基板上の第1領域に、有機薄膜トランジスタを形成するとともに、この有機薄膜トランジスタが有するゲート絶縁層及び有機半導体層のうちの少なくとも一方を第2領域にまで形成して、第2領域に当該領域上に形成された積層構造からなるバンク前駆体層を形成する第1工程、及び、バンク前駆体層における周縁部以外の領域を除去して、残存したバンク前駆体層からなるバンク部を形成する第2工程を有する。
【選択図】 図3
Description
[第1実施形態]
[第2実施形態]
Claims (12)
- 基板上の第1領域に有機薄膜トランジスタが形成され、前記第1領域に隣接して発光素子を形成するための第2領域を有しており、前記第2領域の周縁部にバンク部が形成された有機薄膜トランジスタ基板の製造方法であって、
前記基板上の前記第1領域に、ゲート電極、ゲート絶縁層、該ゲート絶縁層の前記ゲート電極に対して反対側に形成されたソース電極及びドレイン電極、並びに、前記ゲート絶縁層の前記ゲート電極に対して反対側に形成され前記ソース電極及び前記ドレイン電極の両方に接する有機半導体層を少なくとも備える有機薄膜トランジスタを形成するとともに、前記ゲート絶縁層及び前記有機半導体層のうちの少なくとも一方を前記第2領域にまで形成して、前記第2領域に当該領域上に形成された積層構造からなるバンク前駆体層を形成する第1工程と、
前記バンク前駆体層における前記周縁部以外の領域を選択的に除去して、残存した前記バンク前駆体層からなる前記バンク部を形成する第2工程と、
を有することを特徴とする有機薄膜トランジスタ基板の製造方法。 - 前記第1工程において、
前記基板上の前記第1領域にゲート電極を形成し、
前記基板上の前記第1領域及び前記第2領域に前記ゲート電極を覆うようにゲート絶縁層を形成し、
前記第1領域の前記ゲート絶縁層上にソース電極及びドレイン電極を形成し、
前記第1及び第2領域の前記ゲート絶縁層上に、前記ソース電極及び前記ドレイン電極を覆うように有機半導体層を形成し、
前記第1領域と、前記第2領域における前記周縁部と、を含む領域の前記有機半導体層上にマスク層を形成し、
前記第2工程において、
エッチングを行うことにより前記マスク層で覆われていない領域の前記バンク前駆体層を選択的に除去する、
ことを特徴とする請求項1記載の有機薄膜トランジスタ基板の製造方法。 - 前記第1工程において、
少なくとも前記ゲート絶縁層を形成する前に、前記基板上の前記第2領域に前記発光素子用の下部電極を形成し、
前記ゲート絶縁層を形成した後に、当該ゲート絶縁層の一部に開口を設け、
前記ドレイン電極の形成時又は形成後に、前記開口により前記ドレイン電極と前記下部電極を接続させ、
前記第2工程において、
前記第2領域の前記下部電極上に形成された前記バンク前駆体層を選択的に除去する、
ことを特徴とする請求項2記載の有機薄膜トランジスタ基板の製造方法。 - 前記第1工程において、前記有機半導体層と前記マスク層との間に保護層を形成する、ことを特徴とする請求項2又は3記載の有機薄膜トランジスタの製造方法。
- 前記第1工程において、
前記基板上の前記第1領域に前記ソース電極及び前記ドレイン電極を形成し、
前記基板上の前記第1及び第2領域に、前記ソース電極及び前記ドレイン電極を覆うように前記有機半導体層を形成し、
前記第1及び第2領域の前記有機半導体層上に前記ゲート絶縁層を形成し、
前記第1領域の前記ゲート絶縁層上に前記ゲート電極を形成し、
前記第1領域と、前記第2領域における前記周縁部とを、を含む領域の前記ゲート絶縁層上に、前記ゲート電極を覆うようにマスク層を形成し、
前記第2工程において、
エッチングを行うことにより前記マスク層で覆われていない領域の前記バンク前駆体層を選択的に除去する、
ことを特徴とする請求項1記載の有機薄膜トランジスタ基板の製造方法。 - 前記第1工程において、
少なくとも前記有機半導体層を形成する前に、前記基板上の前記第2領域に前記発光素子用の下部電極を形成し、
前記ドレイン電極の形成時又は形成後に、前記ドレイン電極と前記下部電極を接続させ、
前記第2工程において、
前記第2領域の前記下部電極上に形成された前記バンク前駆体層を選択的に除去する、
ことを特徴とする請求項5記載の有機薄膜トランジスタ基板の製造方法。 - 前記第1工程において、前記ゲート絶縁層と前記マスク層との間に保護層を形成する、ことを特徴とする請求項5又は6記載の有機薄膜トランジスタ基板の製造方法。
- 基板上の第1領域に有機薄膜トランジスタが形成され、前記第1領域に隣接して発光素子を形成するための第2領域を有しており、前記第2領域の周縁部にバンク部が形成された有機薄膜トランジスタ基板であって、
前記有機薄膜トランジスタは、ゲート電極、ゲート絶縁層、該ゲート絶縁層の前記ゲート電極に対して反対側に形成されたソース電極及びドレイン電極、並びに、前記ゲート絶縁層の前記ゲート電極に対して反対側に形成され前記ソース電極及び前記ドレイン電極の両方に接する有機半導体層を少なくとも備えるものであり、
前記バンク部は、前記ゲート絶縁層及び前記有機半導体層のうちの少なくとも一方の層と同一の材料から構成される層を含む、
ことを特徴とする有機薄膜トランジスタ基板。 - 前記バンク部は、前記ゲート絶縁層と同一の材料から構成される層、及び、前記有機半導体層と同一の材料から構成される層の両方を含む、ことを特徴とする請求項8記載の有機薄膜トランジスタ基板。
- 前記基板上の前記第2領域には、前記発光素子用の下部電極が形成されている、ことを特徴とする請求項8又は9記載の有機薄膜トランジスタ基板。
- 基板と、前記基板上の第1領域に形成された有機薄膜トランジスタと、前記基板上の前記第1領域に隣接する第2領域に形成された発光素子と、前記基板上の前記第2領域の周縁部に前記発光素子を囲むように形成されたバンク部と、を有する画像表示パネルの製造方法であって、
前記基板上の前記第1領域に、ゲート電極、ゲート絶縁層、該ゲート絶縁層の前記ゲート電極に対して反対側に形成されたソース電極及びドレイン電極、並びに、前記ゲート絶縁層の前記ゲート電極に対して反対側に形成され前記ソース電極及び前記ドレイン電極の両方に接する有機半導体層を少なくとも備える有機薄膜トランジスタを形成するとともに、前記基板上の前記第2領域に前記発光素子用の下部電極を形成した後、前記ゲート絶縁層及び前記有機半導体層のうちの少なくとも一方の層を前記第2領域にまで形成して、前記第2領域の前記下部電極上に形成された積層構造からなるバンク前駆体層を形成する第1工程と、
前記バンク前駆体層における前記周縁部以外の領域を選択的に除去して、残存した前記バンク前駆体層からなる前記バンク部を形成して有機薄膜トランジスタ基板を得る第2工程と、
前記下部電極上の前記バンク部に囲まれた領域に、少なくとも発光層及び前記発光素子用の上部電極を順次形成して前記発光素子を形成する第3工程と、
を有することを特徴とする画像表示パネルの製造方法。 - 基板と、該基板上の第1領域に形成された有機薄膜トランジスタと、前記基板上の前記第1領域に隣接する第2領域に形成された発光素子と、前記基板上の前記第2領域の周縁部に前記発光素子を囲むように形成されたバンク部と、を有する画像表示パネルであって、
前記有機薄膜トランジスタは、ゲート電極、ゲート絶縁層、該ゲート絶縁層の前記ゲート電極に対して反対側に形成されたソース電極及びドレイン電極、並びに、前記ゲート絶縁層の前記ゲート電極に対して反対側に形成され前記ソース電極及び前記ドレイン電極の両方に接する有機半導体層を少なくとも備えており、
前記バンク部は、前記ゲート絶縁層及び前記有機半導体層のうちの少なくとも一方の層と同一の材料から構成される層を含む、
ことを特徴とする画像表示パネル。
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JP2009134905A (ja) * | 2007-11-29 | 2009-06-18 | Casio Comput Co Ltd | 表示パネル及びその製造方法 |
US9011729B2 (en) | 2010-04-22 | 2015-04-21 | Idemitsu Kosan Co., Ltd. | Organic thin-film transistor |
JP2015119190A (ja) * | 2010-02-12 | 2015-06-25 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
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CN101647320A (zh) | 2010-02-10 |
US8030125B2 (en) | 2011-10-04 |
EP2136606A4 (en) | 2011-04-06 |
TW200904241A (en) | 2009-01-16 |
US8324627B2 (en) | 2012-12-04 |
EP2136606B1 (en) | 2012-05-16 |
TWI442815B (zh) | 2014-06-21 |
US20100072464A1 (en) | 2010-03-25 |
KR101441159B1 (ko) | 2014-09-17 |
WO2008123244A1 (ja) | 2008-10-16 |
KR20090128511A (ko) | 2009-12-15 |
EP2136606A1 (en) | 2009-12-23 |
US20110309366A1 (en) | 2011-12-22 |
JP5372337B2 (ja) | 2013-12-18 |
CN101647320B (zh) | 2012-12-12 |
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