JP2008243170A - Data processing control method, and data processing unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processing control method and a data processing unit capable of avoiding a collision in reading data when a data processing means reads data from a memory means, and preventing the repeated occurrence of resetting. <P>SOLUTION: A reset signal in an ASIC section 11 is detected. When the reset signal is detected, a clock signal is outputted from the ASIC section 11 to an SDRAM 12, and a clock enable signal and a data mask control signal which are set high are outputted. The SDRAM 12 acquires the clock signal, the clock enable signal and the data mask control signal. Based on the acquired clock signal and the clock enable signal, a predetermined time period is measured. After the lapse of the predetermined time period, data outputted from the SDRAM 12 are suspended based on the data mask control signal, and the ASIC section 11 is reset based on the reset signal. When restart is performed after the reset, program information is outputted from a FLASH 13 to the ASIC section 11. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data processing control method in a configuration including a plurality of memory means for data processing means, and a data processing apparatus for realizing the data processing control method.

In a conventional mobile phone, a device that contributes to reducing current consumption, such as PSRAM (Pseudo Static Random Access Memory), is used in order to suppress current consumption in the standby mode. If this device is used in 16-bit burst mode, a certain level of performance can be secured. However, current VoIP (Voice over Internet Protocol) mobile phones require high-speed CPU processing, and higher performance is required. The
Therefore, high performance is realized by using SDRAM (Synchronous Dynamic Random Access Memory) and operating at high speed by 32-bit burst transfer. Since this SDRAM is an inexpensive device, the use of SDRAM has a great merit in terms of cost reduction.

  By the way, when the same bus is shared in a configuration in which SDRAM and FLASH (Flash Memory) as storage means are used in combination with ASIC (Application Specific Integrated Circuit) as data processing means (see Patent Document 1), that is, SDRAM. When FLASH and FLASH are connected to a memory control unit (MEMMC) in the ASIC unit using the same bus, a bus collision occurs at the time of reset (RESET).

While the collision occurs, the FLASH connected to the MEMC falls into an inaccessible state. For this reason, until now, an SDCKE (SDRAM LocK Enable) signal (clock valid signal) is changed from H (High) level to L (Low) level and then reset is applied.
JP 2001-5723 A

However, when the program is expanded and operated in the SDRAM, the supply of the clock signal (CLK) is stopped along with the reset. Although the MEMC side is reset, the SDRAM keeps the previous state because there is no supply of CLK. When the data read is just before the reset, the SDRAM is stopped with data on the data line. In this case, the SDRAM is not initialized because it does not have a reset input terminal. Therefore, when the program is initialized at the time of reset and FLASH starts from address 0, a collision occurs on the data bus with the read data of the SDRAM.
For this reason, the CPU cannot start the program and has to rely on resetting by a watchdog timer (WDT), so that the work of repeating resetting has occurred.

Further, when the SDCKE signal becomes L level, it is not necessarily only the end signal of the cycle. For example, even when the suspend mode (SUSPEND MODE) is entered, it is at L level. In that case, the bus is not in a released state, but is in a state of holding or maintaining its cycle, and a similar state can occur. Therefore, it is necessary to shorten the recovery time associated therewith. In addition, command restrictions occur on the system, creating a difficult situation when creating software.
SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing control method and a data processing apparatus that avoid a collision at the time of reading data when the data processing means reads data from the storage means, and does not cause a work to repeat resetting. is there.

  To achieve the above object, a data processing control method according to the present invention comprises a data processing means, a first memory means connected to the data processing means and holding data processed by the data processing means, and a program A data processing control method in a data processing device including a second memory means storing information, the step of detecting a reset signal in the data processing device, and if the reset signal is detected, the data processing Outputting a clock signal from the means to the first memory means and setting the clock enable signal and the data mask control signal to high, and the memory means includes the clock signal, the clock enable signal and the data. A step of acquiring a mask control signal, and the acquired clock signal and clock signal; Measuring a predetermined time based on a table signal, and stopping output of data from the first memory means based on the data mask control signal after elapse of the predetermined time; and based on the reset signal, A step of resetting the data processing device; and a step of outputting program information from the second memory means to the data processing means when restarted after the resetting.

In the present invention, it is preferable that the reset of the data processing device is executed after the output of data from the first memory means is stopped.
In the present invention, it is preferable that the stop of data output from the first memory means is executed during a reset process in the data processing device.
In addition, the present invention further includes a step of detecting a momentary power interruption, and when the momentary interruption is detected, when the power source is turned on from the momentary interruption state, the data It is preferable to perform a reset in the processing device.

  A data processing apparatus according to the present invention comprises a data processing means, a first memory means connected to the data processing means for holding data processed by the data processing means, and a second memory storing program information. A data processing device comprising: a memory means; a reset signal detecting means for detecting a reset signal in the data processing device; and a clock signal output to the first memory means when the reset signal is detected. And an output signal control means for controlling the clock enable signal and the data mask control signal to be output at a high level, wherein the first memory means is controlled by the output signal control means, and the data The clock signal, clock enable signal and data mask control signal output from the processing means are acquired and acquired. A data output stop control means for measuring a predetermined time based on the clock signal and the clock enable signal, and controlling the output of data to be stopped based on the data mask control signal after the predetermined time has elapsed, The data processing means further includes a control signal output means for outputting a control signal for outputting program information from the second memory means when the data processing device is reset and restarted. It is characterized by that.

  Further, the present invention provides an instantaneous interruption detecting means for detecting an instantaneous interruption of a power supply, and when the instantaneous interruption is detected, when the power supply is turned on from the instantaneous interruption state, It is preferable to further include reset control means for controlling the data processing device to be reset.

  According to the present invention, when the data processing means reads data from the storage means at the time of restart after resetting, it is possible to reliably avoid a collision at the time of data reading, so that the work of repeating the reset does not occur. Furthermore, it is possible to cope with the occurrence of a momentary power interruption.

The best mode for carrying out the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing a system configuration of a reception control apparatus including a data processing apparatus according to the first embodiment of the present invention. Here, a mobile phone will be described as an example of the reception control device.
As shown in FIG. 1, the data processing apparatus 10 is connected to an ASIC unit (data processing means) 11 that processes an input signal and an SDRAM (first data processor) that is connected to the ASIC unit 11 and holds data processed by the ASIC unit 11. Memory means) 12 and FLASH (second memory means) 13 in which program information is stored, and is provided in the reception control device 14.

The reception control device 14, together with the data processing device 10, an RF transmission / reception unit 16 that performs signal transmission / reception with a base station (not shown) via an antenna 15, a liquid crystal display unit (LCD) 17, and an audio signal A A codec unit 18 that performs -D (Analog-Digital) / DA conversion, a speaker 19 for a telephone, a microphone 20 for a telephone, and a key input unit 21 for inputting information by a user are provided.
The ASIC unit 11 internally controls a baseband unit 22 that modulates and demodulates signals, a CPU (Central Processing Unit) 23 that controls signals in the ASIC unit 11, an SDRAMC unit 24 that controls the SDRAM 12, and a FLASH 13. An SRAMC unit 25 is provided. A program required for driving the ASIC unit 11 is expanded from the FLASH 13 to the SDRAM 12 and stored when the reception control device 14 is turned on (at the initial time).

FIG. 2 is a block diagram showing the configuration of the SDRAMC unit of FIG. As shown in FIG. 2, the SDRAMC unit 24 includes an address / data latch circuit 26, a refresh control circuit 27, a control signal generation unit (sequencer) 28, and a row / column address signal switching circuit 29. It is connected to the CPU 23 via an advanced high-performance bus (30).
DATA from the address / data latch circuit 26, address (AD) from the row / column address signal switching circuit 29, SDQM (data mask signal) from the control signal generator 28, CKE, SDCS /, RAS /, CAS /, Each signal line of WE / and SDCLK / is connected to the SDRAM 12.

  FIG. 3 is a block diagram showing a configuration example of a signal generation circuit in the ASIC section of FIG. As shown in FIG. 3, in the ASIC unit 11, soft reset, hard reset, and WDT signals are input to the negative logical sum (negative logical OR) circuit 32 of the reset control unit (RESETC unit) 31, and the negative logic The sum output is input to the delay circuit 33, the fall detection circuit 34, and the selectors 35 and 36. The output from the fall detection circuit 34 is input to a logical product (AND) circuit 38 together with the output from the mode register 37 of the SDRAMC unit 24, and output from the control unit 39 of the SDRAMC unit 24 together with the output from the AND circuit 38. A signal (SDRAM Clock Enable: SDCKE) for operating SDCLK is input to the D flip-flop (D-FF) circuit 40. The D-FF circuit 40 is set to H by forced reset. Then, the SDCKE signal is output from the D-FF circuit 40.

  The output from the mode register 37 of the SDRAMC unit 24 is input to the control unit 39 through the selector 35, and other control signals, for example, SDCS / = L, RAS /, from the control unit 39 to the SDRAM 12 through the selector 36. = H, CAS / = H, WE / = H are output. Note that H represents High and L represents Low. A burst stop command is input to the selectors 35 and 36. The SDCKE signal from the control unit 39 is input to the negative logical product (negative logical AND) circuit 41 together with the output from the delay circuit 33, and the entire internal reset signal and the external reset signal are output from the negative logical AND circuit 41. The output signal is input to the output signal control unit 42, and the output from the output signal control unit 42 is output to the SDRAM 12.

Further, when the SDQM signal and the MEMCLK signal from the control signal unit (not shown) of the SDRAMC unit 24 are input to the D-FF circuit 40 and the output from the falling detection circuit 34 is input, the D-FF circuit 40 outputs an SDQM signal.
Here, a specific processing example of the SDCKE signal and the SDQM signal is shown. Table 1 shows a case where an SDCKE signal is processed, and Table 2 shows a case where an SDQM signal is processed.

  FIG. 4 is a block diagram showing the configuration of the SDRAM bus release means. As shown in FIG. 4, the SDRAM bus release means 43 provided as an additional circuit in the ASIC section 11 added to the existing circuit includes an output signal control means 42 (see FIG. 3) and a reset signal detection. Means 44 are provided. A control output signal from the reset signal detecting means 44 is input to the SDRAM bus releasing means 43 by inputting nPORST at power-on, RESET (PRESET) from the PCMCIA, SOFTRST, general-purpose REST (nUREST), and WDTRST. Is input to the output signal control means 42. The output signal control means 42 is in the truth value, default (DEFAULT), and reset (RESET) in the reference signal (SDCLK) for operating each signal of SDCKE, SDQM, and SDRAM. The control process for is performed.

The bus release means 43 outputs the controlled signals SDCKE, SDQM and SDCLK to the SDRAM 12 connected to the bus (BUS). Each signal is input to the data output stop control means 45 of the SDRAM 12. The bus release means 43 outputs ASIC internal RST and RESETOUT signals.
The bus release means 43 first performs a process of delaying reset (reset after supplying each signal to the SDRAM 12), and then outputs a bus release command to forcibly release the bus.

  That is, the falling detection circuit 34, the control unit 39 (see FIG. 3), and the reset signal detection unit 44 (see FIG. 4) function as a reset signal detection unit that detects a reset signal in the data processing apparatus 10, and output signals The control unit 42, the control unit 39 (see FIG. 3), and the output signal control means 42 (see FIG. 4) output a clock signal (SDCLK) to the SDRAM 12 and detect the clock enable when detecting the reset signal. It functions as an output signal control means for controlling the signal (SDCKE) and the data mask control signal (SDQM) to be output with a high level.

Further, the data output stop control means 45 (see FIG. 4) is controlled by the output signal control means 42, acquires the clock signal, clock enable signal and data mask control signal output from the ASIC 11, and acquires the acquired clock signal and It functions as a data output stop control unit that measures a predetermined time based on the clock enable signal and controls to stop the output of data based on the data mask control signal after the predetermined time has elapsed.
The SRAMC unit 25 (see FIG. 1) functions as a control signal output unit that outputs a control signal for outputting program information from the FLASH 13 when the ASIC unit 11 is reset and restarted.

Next, a data processing control method in the data processing apparatus of FIG. 1 will be described.
First, a reset signal in the data processing device 10 is detected. When this reset signal is detected, the clock signal (SDCLK) is output from the ASIC 11 to the SDRAM 12, and the clock enable signal (SDCKE) and the data mask control signal (SDQM) are set high (High).
Next, the SDRAM 12 acquires a clock signal, a clock enable signal, and a data mask control signal, measures a predetermined time based on the acquired clock signal and clock enable signal, and after the predetermined time has elapsed, that is, at least two clocks. After the delay, the output of data from the SDRAM 12 is stopped based on the data mask control signal.

After the data output from the SDRAM 12 is stopped, the ASIC 11 is reset based on the reset signal. When the ASIC 11 is restarted after the reset, program information is output from the FLASH 13 to the ASIC 11.
The reset of the data processing device 10 is executed after the output of data from the SDRAM 12 is stopped, and the stop of the data output from the SDRAM 12 is executed during a reset process in the data processing device 10.

Thus, the SDRAM bus release means 43 is
(1) Reset instruction signal at power-on (at initial startup) (2) Signal indicating reset instruction from external device (3) Reset control signal (command) from internal software
(4) Signal indicating reset instruction from other CPU (5) Signal from watchdog timer (WDT) (signal for returning system (device) operation to normal when system (device) malfunctions)

When these signals are input, the SDCKE, SDQM, and SDCLK signals for releasing the data bus are output from the ASIC 11 to the SDRAM 12. Then, the SDRAM 12 acquires the signals SDCKE, SDQM, and SDCLK, thereby releasing the data bus after a predetermined period (at least two clocks have elapsed).
As a result, when the ASIC 11 reads data from the FLASH 13 after restarting, data collision can be reliably avoided.
As described above, a bus collision between the SDRAM 12 and the FLASH 13 can be avoided at the time of resetting, which will be further described.

Hereinafter, an example of i-BURST (registered trademark) will be described. In the case of i-BURST, high-speed CPU processing is indispensable, and a CPU executing management of baseband (B / B) processing and operation processing support cannot process unless it is operated at least at 72 M or more. This is one of the factors that require performance.
Considering the low cost and high speed correspondence, the cost performance is much better than the pseudo SRAM, so a method of using this somehow will be described.

On the other hand, regarding the usage of SDRAM, the CPU operates a sequencer of SDRAMC by issuing a command, generates a control signal to SDRAM, and executes data transmission / reception. This transition is managed by the CPU, and the command is issued to the memory controller side. When there is a signal SDCKE and there is no access, the SDRAMC sets SDCKE to L. The MEMC side is divided into an SDRAMC side and an SRAMC side. Since the bus is a common bus, the FLSH and SDRAM buses collide.
Therefore, as a first example, even when the FLSH and SDRAM buses are separated by another bus and a reset (RESET) is applied, the FLSH returns to normal access. Since the SDRAM is initialized again, there is no problem. However, in this case, since the bus is an exclusive bus, there is a demerit that the number of bus systems is increased, but the merit is greater than that which leads to a malfunction in the system.

As a second example, this bus collision occurs because the SDRAM is in the bus read state and does not release the bus. In the write cycle, since the CPU and MEMC are initialized on the hardware when a reset occurs, the reset from the CPU side works effectively. Then, during the cycle in which the SDRAM releases the data, the SDRAMC is created so that the reset is performed after the end of the cycle without performing the reset. Or, when a reset is applied, the reset initiates a data release cycle.
As a third example, when a reset is applied, it is ignored after that cycle, so that the bus is forcibly floated. That is, the clock is maintained and the DQM signal is maintained at H. In that state, the whole is reset with a delay.

As a fourth example, when a burst stop (BURST STOP) command is generated, the data bus is released. For this reason, when a hardware reset occurs, an example of generating a bit corresponding to a pseudo command and forcibly operating a braking unit (1), and not a control signal generating unit after reset detection An example (2) is shown in which the control signal corresponding to the burst stop command is forcibly switched by the multiplexer, and the SDRAM receives the burst stop command. In these examples (1) and (2), after the SDRAM releases the bus, the entire reset occurs. This is an example of dealing with an additional circuit without breaking the conventional control sequence.
When a soft reset occurs, a soft reset may be issued after a burst stop command is generated and the data bus is released (example (3)).

By forming such a mechanism by adding simple hard logic to the SDRAM controller side, it is possible to master SDRAM and reset without offsetting the superior advantages (cost performance and high speed) of SDRAM. FLASH can be accessed regardless of whether the SDRAM is in the REFRESH state.
This, in turn, simplifies the system and removes restrictions on the program, leading to a reduction in program complexity and development time. In addition, damage to FLASH and SDRAM due to bus collision can be avoided, and further, it contributes to lower current consumption that has been increased due to bus collision.
(Second Embodiment)

FIG. 5 is a block diagram showing a system configuration of a reception control apparatus provided with a data processing apparatus according to the second embodiment of the present invention. Here, a mobile phone will be described as an example of the reception control device.
As shown in FIG. 5, the data processing device 50 includes an instantaneous interruption detection unit (instantaneous interruption detection unit) 51 and a reset controller (reset control unit) 53 provided in an ASIC unit (data processing unit) 52. Other configurations and operations are the same as those of the data processing apparatus 10 (see FIG. 1) having the ASIC unit 11 shown in the first embodiment.

In other words, the ASIC unit 52 further includes a reset controller 53 in the ASIC unit 11 including the baseband unit 22, the CPU 23, the SDRAMC unit 24, and the SRAMC unit 25, and the instantaneous interruption detection unit is included in the reset controller 53. The instantaneous interruption detection signal from 51 is input.
The instantaneous interruption detecting unit 51 detects an instantaneous interruption of the power supply, and when the reset controller 53 detects the instantaneous interruption, when the power supply is turned on (ON) from the instantaneous interruption state, a predetermined time elapses. Then, the data processing device 50 is controlled to be reset. The instantaneous interruption detection unit 51 and the reset controller 53 may be provided separately, or may be provided integrally in the ASIC unit 52.

In the case of the data processing apparatus 10 according to the first embodiment described above, it was possible to cope with the normal restart (reset), but the voltage dropped momentarily or the power was turned off (OFF). In the event of a momentary interruption (momentary power failure), it is not supported.
In mobile phones, etc., for example, if a momentary interruption occurs due to a decrease in battery capacity, etc., the system goes down all at once. Since it is not allowed, a restart is required. However, since a bus collision occurs when restarting at a momentary interruption, a delay time is provided when a restart signal is input.

FIG. 6 is an explanatory diagram illustrating the transition state of the power supply voltage and the reset input signal in a graph. As shown in FIG. 6, when the power supply voltage VDD decreases, neither the circuit nor its peripheral part can operate normally. Therefore, a delay time (predetermined time) tD is provided during the rise of the power supply voltage VDD, and the delay time tD elapses. Later, the input stop of the restart input signal RESIN is released. That is, the data processing device 50 is reset.
During this delay time tD, a restart output signal generation time of about 10 ms is taken, and the SDRAM bus is released within this time, so that no bus collision occurs even in the restart at the moment of interruption.

That is, when the power is turned off, no power is supplied, so the system falls into an unstable state. After that, since the transition is made as shown in FIG. 6, the generation timing of the delay time tD is shown in FIG. In the transition period until the power is turned off, the processing is performed in the transition period from off to on.
FIG. 7 is an explanatory diagram showing input / output signals among the power supply, the instantaneous interruption detecting unit, and the reset controller. As shown in FIG. 7, the instantaneous interruption detection unit 51 to which the power supply voltage signal is supplied from the power supply 54 to the VDD unit detects the instantaneous interruption of the power supply 54, and sends the instantaneous interruption detection signal from the RESOUT unit to the ASIC unit 52. Output to the reset controller 53. When the instantaneous interruption detection signal is input to the n_POR unit of the reset controller 53, the reset controller 53 outputs the restart output signal RESETOUT after the delay time tD has elapsed.

The delay time tD can be arbitrarily set by selecting constants for the external capacitor capacitance C and the delay circuit resistance R.
FIG. 8 is a circuit diagram showing an example of a restart output signal generation circuit in the reset controller of FIG. As shown in FIG. 8, the reset controller 53 generates a restart output signal RESET_OUT that includes, for example, AND circuits 54 and 55, a pulse extender logic 56, and shift registers 57 and 58. It has a circuit.

  The AND circuit 54 receives the soft_reset_n signal and the WDT_rst_n signal, and the pulse adjuster 56 receives the output signal from the AND circuit 54. The AND circuit 55 receives an n_POR signal, an n_URESET signal, and a pc_host_soft_reset_n signal that are reset signals generated when the power is turned on or is instantaneously interrupted, and a PRESET signal is inverted and further input from the pulse adjustment unit 56. Output signal is input.

A clock (SBCLK) signal, a “1” signal, and an output signal from the AND circuit 55 are input to the shift register 57, and a clock (SBCLK) signal and an output signal from the shift register 57 are input to the shift register 58. The n_RESET_OUT signal and the output signal from the AND circuit 55 are input. Then, the shift register 57 outputs an n_RESET_OUT signal, and the shift register 58 outputs an rstc_n_asic_n (internal logic) signal.
Then, at the moment of power interruption, the reset controller 53 generates a RESET_OUT signal. The restart output signal generation circuit shown in FIG. 8 also generates a RESET_OUT signal when the power is turned on.

  With the data processing apparatus 50 having the above-described configuration, the SDRAM can access the FLASH because the SDRAM releases the data bus and does not collide with the FLASH bus even when the power supply is interrupted or restarted. Therefore, the restart time can be shortened. This in turn leads to simplification of the system and reduction of program development time, and it is possible to avoid damage to FLASH and SDRAM due to bus collision, and to reduce current consumption that increases due to bus collision. You can also.

Thus, in the data processing apparatus 50, 1. 1. Reset is not repeated on the system with a simple circuit configuration. 2. The previous system configuration can be used. 3. Bus collision can be avoided by adding simple logic. 4. The initialization time due to bus collision can be shortened. 5. Can cope with instantaneous interruption. 6. Device damage due to bus collision can be eliminated for both FLASH and SDRAM. It is possible to obtain various effects that it is possible to fundamentally cope with a simple circuit addition without changing the sequence up to now.
Although the present invention has been described with reference to the above-described embodiment, it is not limited to this embodiment. Therefore, what is implemented as a change aspect without deviating from the meaning of the present invention is also included.

It is a block diagram which shows the system configuration | structure of the reception control apparatus provided with the data processor which concerns on one embodiment of this invention. FIG. 2 is a block diagram illustrating a configuration of an SDRAMC unit in FIG. 1. FIG. 2 is a block diagram illustrating a configuration example of a signal generation circuit in the ASIC unit in FIG. 1. It is a block diagram which shows the structure of the bus release means of SDRAM. It is a block diagram which shows the system configuration | structure of the reception control apparatus provided with the data processor which concerns on 2nd Embodiment of this invention. It is explanatory drawing which shows the transition state of a power supply voltage and a reset input signal with a graph. It is explanatory drawing which shows the input / output signal between a power supply, a momentary interruption detection part, and a reset controller. FIG. 8 is a circuit diagram illustrating an example of a restart output signal generation circuit in the reset controller of FIG. 7.

Explanation of symbols

10, 50 Data processing device 11 ASIC section 12 SDRAM
13 FLASH
14 Reception Control Device 15 Antenna 16 RF Transmitter / Receiver 17 LCD
18 Codec part 19 Speaker 20 Microphone 21 Key input part 22 Baseband part 23 CPU
24 SDRAMC section 25 SRAMC section 26 Address / data latch circuit 27 Refresh control circuit 28 Control signal generating section 29 Row / column address signal switching circuit 30 AHB
31 Reset control unit 32 Negative logic OR circuit 33 Delay circuit 34 Falling detection circuit 35, 36 Selector 37 Mode register 38, 54, 55 AND circuit 39 Control unit 40 D-FF circuit 41 Negative logic AND circuit 42 Output signal control unit 43 Bus release means 44 Reset signal detection means 45 Data output stop control means 51 Instantaneous interruption detection part 52 ASIC part 53 Reset controller 54 Power supply 56 Pulse adjustment part 57, 58 Shift register

Claims (6)

A data processing apparatus comprising: data processing means; first memory means connected to the data processing means for holding data processed by the data processing means; and second memory means for storing program information A data processing control method in
Detecting a reset signal in the data processing device;
If the reset signal is detected, outputting a clock signal from the data processing means to the first memory means, and outputting a clock enable signal and a data mask control signal high; and
The memory means obtains the clock signal, a clock enable signal and a data mask control signal;
Measuring a predetermined time based on the acquired clock signal and clock enable signal, and stopping the output of data from the first memory means based on the data mask control signal after the lapse of the predetermined time;
Resetting the data processing device based on the reset signal;
When restarting after the reset, outputting program information from the second memory means to the data processing means;
A data processing control method comprising:   2. The data processing control method according to claim 1, wherein the reset of the data processing device is executed after the output of data from the first memory means is stopped.   2. The data processing control method according to claim 1, wherein the stop of data output from the first memory means is executed during a reset process in the data processing device. And further comprising detecting a power interruption.
2. The reset in the data processing device is executed after a predetermined time elapses when the instantaneous interruption is detected and the power is turned on from the instantaneous interruption state. Data processing control method. A data processing apparatus comprising: data processing means; first memory means connected to the data processing means for holding data processed by the data processing means; and second memory means for storing program information Because
A reset signal detecting means for detecting a reset signal in the data processing device;
Output signal control means for controlling to output a clock signal to the first memory means and to output the clock enable signal and the data mask control signal high when the reset signal is detected. And
The first memory means includes
The clock signal, clock enable signal and data mask control signal controlled by the output signal control means and output from the data processing means are acquired, and a predetermined time is measured based on the acquired clock signal and clock enable signal. And a data output stop control means for controlling to stop the output of data based on the data mask control signal after the predetermined time has elapsed,
The data processing means further includes a control signal output means for outputting a control signal for outputting program information from the second memory means when the data processing device is reset and restarted. ,
A data processing apparatus. Instantaneous interruption detection means for detecting an instantaneous interruption of the power supply;
Reset control means for controlling to execute reset of the data processing device after elapse of a predetermined time when the instantaneous interruption is detected and the power source is turned on from the instantaneous interruption state; The data processing apparatus according to claim 5, further comprising:

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