JP2019046531A - Serial flash memory reset control device - Google Patents

Abstract

To allow CPU to restart properly even if reset is given while accessing serial flash memory.SOLUTION: CPU 11 is provided with GPIO (1) to which data input/output signal 15 between CPU 11 and serial flash memory 12 is input, and GPIO (2) to which another reset signal 18 separated from reset signal 16 is input, and has a function to output reset signal 17 after CPU 11 accesses serial flash memory 12. The serial flash memory 12 is set in a reset mode by the reset signal 17, and the signal 15 input to GPIO (1) is a signal indicating a reset mode state. The CPU 11 confirms whether the signal 15 to GPIO (1) indicates the reset mode state or indicates that the reset mode has been released, and performs reboot processing when release of the reset mode is recognized.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a reset control method in an apparatus equipped with a serial flash memory.

  Currently, in devices such as mobile phones, mobile terminals, and routers, the program data required to operate the device must be large in capacity, so it is stored in flash memory, and the main CPU data Connected to the bus. Many conventional flash memories have a so-called parallel type, but the feature is that a large number of signal lines are required for addresses and data, so that the number of pins is large. In addition, the operation speed was slow.

  Recently, serial flash memory has been developed to improve the problem. However, because of its small capacity at the beginning of development, it was not used as a memory for high-performance CPUs. As an improvement measure, a method of expanding the address and increasing the capacity was adopted.

  It is necessary to expand the conventional 3-byte address and store the fourth or more bytes in the extended address register in the serial flash memory. However, this extended address register has a problem that it is cleared only by a power reset cycle and reset by an external reset signal.

  The reset requirement of the extended address register is described in Non-Patent Document 1, for example.

"AR # 57744: Design Advisory for Zynq-7000 SoC-Reset requirements for Zynq and QSPI when using flash larger than 16MB", Internet <URL: http: // japan. xilinx. com / support / answers / 57744. html> [Search June 13, 2017]

  In a device equipped with a serial flash memory, for example, when there is some abnormality in the device and the CPU is restarted, the extended address register is not cleared. Therefore, instead of the address “0” originally restarted, the extended address + Since it becomes '0', it cannot start normally.

  Furthermore, even if the extended address is cleared by a power reset cycle or reset by an external reset signal, the serial flash memory is temporarily in a reset mode and cannot be accessed for a certain period of time. It is necessary to have some weight before doing.

  FIG. 4 shows a configuration diagram of reset signals of the conventional CPU and serial flash memory. In FIG. 4, the CPU 11 includes a dedicated I / F (interface) 11 a and transmits a select signal 13 (SEL) and a clock signal 14 (CLK) to the serial flash memory 12. Further, the data input / output signal 15 (D) is exchanged between the dedicated I / F 11 a and the serial flash memory 12.

  The CPU 11 and the serial flash memory 12 are supplied with a reset signal 16 from the outside by a reset switch, for example. The serial flash memory 12 includes an extended address register in which a conventional 3-byte address is extended, and is configured by a serial flash memory using, for example, QSPI (Quad Serial Peripheral Interface).

  With the above configuration, data is read and written from the CPU 11 to the serial flash memory 12 having the extension address register.

  In the circuit shown in FIG. 4, when the CPU 11 is accessing the serial flash memory 12, if the reset is performed by a reset switch or the like (the reset signal 16 is input), the CPU 11 is reset and restarted. Since the memory 12 is in the reset mode, correct data cannot be read from the serial flash memory 12 even if the CPU 11 immediately reads the data in the serial flash memory 12 after canceling the reset. For this reason, the apparatus stops.

  The present invention solves the above-described problems, and an object of the present invention is to provide a serial flash memory reset control device in which a CPU can be normally restarted even if a reset is applied while the serial flash memory is being accessed. There is.

The serial flash memory reset control device according to claim 1 for solving the above-mentioned problem is a serial flash memory reset control device having an extended address register, in which data is read and written by a CPU.
In the CPU, a first input / output port to which a data signal transmitted / received between the CPU and the serial flash memory is input, a first reset signal for power activation, and the first reset signal are separated. A second input / output port to which a second reset signal for the CPU is input;
The CPU
When the second reset signal is input to the second input / output port during the period in which the CPU is accessing the serial flash memory, the serial flash memory A function of outputting a third reset signal to the serial flash memory;
Monitor and recognize whether the data signal transmitted from the serial flash memory to the first input / output port of the CPU is a signal indicating the reset mode state of the serial flash memory or a signal indicating that the reset mode is released Monitoring function to
A function of performing a restart process when the monitoring function recognizes the release of the reset mode,
The serial flash memory is set to a reset mode by the input of the third reset signal, and has a function of using a transmission data signal from the serial flash memory to the first input / output port of the CPU as a signal indicating a reset mode state. It is characterized by being.

  According to a second aspect of the present invention, there is provided the serial flash memory reset control device according to the first aspect, wherein the monitoring function of the CPU is executed by issuing a dummy cycle from the CPU to the serial flash memory.

  The serial flash memory reset control device according to claim 3 is the serial flash memory reset control device according to claim 1, wherein the third reset signal is a power reset cycle in which the power of the serial flash memory is turned off and then turned on again. It is a power control signal to be raised.

  According to the above configuration, the serial flash memory is not a reset signal from the outside while the CPU is accessing the serial flash memory, but is output from the CPU after the access is completed. Reset by reset signal.

  Since the reset mode state of the serial flash memory is monitored based on the data signal input to the first input / output port, the CPU can be restarted after the reset mode is released.

  For this reason, even if the reset switch is pressed while the serial flash memory is being accessed (even if the second reset signal is input), the CPU can be restarted normally, and the CPU can properly restore data from the serial flash memory. It is prevented that the program stops without being read. Further, the writing process is prevented from being interrupted.

According to a fourth aspect of the present invention, there is provided the reset control device for a serial flash memory according to the third aspect.
The power supply reset cycle of the serial flash memory is caused to occur by at least one of the power control signal and the first reset signal.

  According to the above configuration, even when the first reset signal for power activation is input to the CPU (when power reset is generated), the power reset cycle of the serial flash memory can be caused. The reset of the serial flash memory can be synchronized.

(1) According to the first to fourth aspects of the present invention, even if the reset switch is pressed during the access to the serial flash memory (even if the second reset signal is input), the CPU restarts normally. This prevents the CPU from reading data from the serial flash memory and stopping the data normally. Further, the writing process is prevented from being interrupted.
(2) According to the invention described in claim 4, when the first reset signal for power activation is input to the CPU, the reset of the CPU and the serial flash memory can be synchronized.

The circuit block diagram by Example 1 of this invention. The flowchart of the operation | movement by Example 1 of this invention. The circuit block diagram by Example 2 of this invention. The circuit block diagram by Example 3 of this invention. The conventional circuit block diagram.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments.

  The change from the conventional circuit in the present embodiment is that an extension address register is provided, and in the reset controller of the serial flash memory in which data is read and written by the CPU, the reset is a serial that is separated from the reset to the CPU. A flash memory resetting device is provided. Regarding the resetting of the CPU, the power-on and the other switches are separated.

  Furthermore, in order to confirm whether or not the serial flash memory has returned from the reset mode, the data input / output signal is output by the CPU GPIO (General Purpose Input / Output, General Purpose I / O (General Purpose I / O Port)). Configured to monitor. As the serial flash memory, a serial flash memory using QSPI can be applied to the present invention.

  FIG. 1 shows a circuit configuration according to the first embodiment, and the same parts as those in FIG. The CPU 11 is provided with GPIO (1) (first input / output port) to which a data input / output signal 15 (D) transmitted / received between the dedicated I / F 11a and the serial flash memory 12 is input.

  Further, the CPU 11 receives a reset signal 16 for power activation (first reset signal) and another reset signal 18 (second reset signal) separated from the reset signal 16 by other switches. A GPIO (2) (second input / output port) for reading is provided.

  When other reset signal 18 is input to GPIO (2) while CPU 11 is accessing serial flash memory 12, CPU 11 reset signal 17 (R) after CPU 11 finishes accessing serial flash memory 12. ) (Third reset signal for serial flash memory) is output to the serial flash memory 12.

  The serial flash memory 12 is set to the reset mode by the reset signal 17 (R) from the CPU 11, and at that time, the transmission data signal (data input / output signal 15 (D)) from the serial flash memory 12 to the CPU 11 is changed to the reset mode state. It has the function of making the signal shown (for example, high impedance '1').

  Further, the CPU 11 indicates that the data input / output signal 15 (D) input to the GPIO (1) is a signal indicating the reset mode state of the serial flash memory (for example, “1”) or that the reset state is released. It has a monitoring function of monitoring and recognizing whether it is a signal (eg, “0”).

  Further, the CPU 11 has a function of performing its own restart process when the monitoring function recognizes the reset mode cancellation. Other parts are configured in the same manner as in FIG.

  Next, the operation of the first embodiment will be described with reference to FIG. FIG. 2 shows a processing flow performed by the CPU 11 of FIG. In step S101, the other reset signal 18 input to GPIO (2) is read, and it is determined whether or not the reset signal is “0” when the reset is applied by a reset switch or the like.

  If it is determined in step S101 that the other reset signal 18 is “0”, the process proceeds to reset processing. However, if the CPU 11 is accessing the serial flash memory 12 (QSPI), the access is completed. In step S102, the reset signal 17 (R) to the serial flash memory 12 is validated and reset.

  As a result, the serial flash memory 12 enters the reset mode, and the serial flash memory 12 sets the data input / output signal 15 (D) to high impedance ('1').

  In step S104, it is determined whether or not the data input / output signal 15 (D) monitored by GPIO (1) is “0” (that is, a signal indicating that the reset mode has been released).

  Since data is normally pulled up by a resistor, at least all “1” can be read in GPIO (1) during the reset period. The CPU 11 issues a dummy cycle to the serial flash memory 12 to monitor the data (data input / output signal 15 (D)), recognizes that the reset mode has been released when “0” can be read, and in step S105 the CPU 11 Reboot.

  As described above, the serial flash memory 12 is reset not by an external reset signal while the CPU 11 is accessing the serial flash memory 12 but by the reset signal 17 (R) output from the CPU 11 after the access is completed. Is done. Since the reset mode state of the serial flash memory 12 is monitored based on the data input / output signal 15 (D) input to the GPIO (1), the CPU 11 restarts normally after the reset mode of the serial flash memory 12 is released. Is done.

  For this reason, even if the reset switch is pressed while the serial flash memory 12 is being accessed (even if the other reset signal 18 is input), the CPU 11 can be restarted normally. It is prevented from stopping without being read normally. Further, the writing process is prevented from being interrupted.

  In the second embodiment, when the serial flash memory is reset, the external reset signal is not used and the power reset cycle of the serial flash memory is used. That is, in place of the reset signal 17 (R) output from the CPU 11 to the serial flash memory 12 of the first embodiment, the power supply of the serial flash memory 12 is turned off and then turned on again to reset the power supply reset cycle of the serial flash memory 12. As shown in FIG. 3, the power supply control signal 27 for causing the above is provided in the GPIO (3) in the CPU 11.

  In FIG. 3, 31 is a transistor that is ON / OFF controlled by the power supply control signal 27 of GPIO (3). When the power supply control signal 27 is OFF, the voltage of the power supply 30 is supplied to the power supply pin of the serial flash memory 12. Instead, when the power control signal 27 is ON, the voltage of the power supply 30 is supplied to the power supply pin of the serial flash memory 12. Other portions are configured in the same manner as in FIG.

  The operation of the circuit in FIG. 3 is the same as that in the flowchart in FIG. 2, but the operation in step S103 in FIG. 2 is replaced with the processing in step S203 described later.

  That is, in step S101, the other reset signal 18 input to GPIO (2) is read, and it is determined whether or not the reset signal is “0” when the reset is applied by a reset switch or the like.

  If it is determined in step S101 that the other reset signal 18 is “0”, the process proceeds to reset processing. However, if the CPU 11 is accessing the serial flash memory 12 (QSPI), the access is completed. In step S203, the power control signal 27 of GPIO (3) is turned off to turn off the serial flash memory 12 and then turn on again to cause a power reset cycle of the serial flash memory 12. .

  As a result, the serial flash memory 12 enters a power supply reset cycle and sets the data input / output signal 15 (D) to high impedance ('1').

  Next, in step S104, it is determined whether or not the data input / output signal 15 (D) monitored by GPIO (1) is '0' (that is, a signal indicating that the power reset cycle has been released).

  Since data is normally pulled up by a resistor, at least all “1” can be read in GPIO (1) during the reset period. The CPU 11 issues a dummy cycle to the serial flash memory 12 to monitor the data (data input / output signal 15 (D)), recognizes that the power reset cycle has been released when “0” can be read, and in step S105 the CPU 11 Reboots.

  In the second embodiment, as in the first embodiment, even if the reset switch is pressed while the serial flash memory 12 is being accessed (the other reset signal 18 is input), the CPU 11 can be restarted normally. Thus, the CPU 11 is prevented from stopping without reading data normally from the serial flash memory 12. Further, the writing process is prevented from being interrupted.

  In the second embodiment, the power reset signal of the serial flash memory 12 is caused by the power control signal 27 output from the GPIO (3) of the CPU 11. However, in the third embodiment, the reset signal 16 ( When the first reset signal) is input (when a reset occurs due to power activation), the power reset cycle of the serial flash memory 12 is caused to occur.

  FIG. 4 shows a circuit configuration of the reset control device according to the third embodiment, and the same parts as those in FIG. 4 differs from FIG. 3 in that an OR circuit 28 that takes the logical sum of the power control signal 27 output from the GPIO (3) of the CPU 11 and the reset signal 16 is provided. The other parts are the same as those shown in FIG.

  The OR circuit 28 is “0” when the output of the power control signal 27 is “0” (low level), the output of the reset signal 16 is “0” (low level), or both are “0” (low level). (Low level) is output, otherwise, “1” (High level) is output.

  In the apparatus configured as described above, when the reset signal 18 is not input and the power supply control signal 27 is not output, the reset signal 16 (reset) is externally transmitted to the CPU 11 by, for example, a reset switch. When the signal '0' is input (when a reset due to power activation occurs), the CPU 11 proceeds to a reset process.

  At the same time, since the output of the OR circuit 28 becomes ‘0’ (low level), the transistor 31 is turned off and the serial flash memory 12 starts a power reset cycle. Since this power reset cycle is a forced reset to turn off the power, the inside of the serial flash memory 12 chip is completely initialized.

  As described above, the reset of the CPU 11 and the serial flash memory 12 can be synchronized when the reset due to the power activation occurs. When the reset signal 16 is released, both the CPU 11 and the serial flash memory 12 are restarted, so that the system is restarted.

  Note that when a reset occurs due to power-on as described above, a data input / output signal (D) that is input to GPIO (1) to confirm whether or not the serial flash memory 12 has returned from the reset mode. Is not used (the determination process of step S104 in FIG. 2 is not performed).

  Further, when the reset signal 16 is not input and the other reset signal 18 (reset signal “0”) is input from the outside to the CPU 11 by a reset switch or the like, the steps S101, S102, described in the second embodiment, The process of S203 is performed, and the power reset cycle of the serial flash memory 12 is caused by the power control signal 27. Thereafter, the processes similar to steps S104 and S105 described in the second embodiment are performed.

  As described above, the power reset cycle of the serial flash memory 12 is in any state when the other reset signal 18 is input to the CPU 11 or when a reset due to power activation occurs (the reset signal 16 is input). Can be caused.

  According to the third embodiment, even if the reset switch is pressed while the serial flash memory 12 is being accessed (even if the reset signal 16 or other reset signal 18 is input), the CPU 11 can be restarted normally. It is possible to prevent the CPU 11 from stopping from reading data from the serial flash memory 12 without being normally read. Further, the writing process is prevented from being interrupted.

  In addition, when a reset due to power activation occurs (when the reset signal 16 is input), the CPU 11 and the serial flash memory 12 can perform the reset process in synchronization.

11 ... CPU
11a ... Dedicated I / F
12 ... Serial flash memory 13 ... Select signal (SEL)
14 ... Clock signal (CLK)
15: Data input / output signal (D)
16 ... Reset signal (first reset signal)
17 ... Reset signal (R) (third reset signal)
18 .. Other reset signal (second reset signal)
27: Power control signal 28 ... OR circuit 30 ... Power supply 31 ... Transistor

Claims (4)

A serial flash memory reset control device that has an extended address register and is read and written by a CPU,
In the CPU, a first input / output port to which a data signal transmitted / received between the CPU and the serial flash memory is input, a first reset signal for power activation, and the first reset signal are separated. A second input / output port to which a second reset signal for the CPU is input;
The CPU
When the second reset signal is input to the second input / output port during the period in which the CPU is accessing the serial flash memory, the serial flash memory A function of outputting a third reset signal to the serial flash memory;
Monitor and recognize whether the data signal transmitted from the serial flash memory to the first input / output port of the CPU is a signal indicating the reset mode state of the serial flash memory or a signal indicating that the reset mode is released Monitoring function to
A function of performing a restart process when the monitoring function recognizes the release of the reset mode,
The serial flash memory is set to a reset mode by the input of the third reset signal, and has a function of using a transmission data signal from the serial flash memory to the first input / output port of the CPU as a signal indicating a reset mode state. A serial flash memory reset control device.   2. The serial flash memory reset control device according to claim 1, wherein the monitoring function of the CPU is implemented by issuing a dummy cycle from the CPU to the serial flash memory.   3. The serial flash memory reset according to claim 1, wherein the third reset signal is a power control signal that causes a power reset cycle by turning the power of the serial flash memory off and then on again. 4. Control device.   4. The serial flash memory according to claim 3, wherein a power reset cycle of the serial flash memory is caused to occur by at least one of the power control signal and the first reset signal. 5. Reset control device.

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