JP2015055983A - Semiconductor device initial setting circuit, semiconductor device initial setting method, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable initial setting appropriate for a system to be made without an access to a CPU and an initialization program with fewer terminals in a semiconductor device to which an identical OTP setting is made.SOLUTION: A terminal control unit 13 determines a terminal state from up to three level states and outputs a determined terminal state. An initial setting control unit 15 includes OTP memories 41 to 43 storing a plurality of initial voltage setting patterns, and selects one initial voltage setting pattern from the initial voltage setting patterns stored in storage means.

Description

  The present invention relates to an initial setting circuit and method for a semiconductor device such as a power supply device and a power management device, and a semiconductor device.

  Various settings of the semiconductor device need to be changed depending on the intended use, system type, and situation. For example, in the case of a power management device, there are voltage setting and sequence setting of the mounted linear regulator and switching regulator. For this reason, a register for writing data from a CPU (Central Processing Unit) outside the semiconductor device is provided, and the register data is changed and operated as necessary.

  However, in the case of a system that does not include a CPU or a semiconductor device that needs to operate before the CPU becomes operable, it is necessary to perform a desired operation by initial setting of the registers. In order to prevent unintentional operation when the power is turned on, it is known that an initial setting is stored in advance in the built-in ROM, and an initialization program is started when the semiconductor device is started and the initial setting is stored in a register ( For example, see Patent Document 1). The built-in ROM is hereinafter referred to as “OTP (One Time Programmable) memory”. The setting in the OTP memory is referred to as “OTP setting”.

  However, in such an initial setting method, the initial setting is stored in advance in the OTP memory, so that one initial setting is determined for one semiconductor device, and the OTP setting changes every time the usage or system changes. The semiconductor device must be manufactured, and the old OTP setting semiconductor device remains in stock. Therefore, it is considered that the initial operation is switched by a terminal. However, the conventional initial setting method has a problem that a large number of terminals are required to select more initial values.

  For example, Patent Document 2 discloses a multiprocessor system in which an activation CPU, a master CPU, and an address of a memory to be read are selected by a terminal for the purpose of flexibly responding to required use. However, although it is possible to flexibly cope with the required specifications and the system operation can be switched with terminals, the problem of enabling more initial settings with a smaller number of terminals has not been solved.

  The object of the present invention is to solve the above problems, and in a semiconductor device having the same OTP setting, an initial setting of a semiconductor device capable of performing an initial setting adapted to the system with a smaller number of terminals and without CPU access or an initialization program. It is to provide a setting circuit.

An initial setting circuit of a semiconductor device according to the present invention includes:
Terminal determination means for determining the terminal state up to three values and outputting the determined terminal state;
Storage means for storing a plurality of initial voltage setting patterns;
Initial setting means for selecting one initial voltage setting pattern from the initial voltage setting patterns stored in the storage means, using the terminal state determined by the terminal determination means;
It is provided with.

  According to the initial setting circuit of the semiconductor device according to the present invention, it is possible to perform the initial setting according to the system with a smaller number of terminals and without CPU access or initialization program in the same OTP setting semiconductor device. As a result, it is possible to avoid making an unnecessary inventory of semiconductor devices.

1 is a block diagram showing a configuration of a semiconductor system including a CPU 1, a semiconductor device 2, and semiconductor devices 3-1, 3-2 and 3-3 according to Embodiment 1 of the present invention. 3 is a block diagram illustrating configurations of a terminal control unit 13 and an initial setting control unit 15 according to the first embodiment. FIG. It is a flowchart which shows the ternary determination process performed by the ternary determination part 14 of the terminal control part 13 of FIG. FIG. 6 is a block diagram illustrating configurations of a terminal control unit 13A and an initial setting control unit 15 according to the second embodiment. It is a flowchart which shows the ternary determination process performed by 14 A of ternary determination parts of 13 A of terminal control parts of FIG.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component. In this embodiment, a power management semiconductor device that supplies power of a necessary voltage to an electronic device is taken as an example.

Embodiment 1. FIG.
FIG. 1 is a block diagram showing a configuration of a semiconductor system including a CPU 1, a semiconductor device 2, and semiconductor devices 3-1, 3-2 and 3-3 according to Embodiment 1 of the present invention. FIG. 2 is a block diagram illustrating configurations of the terminal control unit 13 and the initial setting control unit 15 according to the first embodiment. Here, the terminal control unit 13 and the initial setting control unit 15 constitute an initial setting circuit of the semiconductor device 2. The semiconductor system according to this embodiment includes a CPU 1, a semiconductor device 2, and semiconductor devices 3-1, 3-2, and 3-3, and the semiconductor device 2 is compared with a known semiconductor system. The apparatus further includes a start trigger detection unit 12 and a terminal control unit 13. FIG. 2 shows a flow of initial value setting with only one terminal T1 for simplification.

  In FIG. 1, the semiconductor device 2 includes a serial interface 11, a start trigger detection unit 12, a terminal control unit 13 having a ternary determination unit 14, an initial setting control unit 15, linear regulators 21 and 22, and a switching regulator. 23. Here, the semiconductor device 2 is a power management semiconductor device, and the serial interface 11 communicates with the CPU 1 via a serial bus. The semiconductor devices 3-1, 3-2 and 3-3 are respectively supplied with power from regulators 21, 22 and 23 which perform voltage control for power supply via power supply lines P 1 to P 3. Further, as shown in FIG. 2, the initial setting control unit 15 includes OTP memories 41, 42, and 43 that hold voltage initial setting values of the regulators 21, 22, and 23. The initial setting control unit 15 further includes a pattern selection unit 44 that selects one voltage setting pattern from the three voltage setting patterns A, B, and C from the OTP memories 41 to 43 and outputs the selected voltage setting pattern to the regulators 21 to 23. . The initial setting control unit 15 further includes an OTP control unit 40 that stores voltage initial settings in the OTP memories 41 to 43 based on an initial voltage setting write signal from an external circuit. The semiconductor device 2 does not include the serial interface 111 and may not communicate with the CPU 1.

  In the semiconductor device 2 of FIG. 1, supply voltages to the semiconductor devices 3-1, 3-2 and 3-3 are set from the CPU 1 through the serial interface 11 to the linear regulators 21 and 22 and the switching regulator 23 after the CPU 1 is activated. Passed to. As for the initial voltage setting before starting up the CPU 1, the values already set in the OTP memories 41, 42 and 43 are transferred to the linear regulators 21 and 22 and the switching regulator 23, respectively.

  In FIG. 1, the activation trigger detection unit 12 detects the activation trigger signal at the terminal T <b> 1 and outputs the detection signal to the terminal control unit 13. The terminal control unit 13 is connected to the terminal T1 and includes a circuit that performs signal control of the terminal T1 and ternary determination (high level, low level, and high impedance) at the terminal T1. The initial setting control unit 15 determines the initial setting based on the output signal from the terminal control unit 13. Therefore, according to the state of the terminal T1 determined by the terminal control unit 13, one pattern is selected from a plurality of initial voltage patterns in the initial setting control unit 15, and the selected one initial voltage pattern is the linear regulators 21, 22 and the switching. Passed to the regulator 23.

  In FIG. 2, the terminal control unit 13 includes a PU control unit 31 including a pull-up resistor and a switch for determining whether to pull up, and a PD control unit 32 including a pull-down resistor and a switch for determining whether to pull down. Prepare. Further, the terminal control unit 13 determines whether the input signal from the terminal T1 is high level, low level, or high impedance, and the input signal from the terminal T1 to the ternary determination unit 14. And an input control unit 33 for controlling whether or not to pass. The initial setting control unit 15 includes an OTP memory 41 in which a voltage setting pattern A is stored, an OTP memory 42 in which a voltage setting pattern B is stored, an OTP memory 43 in which a voltage setting pattern C is stored, and OTP memories 41 to 41. 43 includes an OTP control unit 40 that stores initial voltage settings from an external circuit. The initial setting control unit 15 further includes a pattern selection unit 44 that selects one voltage setting pattern from the OTP memories 41 to 43 based on an output signal from the ternary determination unit 14. Here, one voltage setting pattern selected by the pattern selection unit 44 is transferred to the regulators 21, 22, and 23 as initial settings.

  FIG. 3 is a flowchart showing a ternary determination process executed by the ternary determination unit 14 of the terminal control unit 13 of FIG.

  In FIG. 3, when a ternary determination start trigger such as power-on or start signal is detected, the terminal state when the pull-up of the terminal T1 and the input to the ternary determination unit 14 are validated is PU (pull-up). The determination result is held (S1). Here, as a PU determination result, “PU determination = 1” is set when the voltage at the terminal T1 is pulled up, and “PU determination = 0” is set when the voltage is not pulled up. Next, the terminal T1 pull-up is disabled, and the state of the terminal T1 when the pull-down and the input to the ternary determination unit 14 are enabled is held as a PD (pull-down) determination result (S2). Here, as a PD determination result, “PD determination = 1” is set when the voltage of the terminal T1 is pulled down, and “PD determination = 0” is set when the voltage is not pulled down. Further, the pull-up and pull-down of the terminal T1 and the input to the ternary determination unit 14 are invalidated (S3).

  Next, based on the PU determination result and PD determination result held in steps S1 and S2, the state of the terminal T1 is determined as follows. First, it is determined whether or not PU determination = 0 and PD determination = 1 (S4). If “YES” in the step S4, a ternary determination signal indicating that the terminal T1 is at a low level is output (S5), and the ternary determination process is ended. On the other hand, if NO in step S4, it is determined whether PU determination = 1 and PD determination = 0 (S6). If “YES” in the step S6, a ternary determination signal indicating that the terminal T1 is at a high level is output (S7), and the ternary determination process is ended. On the other hand, if NO in step S6, it is determined whether PU determination = 1 and PD determination = 1 (S8). If “YES” in the step S8, a ternary determination signal indicating that the terminal T1 is high impedance is output (S9), and the ternary determination process is ended. On the other hand, if “NO” in the step S8, the process returns to the step S1, and the ternary determination process is repeatedly performed again from the PU determination.

In the embodiment configured as described above, FIG. 3 shows a control flow for setting an initial value using only one terminal T1 for simplification. However, if the number of terminals for initial setting increases, a candidate initial voltage can be obtained. The number of setting patterns also increases. Since three types of initial voltage setting patterns can be assigned to each terminal, if the number of terminals is N, an initial setting suitable for the intended use and system can be selected from among ^3N types of initial voltage setting patterns. . For example, when three terminals are used as initial setting terminals, only 2 ³ = 8 kinds of initial voltage setting patterns can be selected in the prior art, but according to the present embodiment, 3 ³ = 27 kinds of initial voltage setting patterns using the same three terminals. The setting can be selected.

In Patent Document 2, since there are 64 combinations of address designations, 6 terminals are used. However, according to the present embodiment, the same 64 patterns can be realized with 4 terminals, and the reduction of 2 terminals as address designation terminals can be achieved. It becomes possible. That is, in the present embodiment, three types of initial voltage setting patterns can be assigned to one terminal, and if the number of terminals is N, the initial setting suitable for the intended use and system can be selected from the ^3N types of initial voltage setting patterns. The feature is that can be selected.

Embodiment 2. FIG.
FIG. 4 is a block diagram illustrating configurations of the terminal control unit 13A and the initial setting control unit 15 according to the second embodiment. The second embodiment of FIG. 4 differs from the first embodiment of FIG. 2 in the following points.
(1) Although the terminal control unit 13 in FIG. 2 includes a ternary determination unit 14, instead of this, in FIG. 4. A terminal control unit 13A is provided. The terminal control unit 13A includes a ternary determination unit 14A that outputs a terminal determination completion signal. Other configurations are the same as those in FIG.

  According to the ternary determination unit 14A that also outputs a terminal determination completion signal according to the second embodiment configured as described above, the terminal determination completion signal is detected in the semiconductor device 2 or to an external circuit of the semiconductor device 2. Output. Thereby, after the terminal determination is completed, the terminal T1 can be used with another function, and there is no need to provide an initial setting dedicated terminal. Further, if the functions of all terminals are used for initial setting only when initial setting of the semiconductor device 2 is performed, and the initial setting is completed, the function of each terminal is changed to the original function, thereby increasing the number of initial voltage setting patterns.

  FIG. 5 is a flowchart showing a ternary determination process executed by the ternary determination unit 14A of the terminal control unit 13A of FIG. The ternary determination process of FIG. 5 is characterized by outputting a terminal determination completion signal in step S10 after the processes of steps S5, S7, and S9, compared to the ternary determination process of FIG. Other configurations are the same as those in FIG.

According to the first and second embodiments configured as described above, three types of initial voltage setting patterns can be assigned to one terminal. If the number of terminals is N, 3 ^N types of initial voltage setting patterns can be selected. It is possible to select an initial setting suitable for the intended use and system. Thereby, even in the semiconductor device 2 having the same OTP setting, the initial setting according to the system can be performed from a larger number of initial voltage setting patterns with a smaller number of terminals, and the versatility of the semiconductor device 2 can be improved. In particular, since it is not necessary to manufacture the semiconductor device 2 having different OTP settings for each usage or system, useless inventory is eliminated.

1 ... CPU,
2 ... Semiconductor device,
3-1, 3-2, 3-3 ... semiconductor device,
11 ... Serial interface,
12 ... Activation trigger detection unit,
13, 13A ... terminal control unit,
14, 14A... Ternary determination unit,
15 ... Initial setting control unit,
21, 22 ... Linear regulator,
23 ... Switching regulator,
31 ... PU control unit 32 ... PD control unit,
33 ... Input control unit,
40. OTP control unit,
41, 42, 43 ... OTP memory,
44 ... pattern selection unit,
T1 terminal.

JP-A-2-005115 JP 2012-137946 A

Claims (7)

Terminal determination means for determining the terminal state up to three values and outputting the determined terminal state;
Storage means for storing a plurality of initial voltage setting patterns;
Initial setting means for selecting one initial voltage setting pattern from the initial voltage setting patterns stored in the storage means, using the terminal state determined by the terminal determination means;
An initial setting circuit for a semiconductor device, comprising:   2. The initial setting circuit for a semiconductor device according to claim 1, further comprising signal output means for outputting a terminal determination completion signal when a terminal state is output by said terminal determination means.   3. The semiconductor device initial setting circuit according to claim 1, wherein the three values include a high level, a low level, and a high impedance. An initial setting method for a semiconductor device comprising a storage means for storing a plurality of initial voltage setting patterns,
Determining the terminal state up to three values, and outputting the determined terminal state;
Selecting one initial voltage setting pattern from the initial voltage setting patterns stored in the storage means using the determined terminal state;
An initial setting method for a semiconductor device, comprising:   5. The semiconductor device initial setting method according to claim 4, further comprising a step of outputting a terminal determination completion signal when the terminal state is output.   6. The semiconductor device initial setting method according to claim 4, wherein the three values include a high level, a low level, and a high impedance.   A semiconductor device comprising the initial setting circuit of the semiconductor device according to claim 1.

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