JP2008242815A - Test circuit for random number generation circuit, and test method for random number generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test circuit and test method for a random number generation circuit, capable of easily setting an operation time for generating random numbers which never cause collision to the random number generation circuit. <P>SOLUTION: A random number generation circuit 2 which shows a transitional response up to generation of random numbers is activated from an initial state by applying a random number generation activation signal 10 just after a reset signal 9 thereto to start random number generating operation, and fetches output data to a buffer memory 6 at a time after an end signal 15 set by an operation time setting signal 13. Two pieces of output data 16 fetched for a predetermined frequency are compared by a comparison circuit 7, and when even one matching set is present, the same operation is repeated by extending the operation time, whereby an operation time capable of generating sufficiently random numbers without collision is calculated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a test circuit for a random number generation circuit and a test method for a random number generation circuit used for evaluating whether or not output data output from a random number generation circuit is a random number.

For example, for protection of information on the network, true random numbers or pseudo-random numbers close to equivalent are becoming indispensable, and their characteristics are completely irregular, equal probabilities, irrelevant before and after, and no periodicity. Have Note that the true random number generally indicates that generated by using a physical phenomenon, but in the present specification, it is used to include a pseudo-random number close to the equivalent.
For example, there are a random number generation circuit mounted on a SoC (system on a chip) device that inputs Seed as seed information after reset release and another that generates it by itself without inputting it.
In the former case, if the same Seed is inserted, the random number output after reset release is always the same, so a value is stored in a flash memory or the like, and a different value Seed is read and used each time reset is released.
In the latter case, there is no need to input Seed, but a stirring circuit (a circuit that is a source of randomness) is used. Because of this stirring circuit, there may be a case where an operation time as a certain period of time is required after releasing the reset until a highly random output is output.

In the case of using the latter agitation circuit, if the setting of the operation time of the random number generation circuit is short in starting the random number generation circuit after reset release, the random number output several times after the reset release becomes exactly the same value. This phenomenon is called collision.
Since the setting of the operation time of the random number generation circuit that does not cause a collision of random number output is affected by the environment such as noise (layout conditions, register access frequency of the program), actual machine evaluation is performed for each SoC device equipped with the random number generation circuit. I have decided.
Normally, measurement is performed about 1000 times per sample in consideration of a predetermined order of collision probability. In addition, considering individual differences, it is necessary to measure several samples.
The operator or user needs a lot of time to perform the actual machine evaluation of the above 1000 times x several samples while changing the setting of the operation time of the random number generation circuit, and to set or obtain the operation time that does not cause a collision. And consumes many resources.

On the other hand, Patent Document 1 discloses an apparatus that continuously generates random numbers, counts the same appearing values, and determines that the generated random numbers are not random when the counted values are larger than a certain threshold value. Has been.
Further, Patent Document 2 discloses a device formed in a chip, similar to Patent Document 1. In this patent document 2, a random number of bits is generated based on a signal generated from a random number generating element in a semiconductor chip incorporating the random number generating element, and a certain amount of sample data is acquired within a predetermined time. An apparatus is disclosed in which a random number generation frequency of each numerical value is examined and a product exceeding a threshold value is determined as a defective product.
Thus, Patent Document 1 and Patent Document 2 do not disclose means and a method for easily setting an operation time for generating a random number that does not cause a collision in the random number generation circuit described above.
WO 2004/081786 JP 2003-196081 A

  The present invention has been made in view of the above points, and a random number generation circuit test circuit capable of easily setting an operation time for generating a random number that does not cause a collision to the random number generation circuit, and a random number generation An object is to provide a test method for a circuit.

  A test circuit for a random number generation circuit according to an embodiment of the present invention applies a start signal for generating a random number from an initial state a plurality of times at a predetermined time interval to a random number generation circuit having a transient random number generation characteristic. The start signal applying means, and each output data output from the random number generation circuit after the operation time set shorter than the time interval are compared with each other with the time when each start signal is applied as a reference time, and they match. Determining means for determining whether there is output data to be output.

  A test method for a random number generation circuit according to an embodiment of the present invention provides a random number generation circuit having a transient random number generation characteristic with a start signal for generating a random number from an initial state a plurality of times at predetermined time intervals. The start signal applying step to be applied and the output data output from the random number generation circuit after the operation time set shorter than the time interval are compared with each other with the time when each start signal is applied as a reference time. And a determination step for determining whether or not matching output data exists.

  According to the present invention, it is possible to easily set an operation time for generating a random number that does not cause a collision to the random number generation circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 shows the configuration of a test circuit for random number generation circuit (hereinafter abbreviated as a test circuit) 1 according to a first embodiment of the present invention. The test circuit 1 is used in connection with a random number generation circuit 2 that generates random numbers. The random number generation circuit 2 has a transient random number generation characteristic. That is, the random number generation circuit 2 has a built-in stirring circuit 3 that requires a certain time (hereinafter referred to as operation time) required to generate a sufficiently random pseudo-random number (hereinafter simply referred to as a random number) from the initial state. is doing.
The test circuit 1 is incorporated in the SoC product 4 together with the random number generation circuit 2 until the random number generation circuit 2 generates a random number that can be regarded as a true random number during the initial evaluation or mass production test of the SoC product 4. The recommended value for the above operation time, that is, a recommended value is output.

The test circuit 1 includes a timing generation circuit 5 that generates various timing signals. The test circuit 1 also includes a buffer memory 6 as a memory circuit that temporarily stores (stores) output data output from the random number generation circuit 2 to which a timing signal is applied (which becomes a random number after the operation time), The comparator circuit 7 compares the two output data from the buffer memory 6 with each other.
The buffer memory 6 and the comparison circuit 7 form determination means for determining whether or not the random number generation circuit 2 generates a sufficiently random random number.
The timing generation circuit 5 includes a CPU 8 that controls generation of various timing signals in synchronization with a clock by a clock oscillator (not shown). The reset signal 9 and the random number generation start signal 10 as various timing signals generated by the timing generation circuit 5 are applied to the random number generation circuit 2 a plurality of times at predetermined time intervals.

The random number generation circuit 2 is reset to an initial state when the reset signal 9 is applied, and the random number generation start signal 10 is applied immediately after the reset signal 9, so that the random number generation circuit 2 includes the internal stirring circuit 3. A control operation is started to start the stirring operation in software.
In this manner, the timing generation circuit 5 forms activation signal application means for applying an activation signal for generating random numbers from an initial state to the random number generation circuit 2 having a transient random number generation characteristic at predetermined time intervals.
The stirring circuit 3 has a configuration shown in FIG. 2, for example. In FIG. 2, an example of the agitation circuit 3 for 1 bit is shown, but actually, a plurality of random numbers are generated by the plurality of agitation circuits 3.

The stirring circuit 3 includes a two-input OR circuit 11 and a three-input exclusive OR circuit (abbreviated as XOR circuit) 12 to which an output from the OR circuit 11 and two control data X1 and X2 are input. The output U of the XOR circuit 12 is input to an OR circuit 11 to which mode data Y is input. The three-input XOR circuit 12 examines the two-input XOR, and further performs an XOR operation between the output and the remaining one input.
The digital values (binary values) of the mode data Y and the control data X1 and X2 are controlled by a control means (not shown) in the random number generation circuit 2. The mode data Y is used for the stirring mode related to the stirring operation when Y = 0, and to other modes not related to the stirring operation when Y = 1. In the other mode of Y = 1, the output U = 1 when X1 = X2, and the output U = 0 when X1 ≠ X2.

In the stirring mode with Y = 0, the control data X1 and X2 are set to X1 = X2 when the stirring operation is prohibited. In this case, the output U of the stirring circuit 3 becomes a definite value of U = 0 or 1.
On the other hand, when the stirring operation is started, the control data X1 and X2 are set to X1 ≠ X2. In this case, the stirring circuit 3 oscillates at a very high frequency.
This oscillation state at a very high frequency shows an unstable transient response characteristic with respect to the stirring function at the time of starting, but becomes a stable stirring operation state after an appropriate time from the starting time, that is, after the operating time has elapsed. In this stable stirring operation state, the output U changes randomly due to noise or the like. The output U of the agitation circuit 3 is used as output data for random number generation for one bit of the random number generation circuit 2.

In the present embodiment, the agitation circuit 3 is activated by the random number generation activation signal 10, and it is evaluated whether or not it is a random number at a timing after the operation time from the random number generation activation time (random number generation end signal 15 described later). The output data is taken in, and the random number generation operation is stopped (terminated).
The reset signal 9 and the random number generation start signal 10 are repeatedly generated under the control of the CPU 8, for example, as shown in FIG.
As described above, the reset signal 9 sets the random number generation circuit 2 to an initial state, and the stirring operation of the stirring circuit 3 starts when the random number generation start signal 10 is applied. The timing generation circuit 5 may apply the reset signal 9 and the random number generation start signal 10 immediately after the reset signal 9 to the random number generation circuit 2 as a set of signals.

As shown in FIG. 3, the CPU 8 outputs a random number generation circuit operation time setting signal (hereinafter simply abbreviated as an operation time setting signal) 13 for setting a random number generation operation time of the random number generation circuit 2 to the random number generation circuit 2. To do.
As shown in FIG. 3, the random number generation circuit 2 includes a random number generation end signal (hereinafter referred to as a random number generation end signal) that terminates the random number generation operation after the operation time set by the operation time setting signal 13 after the random number generation start signal 10 becomes active. , Simply abbreviated as end signal) 15.
In FIG. 3, the random number generation start signal 10 becomes active from L to H, and the time interval from this timing until the end signal 15 changes from L to H is set as the operation time. It is not what is done.
This end signal 15 is output to the buffer memory 6 together with the output data 16 output from the random number generation circuit 2.

The buffer memory 6 outputs the output data 16 output from the random number generation circuit 2 at the timing when the end signal 15 becomes active (for example, the timing of the falling edge of the pulse of the end signal 15 shown in FIG. 3). 16 is fetched and temporarily stored in the buffer memory 6.
The operation of the stirring circuit 3 is stopped by the end signal 15. Immediately after the output data 16 is temporarily stored in the buffer memory 6 at the timing of the end signal 15, the next reset signal 9 is output from the timing generation circuit 5. Then, the same operation is repeated.
That is, when the random number generation start signal 10 is applied between the reset signal 9 and the next reset signal in FIG. 3, the random number generation circuit 2 starts from the initial state, and after the same operation time has elapsed, The operation of sequentially storing the output data 16 output from the random number generation circuit 2 in the buffer memory 6 is repeated. However, when matching output data 16 is obtained as described later, the operation time is changed to be longer.

When the buffer memory 6 stores a plurality of output data 16 in the buffer memory 6, the buffer memory 6 outputs two of the output data 16 to the comparison circuit 7. Each output data is data composed of a plurality of bits of a predetermined number of bits or more.
For example, when the two output data output from the buffer memory 6 are 6a and 6b, the comparison circuit 7 compares the two output data 6a and 6b in units of bits, and determines whether or not they completely match. The determination signal 17 of the determination result is output.
The comparison circuit 7 compares the output data 16 with all combinations. For example, when the number of times of measurement M = 1000, 1000 × 999 comparisons are performed.
The determination signal 17 of the comparison circuit 7 is output to, for example, the timing generation circuit 5 (the CPU 8). The CPU 8 increases the value of the operation time setting signal 13 (that is, the operation time) and outputs it to the random number generation circuit 2 when the determination signal 17 in the case of coincidence is input even once.

Then, the random number generation circuit 2 performs an operation of outputting the output data 16 from the beginning by the extended operation time setting signal 13.
On the other hand, when it is determined that the comparison results do not match in all combinations, the operation time based on the operation time setting signal 13 in that case is output from the SoC product 4. The operation time can be used as a recommended value for random number generation.
When actually used by the user, the operation time of the recommended value can be used as the operation time setting signal 13 by software (more specifically, operation time register write processing), for example.

Moreover, when setting the initial value of the operation time by the operation time setting signal 13 for the first time, it can be performed by input from, for example, the keyboard 18 as the operation time setting input means. In addition, the user can also set or change the value of the number of times of measurement M from the keyboard 18.
FIG. 4 shows a flowchart of a test method for obtaining (evaluating) a recommended value of the operation time of random number generation by the test circuit 1 according to the present embodiment. The operation of this embodiment will be described below with reference to FIG.

When the power of the SoC product 4 in FIG. 1 is turned on, the CPU 8 of the timing generation circuit 5 sets the number of times of measurement M (for example, M = 1000 here) to obtain the output data 16, and for the number of times of measurement. The parameter i is set to an initial value i = 1. For example, the number of times of measurement M is initially set by the user, and thereafter, the value is used as a default value. In the next step S2, the CPU 8 outputs, for example, a pulsed reset signal 9 that changes from H to L to the random number generation circuit 2 as shown in FIG. 3 to activate the reset function. The random number generation circuit 2 is reset to an initial state by the pulse-like reset signal 9.
In the next step S3, the CPU 8 outputs, for example, a pulse-like random number generation start signal 10 immediately after the reset signal 9 to the random number generation circuit 2 as shown in FIG. For example, when the random number generation activation signal 10 changes from L to H, the random number generation circuit 2 becomes active in the random number generation function.

Then, as shown in step S4, the random number generation circuit 2 starts the random number generation operation and starts the random number generation operation. Then, the random number generation circuit 2 starts to output the generated output data 16 to the buffer memory 6. The CPU 8 also outputs an operation time setting signal 13 to the random number generation circuit 2.
In the next step S5, the buffer memory 6 waits for the end signal 15 to be input (or activated) from the random number generation circuit 2.
In other words, the random number generation circuit 2 generates the end signal 15 after the operation time according to the operation time setting signal 13 and continues the operation of random number generation until the end signal 15 is generated. When the end signal 15 becomes active, the value of the random number is fixed at that timing, and the operation of random number generation is stopped (terminated).

Then, when the end signal 15 becomes active from the random number generation circuit 2 as shown in step S6, the buffer memory 6 chips the memory cell of the buffer memory 6 at the rising edge of the pulse of the end signal 15 as shown in FIG. Apply an enable signal.
The output data 16 is stored in the memory cell of the buffer memory 6 at the timing of the end signal 15.
Then, as shown in FIG. 3, the next reset signal 9 is output to the random number generation circuit 2 immediately thereafter (however, since the operation time can be variably set, immediately after including the variable width margin). The same operation as described above is repeated.
A plurality of output data 16 are stored in the buffer memory 6. Then, a set of two output data 6a and 6b is input from the buffer memory 6 to the comparison circuit 7 as shown in step S7 of FIG. Note that the process of transition from step S6 to S7 in FIG. 4 is simplified (at least when a plurality of output data 16 is obtained, the process proceeds from step S6 to S7).

As shown in step S8, the comparison circuit 7 determines whether or not the pair of the two output data 6a and 6b input from the buffer memory 6 matches. The determination signal 17 of the determination result is output to the timing generation circuit 5.
If they match, the CPU 8 of the timing generation circuit 5 increases the operation time value of the operation time setting signal 13 as shown in step S9, and returns to step S1. Accordingly, in this case, the same operation is repeatedly performed from step S1 by the operation time setting signal 13 set to a value longer (larger) than the operation time initially set.
On the other hand, if they do not match in step S8, the process proceeds to step S10. In step S10, the CPU 8 determines whether the parameter i for the number of measurements is less than M. If it is less than M, the parameter i is increased by one as shown in step S11, and the process returns to step S2.

Note that steps S7 and S8 in FIG. 4 show simple operation contents. As described above, the comparison circuit 7 determines whether or not all combinations of the two output data 6a and 6b in the output data 16 stored in the buffer memory 6 match.
If it is determined that all combinations do not match, the process proceeds to step S12 via i = M in step S10. Then, the operation time setting signal 13 in this case is output from the timing generation circuit 5, and the evaluation or test for setting the recommended value of the operation time by the operation time setting signal 13 is completed.
As described above, the present embodiment automatically satisfies the condition that the output data output from the random number generation circuit 2 is not the same output data for the predetermined number of times of measurement M, that is, no collision occurs. Automatically calculates the recommended operating time that can generate random numbers.
That is, in this embodiment, the recommended value of the operation time as described above is automatically calculated, and the operation time of the recommended value is set.

For this reason, it is possible to greatly reduce the operation time calculation and setting work that has been troublesome in the conventional example by the user.
In the configuration of FIG. 1, the determination signal 17 is input to the timing generation circuit 5, and the operation time change control is performed based on the determination result of the determination signal 17. On the other hand, even in a case where the determination signal 17 is not input to the timing generation circuit 5 and the determination signal 17 is obtained by the comparison circuit 7 with respect to the case of the predetermined number M, it is easier than the conventional example. There is an advantage that the recommended value of the operating time can be obtained and evaluated.

(Second Embodiment)
Next, a test circuit according to a second embodiment of the present invention will be described. This test circuit has the same configuration as the test circuit 1 shown in FIG. However, the operation of the timing generation circuit 5 by the CPU 8 is slightly different from that of the first embodiment.
In the first embodiment, for example, when an operation time longer than an appropriate operation time is set for the random number generation circuit 2 as the operation time setting signal 13 first, the operation time is final. The operation time is set or obtained.
On the other hand, this embodiment includes means or a method for calculating or setting a boundary value closer to a more appropriate operation time as a recommended value by performing the process of changing the operation time at least once.

Then, the CPU 8 calculates a boundary value closer to a more appropriate value as the operation time by performing the process of changing the operation time at least once.
FIG. 5 is a flowchart showing a part of the outline of the operation according to the present embodiment. FIG. 5 is similar to FIG. 4 and omits the same processing parts as FIG.
The present embodiment is a configuration or method in which step S21 is performed between steps S10 and S12 in FIG. In this step S21, the CPU 8 determines (from step S1) whether or not the operation time setting signal 13 has been changed to be set longer before reaching this step S21. Specifically, in the process of FIG. 4, it is determined whether or not the operation time setting signal 13 in step S9 has been changed to be set longer.
If this change has been made, the process proceeds to step S12, and the operation time setting signal 13 finally changed by the change is set as the operation time of the boundary value.

Therefore, in the determination in step S21, there is a change that sets the operation time setting signal 13 to be long. Specifically, in the processing of FIG. 4, there is a change that sets the operation time setting signal 13 in step S9 to be long. In the case, the same operation time as in FIG. 4 is obtained.
If the operating time in this case is shorter than this value, a matching output data set appears, so that the operating time is a boundary value close to an appropriate operating time value.
On the other hand, if it is determined in step S21 that the setting for setting the operation time setting signal 13 to be longer has not been made, the CPU 8 sets the operation time setting signal 13 to be shorter as shown in step S22. The change is made and the process returns to step S1 in FIG. Then, the processing shown in FIG. 4 is performed except for the changed portion of FIG. 5 from step S1.

In this case, as shown in FIG. 5, the operation time setting signal 13 is changed to be sequentially shortened until a matching set appears in step S8.
In this way, it is determined whether or not there is a matching set in step S8. If there is a matching set, the CPU 8 immediately before the matching set exists as shown in step S23. The set operation time setting signal 13 is stored in a register or the like of the CPU 8 as the operation time of the boundary value. Then, after the stored processing, the process proceeds to step S12, and the operation time setting signal 13 in that case is output. If this operation time is also shorter than this value, there is a matching set, and therefore the boundary value is close to the appropriate operation time value.
If it is determined in step S21 that no change has been made to set the operating time setting signal 13 longer, the process returns to step S1 through step S22 as shown in FIG. 5, and further matches in step S8. The process of FIG. 5 is repeated until there is a set of output data to be processed. Then, the operation time before the coincident output data set exists is obtained as the boundary value.

Thus, when the boundary value of the operation time obtained by this embodiment is shorter than this boundary value, a collision occurs.
For this reason, according to the present embodiment, the same effect as that of the first embodiment can be obtained, and an operation time closer to a more appropriate value, in other words, a more accurate operation time can be obtained. In addition, the power consumption can be further reduced and random number generation can be performed.
Moreover, even if the user sets the initial value of the random number generation operation time to an arbitrary value by software or the like, a boundary value close to an appropriate value can be automatically obtained as the operation time, and the operation time by the user is evaluated. Time and effort can be greatly reduced.

Note that if the boundary value of the operation time obtained in this case is used as it is, the power consumption can be reduced as compared with the operation time when the margin is included.
Further, the user may freely set a value for increasing or decreasing the operation time by the operation time setting signal 13 from the keyboard 18 as necessary.
Alternatively, initially, this value may be increased to calculate an approximate value of the boundary value, and then the operation time may be changed with a smaller value to obtain a more accurate boundary value.

(Third embodiment)
Next, a third embodiment of the present invention will be described. In the above-described embodiment, the number of bits of the output data 16 generated by the random number generation circuit 2− and the number of bits stored in the buffer memory 6 are not particularly clarified. .
The buffer memory 6 takes in all the numbers of bits in the output data 16 generated by the random number generation circuit 2-.
On the other hand, in the present embodiment, when the bit number n of the output data 16 of the random number generation circuit 2 is n> k (for example, k = 24), the number of bits stored in the buffer memory 6 or the comparison circuit 7 The number of bits to be compared can be made smaller than n bits. Alternatively, it is possible to cope with a case where the number of bits of the output data 16 output from the random number generation circuit 2 is reduced.

When the number of bits is large, in the state in which the random number generation circuit 2 generates a random number close to a true random number, the collision probability that the random number collides becomes small enough, for example, in the number of measurements of about 1000 times. Probability can be ignored (ie considered 0). On the other hand, when the number of bits is small or small, it is necessary to consider this collision probability.
Therefore, a method for calculating the random number collision probability by calculation will be described below.
When there are n bits of random data, the total number of different combinations of the data is 2 ⁿ . For this reason, when the appearance probabilities are uniform, the probability P that at least one identical data appears during m random number acquisitions is subtracted from the value 1 that the same data does not appear. So good
P = 1 − ((2 ⁿ⁻ 1) / 2 ⁿ ) × ((2 ⁿ −2/2 ⁿ ) × …… × ((2 ⁿ − (m−1)) / 2 ⁿ ) (1)
Is calculated.

For example, when calculating the probability that even if m = 1000 random numbers are acquired with 24 bits of random data with n = k (= 24), the probability that the same data appears will be 2.9334%.
In this case, although the random number generation circuit 2 outputs a random number equivalent to an n-bit true random number, the probability that the extracted 24 bits match and an NG determination signal 17 is output is 2.9334. % (Large collision probability).
For this reason, for example, two sets of data with the above conditions are obtained, and the probability that the same data continuously appears for the two sets is a square of 0.029334, which is a sufficiently low probability. That is, even when the number of bits is small, the determination result when determining whether or not there is a pair that matches once in the case of a large number of bits by determining whether or not they match twice continuously. And substantially the same result can be obtained.

Therefore, for example, in the timing diagram of FIG. 3 used in the first embodiment, the output data 16 from the random number generation circuit 2 (with its output as a different random number) around the operation time set by the operation time setting signal 13. ) Change to capture twice. In this case, the number of bits of the output data 16 to be captured is 24 bits, for example.
Specifically, the end signal 15 is output, for example, one clock after the operation time in the first embodiment, in which further random number generation becomes possible, and the timing of the operation time and after the next one clock. Thus, the two output data are stored in the buffer memory 6.
Then, each output data obtained at the timing of the operation time is compared by the comparison circuit 7 in the same manner as in the first embodiment, and the same comparison is also performed for the output data fetched after the next one clock. The comparison circuit 7 is configured to output a determination signal 17 as to whether or not both sets match.

When the comparison circuit 7 outputs the coincidence determination signal 17, the operation time is lengthened. On the other hand, an operation time during which no coincident determination signal 17 is output is obtained as a recommended value. When the coincidence determination signal 17 is not output, the operation time may be further shortened to obtain the boundary value of the operation time as in the second embodiment.
Therefore, according to the present embodiment, the memory capacity of the buffer memory 6 can be reduced, and the burden of comparison processing by the comparison circuit 7 can be reduced. In addition, the number of bits for random number generation by the random number generation circuit 2 can be reduced. Therefore, the circuit scale of the test circuit 1 and the random number generation circuit 2 shown in FIG. 1 can be reduced and the cost can be reduced.
Further, when the random number generation circuit 2 generates a random number with a bit number smaller than 24 bits, for example, three sets of output data are taken so as to substantially satisfy the required collision probability, and three consecutive times It can be changed so that a determination signal is generated when they coincide. As described above, this embodiment can reduce the number of bits to be compared according to the required collision probability.

Further, for example, when the random number generation circuit 2 generates output data having a sufficiently large number of bits, for example, eight times (192 bits) of 24 bits, a collision required in a state where a random number equivalent to a true random number is generated. When the probability Pr is known, for example, P <Pr (2) where n in the equation (1) is an unknown number of bits.
The smallest bit number n satisfying the above condition may be calculated. Then, the output data may be stored or compared with the number of bits.
In this case, it is possible to appropriately reduce the number of bits to be compared in accordance with the required collision probability, and the processing time can be reduced, so that the measurement time can be shortened.
Embodiments configured by partially combining the above-described embodiments and the like also belong to the present invention.

1 is a block diagram showing a configuration of a test circuit for a random number generation circuit according to a first embodiment of the present invention. The circuit diagram which shows the structural example of a stirring circuit. FIG. 3 is a timing chart showing the operation of the first embodiment. 6 is a flowchart illustrating a test method according to the first embodiment. 6 is a flowchart showing a part of a test method according to a second embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... (for random number generation circuits) Test circuit 2 ... Random number generation circuit 6 ... Buffer memory 7 ... Comparison circuit 10 ... Random number generation start signal 16 ... Output data

Claims (5)

A start signal applying means for applying a start signal for generating a random number from an initial state a plurality of times at a predetermined time interval to a random number generating circuit having a transient random number generating characteristic;
Each output data output from the random number generation circuit after the operation time set shorter than the time interval is compared with each other using the time when each start signal is applied as a reference time, and whether there is matching output data Determining means for determining whether or not;
A test circuit for a random number generation circuit, comprising:   The determination means compares each output data output from the random number generation circuit after the operation time with a memory circuit that temporarily stores the output data stored in the memory circuit, and outputs matching data. 2. The test circuit for a random number generation circuit according to claim 1, further comprising a comparison circuit that outputs a determination result of whether or not it exists.   Further, when it is determined by the determining means that there is no matching output data, the operation time value is set to be small, and when the determining means determines that there is matching output data, The operation time boundary value corresponding to the boundary between the output data that does not match the output data that matches the output data is calculated by the determination means by operating with the value of the operation time set to a large value. Test circuit for random number generator circuit described in 1.   When the number of bits of output data output from the random number generation circuit is n, a plurality of output data are compared with each other only by a predetermined number of bits m smaller than the number of bits n, and whether or not they match. 4. The test circuit for a random number generation circuit according to claim 1, wherein the determination is performed. A start signal applying step for applying a start signal for generating a random number from an initial state a plurality of times at a predetermined time interval to a random number generating circuit having a transient random number generation characteristic;
Each output data output from the random number generation circuit after the operation time set shorter than the time interval is compared with each other using the time when each activation signal is applied as a reference time, and there is matching output data A determination step for determining whether or not,
A test method for a random number generation circuit, comprising:

Images