JP2008236660A - Inverter amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, in an inverter amplifier constituted of field effect transistors, since an amplification factor is made worse by gate voltage variation in a field effect transistor that is a constant current source and voltage variation is mixed via a DC bias electric wire in multi-stage connection, adverse influences are exerted each other and desired performance can not be obtained. <P>SOLUTION: An inverter amplifier of the present invention comprises a voltage variation prevention circuit at the gate terminal of a field effect transistor that is a constant current source constituting the amplifier. The voltage variation prevention circuit suppresses voltage variation or the like propagating to the gate terminal. In such a configuration, the gate voltages of field effect transistors constituting the amplifier are not varied and amplification can be performed without impairing an amplification factor of the inverter amplifier. Even in multi-stage connection, the factor that makes each amplifier unstable can be excluded, thereby also accomplishing an amplifier that performs great amplification. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an amplifier circuit in which transistors of a predetermined conductivity type are combined, and more particularly to an inverter amplifier used in a radio-controlled timepiece that receives a standard radio wave including a standard time information signal and displays the time.

  Radio correction clocks receive standard radio waves (eg, 40 kHz radio waves) containing time information and date information from atomic clocks with an accuracy of one second in tens of thousands of years, and correct time errors. This is a watch with a function. For this reason, it is possible to always display an accurate time, and the time adjustment can be saved.

In the radio-controlled timepiece, factors that determine the reception performance of standard radio waves include antenna characteristics and receiving circuit characteristics. In particular, since the receiving circuit is required to have low power consumption, the mounted amplifier circuit is being improved. Since the receiving circuit receives a weak standard radio wave and detects a standard time information signal, a high-magnification amplifier circuit is required at the input unit. That is, there is a high demand for lower power consumption of the amplifier circuit.
For this reason, an inverter amplifier using a field effect transistor or the like is often used for the amplifier circuit in consideration of reduction of current consumption and miniaturization of the circuit.

  Conventionally known inverter amplifiers are high-amplification amplifier circuits that combine transistors of different conductivity types, and have the characteristics that they can be reduced in size and power consumption with a simple configuration. It is what you see.

  In order to use such a conventionally known inverter amplifier for a radio-controlled timepiece, it is necessary to control the amplification factor according to the magnitude of the input signal, but there is a problem that it is difficult to control the linear amplification factor. A technique for solving such a problem is often seen (for example, see Patent Document 1).

  The technique described in Patent Document 1 as a conventional technique is general as an inverter amplifier, and the technique will be described with reference to the drawings. FIG. 7 is a circuit diagram rewritten so as not to depart from the gist of the prior art shown in Patent Document 1. In FIG. In FIG. 7, 10 and 11 are field effect transistors, 1 is a signal input line, 2 and 4 are power supply lines, 3 is a DC bias wire, 5 is a signal output line, and 6 is a DC bias power supply circuit.

The negative side terminal of the DC bias power supply 6 is grounded, the positive side terminal is connected to the gate terminal of the field effect transistor 11, and the signal input line 1 is connected to the gate terminal of the field effect transistor 10.
The source terminal of the field effect transistor 11 is connected to the power supply line 4, and the source terminal of the field effect transistor 10 is connected to the power supply line 2. The drain terminals of the field effect transistors 11 and 10 are connected to form a signal output line 5. That is, the field effect transistors 11 and 10 are connected in series between the power supply lines 2 and 4.
The substrate terminal of the field effect transistor 11 is connected to the power supply line 4, and the substrate terminal of the field effect transistor 10 is connected to the power supply line 2.

A DC power supply (not shown) having the power supply line 4 side positive is connected to the power supply lines 2 and 4, and a potential corresponding to an intermediate value between the power supply line 2 and the power supply line 4 is set in the DC bias power supply circuit 6. When an analog signal is applied to the signal line input 1 in addition to the gate 11, a signal having a phase opposite to that of the amplified signal line input 1 appears on the signal output line 5.
By increasing or decreasing the potential of the DC bias power supply circuit 6, the amplification factor of the signal appearing on the signal output line 5 can be changed.

Japanese Patent Laid-Open No. 56-2715 (page 2, Fig. 1)

  The technique described as the prior art in Patent Document 1 shown in FIG. 7 has an advantage that the amplification factor of the inverter amplifier composed of the field effect transistors 10 and 11 can be linearly controlled by the voltage of the DC bias wire 3. However, according to a study by the inventors, it has been found that when a resistance component is added in series to the DC bias wire 3, there is a problem that the amplification factor of the inverter amplifier is deteriorated.

  As already described, the inverter amplifier shown in FIG. 7 is composed of a field effect transistor. Such a circuit may be constituted by a combination of discrete (single function parts) or may be formed by being integrated on a semiconductor substrate. In both cases, the wiring of each component and each element may be routed. If this wiring is a DC bias electric wire 3, resistance components such as wiring resistance are connected in series to this electric wire. Sometimes.

  When a resistance component is inserted in series with the bias power supply circuit 6 and connected to the gate terminal of the field effect transistor 11, the gate voltage of the field effect transistor 11 changes according to the signal waveform appearing on the signal output line 5. Since a waveform having a phase opposite to that of the signal input line 1 appears, a constant voltage cannot be maintained, and the amplification factor of the inverter amplifier composed of the field effect transistors 10 and 11 is deteriorated. .

  The resistance component inserted in series in the bias power supply circuit 6 causing such a problem includes the internal resistance of the bias power supply circuit 6 itself in addition to the wiring resistance as described above.

  Further, when such inverter amplifiers are connected in multiple stages to greatly amplify the input signal, the voltage fluctuations of the inverter amplifiers are mixed through the DC bias voltage line 3, and an unexpected feedback is caused by the field effect transistor 11. Over the gate terminal. For this reason, the inverter amplifiers may adversely affect each other, resulting in oscillation. In particular, when the bias power supply circuit 6 is a battery, the internal resistance is high, and such a problem is remarkable.

  In other words, in the conventionally known technology, a resistance component is added to the constituent elements, or the internal resistance of the bias power supply circuit to be used is limited, so there is a restriction for normal operation when trying to use it. Many were not practical.

  The inverter amplifier of the present invention is made in order to solve these problems, and includes a voltage fluctuation preventing means, suppresses the fluctuation of the gate voltage of the field effect transistor constituting the inverter amplifier, and follows the theory. An amplifier circuit for obtaining an amplification factor is provided.

  In order to solve the above problems, the present invention employs the following configuration.

A first transistor of one conductivity type and a second transistor of a conductivity type different from the one conductivity type are connected in series between the first power source and the second power source, and their output terminals are shared. In the inverter amplifier that inputs different voltage signals to each other's input terminals,
A voltage fluctuation preventing means is inserted between the input terminal of either the first transistor or the second transistor and a generation source for generating a voltage signal, and the fluctuation of the voltage signal is controlled by the operation of the voltage fluctuation preventing means. It is characterized by correcting.

  The voltage fluctuation preventing means is a filter circuit in which a resistance means is connected in series between an input node and an output node, and a capacitive means is connected between the output node and the first power supply or the second power supply. Features.

  The voltage fluctuation preventing means is a constant voltage circuit that converts a voltage signal of a generation source that generates a voltage signal input to an input node into a predetermined voltage signal and outputs the voltage signal.

  The constant voltage circuit is a voltage regulator circuit having a reference current source, a differential amplifier circuit, and an output circuit.

The inverter amplifier according to the present invention includes voltage fluctuation preventing means for preventing voltage fluctuation occurring in the gate voltage of the field effect transistor for controlling the amplification factor. Since this voltage fluctuation preventing means can suppress the fluctuation of the gate voltage in the field effect transistor constituting the inverter amplifier, it is possible to obtain an amplification factor as designed without malfunction.
In addition, even when it is necessary to increase the amplification factor by connecting inverter amplifiers in multiple stages, voltage fluctuations appearing in the gate voltage of the field effect transistor of each amplification stage that is a constant current source can be removed, and the DC bias voltage Since mixing through the wire can be prevented, it is possible to eliminate a factor that makes the amplifier circuit unstable.

  As described above, since the inverter amplifier of the present invention includes the voltage fluctuation preventing means, even if a battery is used as a generation source for generating a voltage signal, an expected amplification factor can be obtained, and a minute input signal can be obtained. In contrast, a large amplification can be performed while controlling the amplification factor.

Embodiments of an inverter amplifier according to the present invention will be described below in detail with reference to the drawings. In the embodiment of the present invention, a case will be described as an example where the inverter amplifier is used in a reception circuit of a radio-controlled timepiece that receives standard radio waves and corrects the time.
In the present embodiment, an example in which the transistors constituting the inverter amplifier are field effect transistors and P-channel and N-channel types are used will be described.

[Description of whole block: Fig. 1]
FIG. 1 is a block diagram illustrating a first embodiment of an inverter amplifier according to the present invention. In FIG. 1, 50 and 51 are field effect transistors, 52 is a voltage fluctuation prevention circuit as voltage fluctuation prevention means, 61 is a signal input line, 62, 64 and 68 are power supply lines, and 63 is an input of the voltage fluctuation prevention circuit 52. Reference numeral 65 denotes a signal output line, 66 denotes a DC bias power supply, 67 denotes a resistance element, and 69 denotes an output node of the voltage fluctuation preventing circuit 52.
The field effect transistor 51 can be a P-channel type, for example, and the field effect transistor 50 can be an N-channel type, for example.

  The power supply to this circuit will be described as a negative power supply. That is, the power supply line 64 is grounded (for example, 0 V), and the power supply lines 68 and 62 are connected to power supply means for outputting a negative voltage. Of course, the power supply may be operated with a positive power supply. In this case, the power supply lines 68 and 62 may be grounded and the power supply line 64 may be connected to power supply means for outputting a positive voltage.

The DC bias power supply 66 has a negative terminal connected to the power supply line 68, a positive terminal connected to the input node 63 of the voltage fluctuation prevention circuit 52, and an output node 69 that is an output of the voltage fluctuation prevention circuit 52 has a field effect. The gate terminal of the type transistor 51 is connected.
The source terminal of the field effect transistor 51 is connected to the power supply line 64, and the source terminal of the field effect transistor 50 is connected to the power supply line 62. The drain terminals of the field effect transistors 51 and 50 are connected to each other and connected to the signal output line 65. The substrate terminal of the field effect transistor 51 is connected to the power supply line 64, and the substrate terminal of the field effect transistor 50 is connected to the power supply line 62.

A signal input line 61 is connected to the gate terminal of the field effect transistor 50. The signal on the input signal line 61 is an input signal including a time code obtained from a circuit (not shown). The gate terminal and the drain terminal of the field effect transistor 50 are connected by a resistance element 67.
An input signal input from the signal input line 61 is amplified by the field effect transistor 50 in which a feedback circuit is configured by the resistance element 67, and the amplification factor is a voltage between the gate terminal and the source terminal of the field effect transistor 51. Controlled by

As described above, when the DC bias power supply 66 uses a battery or a voltage supply circuit having a low ability to hold a constant voltage, it is subject to voltage fluctuations accompanying a plurality of circuit operations driven by the voltage of the DC bias power supply 66. It is easy to maintain a constant voltage as an ideal power source.
In the inverter amplifier of the present invention, a voltage fluctuation preventing circuit 52 is provided between the DC bias power supply 66 and the gate terminal of the field effect transistor 51. As a result, voltage fluctuations mixed in from other circuits can be removed and the gate voltage of the field effect transistor 51 can be kept constant.
Another problem is that a part of the amplified waveform of the signal output line 65 appears at the gate of the field effect transistor 51 and the amplification factor of the inverter amplifier composed of the field effect transistors 50 and 51 decreases. This can be prevented by suppressing the voltage fluctuation at the gate terminal of the field effect transistor 51 at 52.

[Description of multi-stage connection of inverter amplifier: Fig. 2]
The inverter amplifier of the present invention includes the voltage fluctuation prevention circuit 52 and can suppress fluctuations in the gate voltage of the field effect transistor 51, so that the amplification factor of the inverter amplifier is not deteriorated. Of course, this inverter amplifier may be connected in series and connected in multiple stages to greatly amplify the input signal. Even in such a case, the voltage fluctuation prevention circuit 52 may be provided for each number of stages of the inverter amplifiers. With such a configuration, the voltage fluctuation in each inverter amplifier can be suppressed by each voltage fluctuation prevention circuit 52. The inverter amplifier can operate stably.

  This is shown in FIG. It is a block diagram explaining 2nd Embodiment of the inverter amplifier of this invention. 2, 200a to 200c are the inverter amplifiers shown in FIG. 1, and 500a to 500c are the voltage fluctuation preventing circuit 52 shown in FIG. 213 and 214 are capacitive elements, 223 is a first signal input line, 224 is a first signal output line, 225 is a second signal input line, 226 is a second signal output line, and 227 is a third signal input. Is a line. Reference numeral 228 denotes a third signal output line, which is an output signal line of this multistage amplifier. In addition, the same number is provided to the same structure already demonstrated.

  As shown in FIG. 2, three inverter amplifiers and a voltage fluctuation preventing circuit are connected to form a three-stage multistage amplifier. Capacitance elements 213 and 214 are inserted between the inverter amplifiers. Voltage fluctuation prevention circuits 500a, 500b, and 500c inputs are connected to a DC bias power supply 66.

The signal input from the first signal input line 223 is amplified by the inverter amplifier 200 a and output to the first signal output line 224. The amplified signal of the first signal output line 224 is removed from the direct current component by the capacitor 213, is transmitted through the second input signal line 225, is amplified by the inverter amplifier 200 b, and is output to the second signal output line 226.
The amplified signal of the second signal output line 226 is removed from the DC component by the capacitor 214, is transmitted through the third input signal line 227, is amplified by the inverter amplifier 200 c, and is output to the third signal output line 228.

  Further, each input of the voltage fluctuation preventing circuits 500a, 500b, 500c is connected to a DC bias power supply 66, and voltage fluctuations propagated from the input node 63 are removed, and each inverter is output by the output of each inverter amplifier. Voltage fluctuations generated at the gate terminal of the field effect transistor constituting the amplifier are suppressed.

[Description of Voltage Fluctuation Prevention Circuit 1: FIGS. 3 and 4]
Next, the voltage fluctuation preventing circuit 52 will be described. FIG. 3 is a circuit diagram for explaining an example of the voltage fluctuation preventing circuit 52 shown in FIG. In FIG. 3, 70 is a resistance element, 71 is a capacitance element, and 72 is a power supply node. The same numbers are assigned to the same configurations already described.

A resistance element 70 is connected in series between the input node 63 and the output node 69, and a capacitance element 71 is connected between a connection point between the resistance element 70 and the output node 69 and the power supply node 72.
The power supply node 72 is a node connected to power supply means having a constant voltage, and is connected to the ground or the power supply line 68, for example.

An example of the voltage fluctuation prevention circuit 52 shown in FIG. 3 is a kind of filter circuit, in which voltage fluctuation due to the output waveform of the signal output line 65 propagated to the gate of the field effect transistor 51 is smoothed by the capacitor 71 and input node This is a first-order low-pass filter that is separated by a resistance element 70 so that voltage fluctuations are not transmitted to 63.
This circuit can also eliminate voltage fluctuations from another circuit driven by the DC bias power supply 66.

The time constants of the resistance element 70 and the capacitance element 71 used in this circuit can be freely selected. The time constant in this case is a value obtained by multiplying the resistance value of the resistance element 70 and the capacitance value of the capacitance element 71. This time constant can be freely changed in accordance with the capacity and electrical characteristics of the inverter amplifier and the specifications of the circuit and system using the inverter amplifier of the present invention.
For example, depending on the frequency of voltage fluctuation propagating to the gate of the field effect transistor 51 and its value, it may be better not to make the resistance element 70 too large. At that time, in view of the resistance value, the capacitance value of the capacitive element 71 is increased.
Of course, when the inverter amplifiers are connected in series as shown in FIG. 2 and connected in multiple stages to greatly amplify the input signal, the time constants may be individually changed in the voltage fluctuation preventing circuits 500a, 500b, 500c. Needless to say.

  The voltage fluctuation preventing circuit 52 shown in FIG. 3 is a primary low-pass filter. However, when the gate voltage fluctuation of the field effect transistor 51 is significant, a plurality of circuits shown in FIG. It is good also as a low-pass filter.

  FIG. 4 is a circuit diagram for explaining an example of the voltage fluctuation prevention circuit 52 shown in FIG. 1, and is a circuit having a configuration different from the example shown in FIG. In FIG. 4, reference numeral 73 denotes a field effect transistor, and the same reference numerals are given to the same components already described.

The difference between the example shown in FIG. 4 and the example shown in FIG. 3 is that a field effect transistor 73 is used instead of the capacitor 71. Field effect transistor 73 is connected in series between a connection point between resistance element 70 and output node 69 and power supply node 72. The gate terminal of the field effect transistor 73 is connected to the power supply node 72. The power supply means connected to the power supply node 72 is the same as that shown in FIG.

When the inverter amplifier of the present invention is integrated as a semiconductor device on a semiconductor substrate, the field effect transistor 73 can have the same structure as a normal field effect transistor. For this reason, compared with the case where the capacitive element 71 is used, the occupation area of an element can be made small.
The configuration shown in FIG. 4 is also a primary low-pass filter, and the operation is the same as the configuration shown in FIG.

[Description of Voltage Fluctuation Prevention Circuit 2: FIGS. 5 and 6]
Next, still another configuration example of the voltage fluctuation preventing circuit 52 will be described. FIG. 5 is a circuit diagram for explaining an example of the voltage fluctuation preventing circuit 52 shown in FIG. 1, and is a circuit different from the configuration already described. In FIG. 5, 52a is a constant voltage circuit. The same numbers are assigned to the same configurations already described.

  The constant voltage circuit 52a shown in FIG. 5 is a voltage circuit that is connected to the power supply line 62 and the power supply line 64 and outputs a constant voltage therebetween. The configuration of the constant voltage circuit 52a is not particularly limited, but a configuration in which a field effect transistor or a resistance element is connected in series between the power supply line 62 and the power supply line 64 can be used. What is important is that a constant voltage is output even when the power supply line 62 and the power supply line 64 vary.

FIG. 6 is a circuit diagram illustrating the configuration of the constant voltage circuit 52a shown in FIG. 5, and shows an example of a regulator circuit.
In FIG. 6, reference numeral 80a is a reference current source for generating a reference voltage, 80b is a differential amplifier circuit, and 80c is an output circuit.
In FIG. 6, 81 is a resistance element, 93 is a capacitance element, 82, 83, 84 and 85 are field effect transistors constituting the reference current source 80a, and 86, 87, 88, 89 and 90 are differential amplifier circuits 80b. Field effect transistors 91 and 92 are field effect transistors constituting the output circuit 80c. Reference numerals 100 and 101 denote power supply lines.

  The regulator circuit shown in FIG. 6 amplifies the reference voltage generated by the reference current source 80a by a 1 × differential amplifier circuit, converts the voltage into a predetermined voltage by the output circuit 80c, and outputs the voltage. Of course, the configuration of the regulator circuit shown in FIG. 6 is an example, and the circuit configuration is not particularly limited, and can be freely changed. For example, the magnification of the differential amplifier circuit 80b may be changed.

The constant voltage circuit 52a shown in FIGS. 5 and 6 operates so as to keep the gate voltage of the field effect transistor 51 constant. For this reason, the voltage fluctuation propagating from the signal output line 65 is suppressed, and a constant gate voltage is always applied to the gate terminal of the field effect transistor 51 even if the power supply lines 62 and 64 undergo voltage fluctuation.
Therefore, voltage fluctuations mixed in from other circuits can be removed and the gate voltage of the field effect transistor 51 can be kept constant.

The constant voltage circuit 52a shown in FIGS. 5 and 6 can also be used for a multistage amplifier in which a plurality of inverter amplifiers and a voltage fluctuation preventing circuit as shown in FIG. 2 are connected. In that case, the circuit configuration of the constant voltage circuit 52a and the voltage of the constant voltage may be changed for each inverter amplifier, and can be freely changed according to the specifications of the circuit and system using the inverter amplifier of the present invention.

  The inverter amplifier of the present invention can realize an inverter circuit that can be controlled almost linearly without losing the amplification factor with a small circuit configuration with a small number of implemented parts. For this reason, it is suitable as an automatic gain control device that requires amplification magnification control in accordance with the magnitude of the input signal or an amplification circuit mounted for a radio-controlled timepiece that requires high accuracy.

It is a circuit diagram explaining the structure of the inverter amplifier provided with the voltage variation prevention circuit of this invention. It is a circuit diagram explaining an example of the multistage connection by the inverter amplifier provided with the voltage variation prevention circuit of this invention. It is a circuit diagram explaining the voltage variation prevention circuit of the inverter amplifier of this invention. It is a circuit diagram explaining the example from which the voltage variation prevention circuit of the inverter amplifier of this invention differs. It is a circuit diagram explaining the further different example of the voltage variation prevention circuit of the inverter amplifier of this invention. FIG. 3 is a circuit diagram illustrating a regulator circuit which is an example of a constant voltage circuit constituting the voltage fluctuation prevention circuit of the inverter amplifier of the present invention. It is a circuit diagram explaining the prior art shown in patent document 1. FIG.

Explanation of symbols

50, 51 Field effect transistor 52 Voltage fluctuation prevention circuit 52a Constant voltage circuit 61 Signal input line 62, 64, 68 Power supply line 63 Input node 65 Signal output line 66 DC bias power supply 67 Resistive element 69 Output node

Claims (4)

A first transistor of one conductivity type and a second transistor of a conductivity type different from the one conductivity type are connected in series between the first power source and the second power source, and the output terminals of each other are connected. In the inverter amplifier that is common and inputs different voltage signals to each other's input terminals,
A voltage fluctuation preventing means is inserted between the input terminal of one of the first transistor or the second transistor and a generation source for generating the voltage signal, and by the operation of the voltage fluctuation preventing means, An inverter amplifier that corrects fluctuations of the voltage signal.   The voltage fluctuation preventing means is a filter circuit in which a resistance means is connected in series between an input node and an output node, and a capacitance means is connected between the output node and the first power supply or the second power supply. The inverter amplifier according to claim 1, wherein:   2. The constant voltage circuit according to claim 1, wherein the voltage fluctuation preventing means is a constant voltage circuit that converts a voltage signal of a generation source that generates the voltage signal input to the input node into a predetermined voltage signal and outputs the voltage signal. Inverter amplifier.   4. The inverter amplifier according to claim 3, wherein the constant voltage circuit is a voltage regulator circuit having a reference current source, a differential amplifier circuit, and an output circuit.

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