JP2008235798A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein the value of resistance in a resistive element is changed by the thermal diffusion of impurities from the lower electrode of a capacitive element to the resistive element section due to heat treatment in the formation of a dielectric film in the capacitive element when creating a semiconductor element, such as MISFETs, the capacitive elements, and the resistive elements, on the same semiconductor substrate. <P>SOLUTION: In the structure of a semiconductor device, a projection or a recess is provided partially on an element separation film between conductive materials between a lower electrode for composing the capacitive element and the resistive element, thus preventing impurities traveling in the film due to heat treatment in the formation of the dielectric film of the capacitive element from reaching a nearby element and preventing the concentration of the impurities in the resistive element from changing. With such a structure, the resistive element having a prescribed resistance value can be obtained. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method of forming a semiconductor device including a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a resistive element, and a capacitive element on the same semiconductor substrate, and in particular, sets the resistive element to a predetermined value. The present invention relates to a structure of a semiconductor device capable of performing

In recent years, active elements such as MISFETs or passive elements such as resistance elements and capacitive elements have been miniaturized due to demands for higher integration of semiconductor devices. As a result, capacitive elements and resistive elements that require a certain large area on the semiconductor substrate can be mounted on the semiconductor substrate, and the development of integrated circuits that form all necessary elements on the semiconductor substrate has become active. .
In particular, a technique for forming a capacitive element or a resistive element on an insulating region provided on a semiconductor substrate is known (see, for example, Patent Document 1).

  This will be described with reference to the drawings. FIG. 7 is a cross-sectional view schematically showing a cross section of a semiconductor device, which is a diagram rewritten for ease of explanation while considering the prior art shown in Patent Document 1 without departing from the gist thereof. It is. In FIG. 7, 1 is a semiconductor substrate made of silicon, 2 is an element isolation film which is an insulating region such as a field insulating film, 3 is a gate insulating film of MISFET, 4 is a polysilicon layer, and 5 is a dielectric film. . 40a and 40b are impurities added to the polysilicon layer. This impurity is indicated by a circle. Dashed arrows indicate the migration of impurities.

  FIG. 7 is a diagram showing a state during the manufacturing process of a semiconductor device in which a capacitive element is formed in the capacitive element portion, a resistive element is formed in the resistive element portion, and a MISFET is formed in the MISFET portion. A capacitor element completed after the manufacturing process has a configuration in which an upper electrode and a lower electrode are arranged to face each other and a dielectric layer is sandwiched therebetween. The lower electrode is formed by adding an impurity 40a to a predetermined region of the polysilicon layer 4 and processing its shape in a predetermined process. The dielectric layer processes the dielectric film 5 into a predetermined shape. Although the upper electrode is not shown, it is similarly processed into a predetermined shape.

The resistance element is formed by adding an impurity 40b to a predetermined region of the polysilicon layer 4 and processing its shape in a predetermined process.
The MISFET forms the gate electrode by processing the polysilicon layer 4 into a predetermined shape.
That is, the lower electrode and the resistance element of the capacitive element are formed of the same polysilicon layer 4.

Japanese Patent Laid-Open No. 11-54700 (page 5, FIG. 7)

  In the prior art disclosed in Patent Document 1, since the lower electrode and the resistance element constituting the capacitor element are formed of the same polysilicon layer, the manufacturing process can be shortened by forming them separately. Although there is an advantage, when the inventor examined, it was found that the resistance value of the resistance element might be different from the design value.

That is, due to the heat applied when forming the dielectric film 5, the impurity 40a is thermally diffused in the polysilicon layer 4 in the direction of the impurity 40b, and as a result, the impurity concentration of the impurity 40b changes and resistance is increased. The resistance value of the element changes. In FIG. 7, the movement of the impurity 40a in the direction of the impurity 40b is indicated by a dashed arrow.

For example, the concentration of the impurity 40a added to the region to be the lower electrode is 1 × 10 ¹⁵ atoms / cm ² , and the concentration of the impurity 40b to be added to the region to be the resistance element is 1 × 10 ¹³ to 10 ¹⁴ atoms / cm ² . . The impurity concentration in the region serving as the resistance element is very low compared to the impurity concentration in the region serving as the lower electrode. For this reason, when the impurity 40a moves and reaches the portion of the impurity 40b by the heat in the process of forming the dielectric film 5, the impurity concentration of the impurity 40b changes.

  In order to solve such a problem, the impurity concentration of the resistance element formed in the resistance element portion may be lowered in advance in consideration of this thermal diffusion. However, such impurity concentration can be set if there is only one pair of a capacitive element and a resistive element on a semiconductor substrate, but a high integration in which a plurality of elements are freely laid out according to the specifications of the semiconductor device. In recent semiconductor devices, the impurity concentration has to be changed for each element arrangement location. This is not practical because it requires a manufacturing process for adding impurities at each element location.

  In other words, the prior art disclosed in Patent Document 1 does not achieve a target value even if a resistance element is manufactured so as to have a resistance value as designed, and can be applied to a highly integrated semiconductor device. There wasn't.

  The present invention has been made in order to solve such a problem, and a semiconductor having a predetermined resistance value even if an element different from the resistance element is mixedly mounted on the same semiconductor substrate. An apparatus structure is provided.

  In order to achieve the above object, the structure of the semiconductor device of the present invention adopts the following structure.

In a semiconductor device in which a plurality of elements having different structures are mixedly mounted on a semiconductor substrate, the elements include a capacitor element having a structure in which an upper electrode and a lower electrode face each other, and a resistance element formed by processing a semiconductor layer into a predetermined shape MISFET, which is provided on a semiconductor substrate or an element isolation film provided on the semiconductor substrate,
When any two of the conductive materials constituting the lower electrode of the capacitive element, the conductive material constituting the resistive element, and the conductive material constituting the gate electrode of the MISFET are adjacent to each other, the conductive materials A convex portion or a concave portion is provided between the semiconductor substrate or the semiconductor substrate or the element isolation film or the element isolation film.

  The convex portion or the concave portion is formed by processing a semiconductor substrate or an element isolation film, and is formed integrally.

  The convex part or the concave part has a tapered shape in cross section.

  The convex portion is a material different from the conductive material.

  The recess is filled with a material different from the conductive material.

The present invention forms a lower electrode and a resistance element of a capacitive element, for example, in a semiconductor substrate or on a semiconductor substrate or in an element isolation film or on an element isolation film between the same conductive material such as a polysilicon layer Protrusions or recesses are provided.
With such a structure, since the conductive material is formed along the convex portion or the concave portion, the capacity is increased by the height of the convex portion or the concave portion as compared with the case where there is no convex portion or the concave portion. The distance between the conductive materials between the portion serving as the lower electrode of the element and the portion serving as the resistance element can be substantially increased.
As a result, even when high heat treatment is applied to the entire semiconductor substrate when forming the dielectric film, the high concentration impurity in the portion that becomes the lower electrode of the capacitor element is added through the inside of the conductive material. It does not reach the portion that becomes the resistance element by thermal diffusion. Thereby, the resistance element can have a predetermined resistance value.

In addition, the convex portion or the concave portion can have a tapered cross section, or can be formed of a material different from the conductive material forming the lower electrode and the resistance element of the capacitor element. Furthermore, the recess may be filled with a material different from the conductive material.
By doing so, even when the lower electrode of the capacitor element and the resistor element are arranged close to each other, the distance of the conductive material can be substantially increased, and the impurity of low concentration passes through the inside of the conductive material. It is possible to prevent thermal diffusion to the part to which is added.

  Hereinafter, embodiments of a semiconductor device of the present invention will be described with reference to the drawings. In the present embodiment, an example in which a semiconductor substrate is a silicon semiconductor substrate will be described.

[Description of Structure of First Embodiment: FIGS. 1A and 1B]
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. 1A and 1B are cross-sectional views schematically showing the shape of the semiconductor device of the present invention. The boundaries of the arrangement regions of the capacitive element portion, the resistive element portion, and the MISFET portion are indicated by arrows for easy explanation.
FIG. 1A is a cross-sectional view illustrating a structure in which a convex portion is provided in an element isolation film between each of a capacitive element portion, a resistive element portion, and a MISFET portion. FIG. 1B is a cross-sectional view illustrating a structure in which a recess is provided in the element isolation film between the capacitor element portion, the resistor element portion, and the MISFET portion.

First, the structure of the semiconductor device of the present invention will be described with reference to FIG. In FIG. 1A, 1 is a semiconductor substrate made of silicon, 2 is an element isolation film such as a field insulating film, 3 is a gate insulating film of MISFET, 4a is a lower electrode of a capacitive element, 4b is a resistance element, 4c is A gate electrode of MISFET, 5 is a dielectric film, 6a is an upper electrode of a capacitor, 7a is a source region of MISFET, and 7b is a drain region of MISFET. Reference numerals 40a, 40b, and 60a denote impurities, which are indicated by ◯ and Δ in the figure. A convex portion 8 is provided on the element isolation film 2.
In FIG. 1B, reference numerals 1 to 60a are the same as those in FIG. 1A, and reference numeral 9 denotes a recess provided in the element isolation film 2.

  A region for forming an element is determined by an element isolation film 2 selectively provided on the semiconductor substrate 1. Of course, both the upper portion of the semiconductor substrate 1 and the upper portion of the element isolation film 2 are regions for forming elements. Above the element isolation film 2, a capacitive element portion for forming a capacitive element and a resistive element portion for forming a resistive element are provided. A MISFET portion for forming a MISFET is provided on the upper portion of the semiconductor substrate 1.

In the configuration shown in FIG. 1, the element isolation film 2 is provided with a convex portion 8 and a concave portion 9, each of which is formed by processing the element isolation film 2, and is integrated with the element isolation film 2. The convex portion 8 or the concave portion 9 is provided between the capacitive element portion and the resistive element portion, or between the resistive element portion and the MISFET portion. In the example shown in FIG. 1, two are provided between the resistive element portion and another adjacent element portion.

In the example shown in FIG. 1, the convex portion 8 is provided in the upper portion of the element isolation film 2, and the concave portion 9 is provided in the element isolation film 2.
That is, the convex portion 8 and the concave portion 9 are provided inside the semiconductor substrate 1 or above the semiconductor substrate 1, inside the element isolation film 2, or above the element isolation film 2.

  The capacitive element has a configuration in which an upper electrode 6a and a lower electrode 4a formed by processing a polysilicon layer are arranged to face each other, and a dielectric film 5 is sandwiched therebetween. The capacitance of the capacitive element can be determined by the dielectric constant of the dielectric film 5.

  The resistance element 4b is formed by processing a polysilicon layer and includes an impurity 40b. In the MISFET, a source region 7a and a drain region 7b are provided in a semiconductor substrate 1, a gate insulating film 3 is provided above the semiconductor substrate 1 between them, and a gate electrode 4c formed by processing a polysilicon layer is provided thereon. Provided.

[Description of Operation of First Embodiment: FIGS. 2A and 2B]
Next, the operation of the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a diagram showing a state in the middle of the manufacturing process of the first embodiment of the present invention. FIG. 1 (a) is FIG. 2 (a), and FIG. 1 (b) is FIG. 2 (b). It corresponds to each.

  As shown in FIGS. 2A and 2B, an element isolation film 2 having a predetermined thickness is selectively formed on the semiconductor substrate 1. Thereafter, a convex portion 8 in FIG. 2A or a concave portion 9 in FIG. 2B is formed in the element isolation film 2 by a known photolithography etching method. Thereafter, a gate insulating film 3 having a predetermined thickness is formed. Of course, the gate insulating film 3 may be formed before the convex portion 8 or the concave portion 9 is formed.

  Thereafter, the polysilicon layer 4 is formed on the element isolation film 2, the convex portion 8 or the concave portion 9. The polysilicon layer 4 is formed not only on the top of the convex portion 8 or on the bottom of the concave portion 9 but also along the side surfaces of the convex portion 8 and the concave portion 9.

Thereafter, the impurity 40a is added to the portion that becomes the lower electrode of the capacitor element, and the impurity 40b is added to the portion that becomes the resistance element by a known ion implantation method. For example, the impurity concentration is set to 1 × 10 ¹⁵ atoms / cm ² and the concentration of the impurity 40b is set to 1 × 10 ¹³ to 10 ¹⁴ atoms / cm ² .
Thereafter, the dielectric film 5 is formed on the polysilicon layer 4. 2A and 2B schematically show the state of the manufacturing process so far.

As already described, due to the heat applied when the dielectric film 5 is formed, the impurity 40a is thermally diffused in the polysilicon layer 4 in the direction of the impurity 40b.
The distance by which the impurities thermally diffuse inside the polysilicon layer 4 has a certain value depending on the film quality of the polysilicon layer 4, the impurity concentration, and the temperature, but the polysilicon layer 4 extends along the side surfaces of the protrusions 8 and the recesses 9. In this case, the distance of the polysilicon layer 4 between the portion serving as the lower electrode and the portion serving as the resistance element of the capacitive element is substantially increased. This is because of the level difference caused by the convex portions 8 and the concave portions 9. Thereby, it is possible to prevent thermal diffusion of impurities into the resistance element portion.

As a result, since the impurity 40a does not reach the portion of the impurity 40b, the impurity concentration of the impurity 40b does not change, and a resistance element having a predetermined resistance value can be formed.
In FIG. 2, the state in which the impurity 40a moves in the direction of the impurity 40b is indicated by a dashed arrow.

[Explanation of Second Embodiment: FIGS. 3 (a) and 3 (b)]
Next, a second embodiment of the present invention will be described with reference to the drawings. 3A and 3B are cross-sectional views schematically showing the shape of the semiconductor device of the present invention. The boundaries of the arrangement regions of the capacitive element portion, the resistive element portion, and the MISFET portion are indicated by arrows for easy explanation.

  The second embodiment is provided with the convex portion 8 and the concave portion 9 as in the first embodiment already described, but the shape thereof is different. In FIG. 3, 80 is a convex portion having a tapered shape provided in the element isolation film 2, and 90 is a concave portion having a tapered shape provided in the element isolation film 2. The taper shape refers to a shape in which the end surfaces of the convex portion and the concave portion are not vertical but have a certain angle (inclination). The same numbers are assigned to the same components as those already described.

[Description of Operation of Second Embodiment: FIGS. 4A and 4B]
Next, the operation of the second embodiment of the present invention will be described with reference to FIG. FIGS. 4A and 4B are views showing a state in the middle of the manufacturing process of the second embodiment of the present invention, FIG. 3A being FIG. 4A and FIG. 3B being FIG. It corresponds to each.

  As shown in FIGS. 4A and 4B, an element isolation film 2 having a predetermined thickness is selectively formed on the semiconductor substrate 1, and then the element isolation film 2 is formed by a known photolithography etching method. Then, the convex part 80 and the concave part 90 are formed. Thereafter, a gate insulating film 3 having a predetermined thickness is formed, and then the polysilicon layer 4 is formed on the element isolation film 2, the convex portion 80 or the concave portion 90. The polysilicon layer 4 is formed not only on the upper part of the convex part 80 or the bottom part of the concave part 90 but also on the side surfaces of the convex part 80 and the concave part 90.

  As already described, the heat applied when forming the dielectric film 5 causes the impurity 40a to thermally diffuse inside the polysilicon layer 4 in the direction of the impurity 40b. Since it is also formed along the side surfaces of 80 and the recess 90, the distance of the polysilicon layer 4 between the portion serving as the lower electrode of the capacitive element and the portion serving as the resistance element is substantially increased. This is because of a more complicated level difference due to the tapered shape of the convex portion 80 and the concave portion 90. Thereby, it is possible to prevent thermal diffusion of impurities into the resistance element portion.

As a result, since the impurity 40a does not reach the portion of the impurity 40b, the impurity concentration of the impurity 40b does not change, and a resistance element having a predetermined resistance value can be formed.
In FIG. 4, the manner in which the impurity 40a moves in the direction of the impurity 40b is indicated by broken line arrows as in FIG.

[Description of Third Embodiment: FIGS. 5A and 5B]
Next, a third embodiment of the present invention will be described with reference to the drawings. 5A and 5B are cross-sectional views schematically showing the shape of the semiconductor device of the present invention. The boundaries of the arrangement regions of the capacitive element portion, the resistive element portion, and the MISFET portion are indicated by arrows for easy explanation.

In the third embodiment, a convex portion and a concave portion are provided on the upper portion of the element isolation film 2 as in the first and second embodiments already described, but the structure is different. In FIG. 5, 81 is a convex portion provided on the upper portion of the element isolation film 2, and 82 is a convex portion having a tapered shape provided on the upper portion of the element isolation film 2. The same numbers are assigned to the same components as those already described.

  The convex portions 81 and 82 are configured separately from the element isolation film 2. The conductive element is formed of a material different from the conductive material that forms the lower electrode of the capacitor element and the resistor element. Although this material is not particularly limited, it can be composed of a metal such as copper or titanium, an insulating film such as a nitride film, or a laminated film of a nitride film or an oxide film.

  The shapes of the convex portions 81 and 82 can be freely determined without being influenced by the film thickness or planar shape of the element isolation film 2. For this reason, since it does not affect the element isolation capability and insulation isolation capability of the element isolation film 2, it is possible to form a resistance element having a predetermined resistance value while having a degree of freedom in design.

[Explanation of Fourth Embodiment: FIGS. 6 (a) and 6 (b)]
Next, a fourth embodiment of the present invention will be described with reference to the drawings. 6A and 6B are cross-sectional views schematically showing the shape of the semiconductor device of the present invention. The boundaries of the arrangement regions of the capacitive element portion, the resistive element portion, and the MISFET portion are indicated by arrows for easy explanation.

  4th Embodiment provides the recessed part 9 similarly to 1st Embodiment already demonstrated, However, The structure differs. In FIG. 6, reference numeral 9 a denotes a filling material that fills the recess 9 provided in the element isolation film 2. 6A shows a normal recess 9 and FIG. 6B shows a recess 9 having a tapered shape. The same numbers are assigned to the same components as those already described.

  In the first embodiment and the second embodiment already described, the filling 9a does not exist inside the recess 9, and air exists, for example. The width or depth of the recess 9 may be small, but when the recess 9 is large, the semiconductor device manufacturing process proceeds and an interlayer insulating film is formed thereon by a known method. There are cases where the flattening of the insulating film is hindered.

  If the interlayer insulating film is not flattened, the metal wiring provided thereon may be broken. However, in the fourth embodiment of the present invention, since the recess 9 is filled with the filler 9a, the flatness is maintained.

Various methods can be used to form the filler 9a or 9b. Although illustration is omitted, for example, after the element isolation film 2 is formed, the recess 9 is formed by a known photolithography etching method. Thereafter, a filling material film made of a material different from the conductive material that forms the lower electrode portion and the resistance element portion of the capacitor element is formed, and the recess 9 is filled with the film. Then, the filling material 9a can be formed by removing the filling material film other than the region of the recess 9 by a known chemical polishing method or the like.
There is no particular limitation on the filler material film, but an insulating film such as an oxide film or a stacked film of a nitride film or an oxide film can be used.

  In the embodiment of the present invention described above, the example in which the two convex portions 8 and the concave portions 9 are provided has been described, but the number of the convex portions 8 and the concave portions 9 is not limited thereto. In the first place, the portion where the convex portion 8 or the concave portion 9 is provided is between regions where there is a difference in impurity concentration implanted into the polysilicon layer 4. In the example, the regions having different impurity concentrations are between the capacitive element portion and the resistive element portion, and between the resistive element portion and the MISFET portion. Of course, it may be provided freely depending on the electrical characteristics required for the resistance element and the MISFET.

In the structure of the semiconductor device of the present invention described above, a convex portion or a concave portion is provided on the element isolation film or the element isolation film. However, the convex portion or the concave portion may be provided on the semiconductor substrate or the semiconductor substrate. In the embodiment of the present invention, an example in which a silicon semiconductor substrate is used as the semiconductor substrate has been described, but an SOI (Silicon On Insulator) substrate may be used as the semiconductor substrate. In that case, a convex portion or a concave portion can be provided on the semiconductor substrate.
Regardless of which form of substrate is used, what is important is to provide a convex portion or a concave portion in a suitable place. In view of the arrangement of the substrate or semiconductor element to be used, the arrangement of the convex portion or the concave portion is appropriately determined. It can be changed.

  The structure of the semiconductor device of the present invention does not cause a change in the resistance value of the resistance element in the vicinity of the capacitive element. Therefore, the semiconductor device is suitable for a semiconductor device that requires high integration, in which a semiconductor element such as a capacitor element or a resistance element needs to be formed over the same semiconductor substrate.

It is sectional drawing explaining the convex part and recessed part of 1st Embodiment of the semiconductor device of this invention. It is sectional drawing explaining the effect | action of 1st Embodiment of the semiconductor device of this invention. It is sectional drawing explaining the convex part of the 2nd Embodiment of the semiconductor device of this invention, and a recessed part. It is sectional drawing explaining the effect | action of 2nd Embodiment of the semiconductor device of this invention. It is sectional drawing explaining the convex part and recessed part of 3rd Embodiment of the semiconductor device of this invention. It is sectional drawing explaining the convex part and recessed part of 4th Embodiment of the semiconductor device of this invention. It is sectional drawing for demonstrating the prior art shown in patent document 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation film 3 Gate insulating film 4 Polysilicon layer 4a Lower electrode of capacitive element 4b Resistive element 4c Gate electrode 5 Dielectric film 6 Polysilicon layer 6a Upper electrode of capacitive element 40a, 40b, 60a Impurity 7a Source region 7b Drain region 8, 80, 81, 82 Convex 9,90 Concave 9a Filling

Claims (5)

In a semiconductor device in which a plurality of elements having different structures are mixedly mounted on a semiconductor substrate, the element includes a capacitor element having a structure in which an upper electrode and a lower electrode face each other, and a resistor formed by processing a semiconductor layer into a predetermined shape An element, a MISFET, provided on the semiconductor substrate or an element isolation film provided on the semiconductor substrate;
When any two of the conductive materials constituting the lower electrode of the capacitive element, the conductive material constituting the resistive element, and the conductive material constituting the gate electrode of the MISFET are adjacent to each other, A semiconductor device, wherein a convex portion or a concave portion is provided in the semiconductor substrate between the conductive materials or on the semiconductor substrate or in the element isolation film or on the element isolation film.   The semiconductor device according to claim 1, wherein the convex portion or the concave portion is formed by processing the semiconductor substrate or the element isolation film and is integrally formed.   The semiconductor device according to claim 1, wherein a cross section of the convex portion or the concave portion has a tapered shape.   The semiconductor device according to claim 1, wherein the convex portion is made of a material different from the conductive material.   The semiconductor device according to claim 1, wherein the recess is filled with a material different from the conductive material.

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