JP2008220584A - Display controller for game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To raise the transfer rate of data when a buffer means is arranged between an LSI for image processing and a data storage means in a display controller for a game machine. <P>SOLUTION: When a VDP 134 continuously outputs an address signals a plurality of times in order to call image data having a size not to be output by one-time data signal, from a character ROM 136, the VDP 134 outputs the address signal Address (1), and then outputs the succeeding address signal Address (1) before a data acquisition time of the preceding address signal elapses. The VDP 134 outputs the succeeding address signal Address (1), and then acquires a data signal Data (4) based on the preceding address signal Address (1). Consequently, the transfer rate is raised by shortening a transfer time by one-page unit for the portion of a delay time generated in a level shifter 200. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a display control device for a gaming machine, and more particularly, to a gaming machine used in various game machines such as a ball game machine such as a pachinko machine, a revolving game machine such as a slot machine or a pachislot machine, and a poker game machine. The present invention relates to a display control device.

In recent years, the load applied to the CPU (Central Processing Unit) of the display control board is increasing more and more, such as the image displayed on the display device of the gaming machine has a high resolution and adopts 3D (Dimension). The volume of image data to be displayed on the display device increases, and there are not a few game machines equipped with a large-capacity storage device (ROM (Read Only Memory) or the like).

The display control circuit for controlling the display on the display device calls a large amount of necessary image data from the ROM in accordance with a command (display list) from the CPU, but the image data acquired from the ROM (compressed one) ) And pasting to the frame buffer and outputting to the display device, it has quite a lot of work, and it is an LSI for image processing (Large Scaled Integration) just by calling image data from ROM If the load of VDP (Video Display Processor) is monopolized, there is a possibility that other processing cannot be executed. Alternatively, there is a possibility that only small-size image data can be handled in order to reduce the load related to transfer.

The VDP mounted on the display control circuit is driven at 3.3V, while the ROM or the like is controlled at 1.8V. In such a case, since the connection cannot be made with different potentials, a level shifter is arranged between the VDP and the ROM, and the potential is converted there.

Patent Document 1 describes a synchronous semiconductor memory device that can shorten the clock access time, but does not describe a technique that operates asynchronously as in the present invention.
JP 2001-110185 A

However, the conventional display control apparatus for gaming machines has a problem that the conversion work by the level shifter, generally a buffer (corresponding to the buffer means of the present invention) takes several ns, and the processing becomes slow. Specifically, referring to a timing chart representing data transmission / reception between VDP and ROM in the conventional display control device for gaming machines shown in FIG. 6, when an address signal Address (1) of data desired by VDP is output, a buffer (level shifter) After a delay time of 5 ns occurs, the address signal Address (2) is output to the ROM. In response to the first request from the VDP, the ROM receives its address signal after 102.5 ns (after 22.5 ns for the data request stored in the subsequent address that is continuous with the address of the data requested for the first time). The data signal Data (3) corresponding to Address (2) is output. The output data signal Data (3) has a delay time of 5 ns in the buffer (level shifter), and then the data signal Data (4) is output to the VDP (VDP can acquire the data signal Data (4). become). In other words, the delay time in the buffer (level shifter) is 5 ns when the address signal is output and 5 ns when the data signal is output. Therefore, an extra 10 ns is required for each data signal (8, 16, or 32 bits) received. It will depend on.

The present invention has been made in view of such circumstances, and when there is a buffer means (such as a level shifter) between the image processing LSI and the data storage means, conventionally, a data signal for the output address signal is acquired. Then, the next address signal is output, whereas the next address signal is output and then the data signal for the previous address signal is acquired. It is an object of the present invention to provide a display control device for a gaming machine that reduces the influence on the delay time and increases the data transfer capability from the image processing LSI to the data storage means.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, a display control device for a gaming machine according to claim 1 includes a data storage unit storing image data to be displayed on a display unit provided in the gaming machine, and the data storage unit. In a display control apparatus for a gaming machine, comprising: an image processing LSI that reads image data and outputs the image data to the display means; and a buffer means disposed between the image processing LSI and the data storage means. The processing LSI outputs an address signal for reading image data stored at a predetermined address of the data storage means, and outputs the address signal after a predetermined data acquisition time has elapsed since the output of the address signal. A data signal output from the data storage means is obtained, and the data storage means obtains the address signal after obtaining the address signal. After the data output time has elapsed, the image data stored at the predetermined address is output as a data signal, and the buffer means acquires the address signal output by the image processing LSI and then acquires the predetermined address signal. When the delay time elapses, the address signal is output to the data storage means, and when the data signal output from the data storage means is acquired, the data signal is sent to the image processing LSI after the delay time elapses. When the image processing LSI outputs an address signal a plurality of times in succession in order to call image data of a size that cannot be output by a single data signal from the data storage means, The next address signal is output before the data acquisition time elapses after the address signal is output. And obtaining the data signal based from the output of the address signal to the previous address signal. According to the display control device for a gaming machine according to claim 1, when the address signal is output a plurality of times in succession in order to call image data having a size that cannot be output from the data storage means by a single data signal, Is generated in the buffer means by outputting the next address signal before the data acquisition time has passed since the output of, and acquiring the data signal based on the previous address signal after outputting the next address signal By reducing the transfer time for each page by the delay time, the transfer rate can be increased and the load on the image processing LSI can be reduced. By increasing the transfer speed, it becomes possible to transfer a larger amount of image data.

The display control device for a gaming machine according to claim 2 is a data storage means storing image data to be displayed on a display means provided in the gaming machine, and the display means reads out the image data by the data storage means. In a display control device for a gaming machine, comprising: an image processing LSI that outputs data to a buffer; and a buffer means disposed between the image processing LSI and the data storage means. An address signal for reading the image data stored at a predetermined address of the means is output, and at the same time or after the address signal is output, the read signal is enabled, and after the read signal is enabled, a predetermined effective time has elapsed. Based on the address signal after a predetermined data acquisition time has elapsed since the read signal was invalidated and the address signal was output. A data signal output from the data storage means is acquired, and the data storage means receives the image data stored at the predetermined address after the elapse of a predetermined data output time after acquiring the address signal as a data signal. And when the read signal is recognized as invalid, the data signal is also invalidated, and the buffer means obtains the address signal and the read signal output from the image processing LSI. When the predetermined delay time has elapsed, the address signal and the read signal are output to the data storage means, and when the data signal output by the data storage means is acquired, the image processing is performed after the delay time has elapsed since the acquisition. The data processing LSI is configured to output the data signal, and the image processing LSI is configured to output the data signal. When the address signal is output a plurality of times in succession in order to call up image data having a size that cannot be output from the storage means by a single data signal, the data acquisition time has passed since the address signal was output. The read signal is invalidated first by a time not exceeding twice the delay time, and a data signal based on the previous address signal is acquired after outputting the next address signal. According to the display control device for a gaming machine according to claim 2, if the time from when the image processing LSI switches the read signal to invalid until the data signal is acquired is shorter than the delay time generated by the buffer means, the data signal Since the address signal is output, the read signal is invalidated for a time that does not exceed twice the delay time before the data acquisition time elapses after the address signal is output, and the next address signal is output before the next address By acquiring the data signal based on the signal, the timing for switching the lead signal to invalid can be made slightly earlier than the display control device for gaming machines according to claim 1, and the next output from the image processing LSI similarly Since the address signal may be at the same time or after it is invalidated when the read signal is invalidated, the display control device for gaming machines according to claim 1 It can be quickly and can further enhance the transfer rate.

In a display control device for a gaming machine, when a buffer means is provided between the image processing LSI and the data storage means, the delay time that the image processing LSI generates in the buffer means is to increase the data transfer rate. This is achieved by outputting the next address signal before acquiring the data signal from the data storage means for a time not exceeding.

Embodiments of a display control apparatus for gaming machines according to the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic front view of a pachinko gaming machine 1 as an example of a gaming machine equipped with a display control device for gaming machines according to a first embodiment of the present invention. This pachinko gaming machine 1 is a so-called seven-machine type (first type) pachinko gaming machine, and includes a front door 2 made of a transparent glass plate attached to a frame, and a front door 2 arranged inside the frame. A game board 3 covered by the game board, a pair of speakers 4 arranged obliquely below the left and right of the game board 3, decoration lamps 5 arranged above the game board 3, and the like, and provided below the game board 3. The storage tray 6 and a firing handle 7 provided on the right side (as viewed in FIG. 1) of the storage tray 6 and provided with a firing stop button 71 are configured.

The gaming board 3 is planted on the gaming board 3, a gaming machine display device 10 disposed substantially at the center of the gaming board 3, a passing gate 11 provided on the left side of the gaming machine display device 10. A large number of the four nails 12 (illustrated in the drawing), a start winning device 13 which is a so-called electric tulip (hereinafter abbreviated as “electric chew”), and a large winning device 14 provided below the start winning device 13. , A ball drawing port 15 provided below the grand prize winning device 14, an ordinary (ordinary symbol) display unit 16 composed of an LED (Light Emitting Diode) arranged in the middle of the left edge of the game board 3, It is configured to include a universal figure holding display unit 17 composed of four LEDs arranged continuously below the diagram display unit 16.

The firing handle 7 is a rotational operation member having a firing stop button 71. When the firing handle 7 is rotated without pressing the firing stop button 71, the firing control circuit 150 (FIG. 2) outputs a rotational operation signal representing the rotational operation amount. Output). Note that when the firing stop button 71 is pressed, the rotation operation signal is not output regardless of the rotation operation amount of the firing handle 7.

The gaming machine display device 10 displays a special figure composed of characters such as three-digit Arabic numerals determined based on a lottery result of a special figure (special symbol) on the upper and lower two or one stage, and displays the special figure to the player. From a liquid crystal display device (corresponding to the display means of the present invention) 8 for notifying the lottery result, and a special figure (special symbol) holding display portion 9 composed of four LEDs arranged on the lower side of the window frame of the liquid crystal display device 8 It is configured.

The passing gate 11 is a gate without a prize ball, and when a ball is passed through the passing gate 11, a usual lottery process is performed. In the common figure display unit 16, symbol fluctuation (LED blinking operation) is performed based on the lottery result of the ordinary figure, and if it is lit and displayed after a predetermined time has passed, it becomes a hit, and the movable vanes of the start winning device 13 to be described later are held for a predetermined time Open. If a lottery process for a new symbol is performed while the symbol of the usual figure is changing or during the opening operation of the start winning device 13, the lottery result is temporarily stored (held), and the maximum number of the usual figure hold display units 17 is four. Lights up according to the number of lottery results that can be put on hold. When the previous symbol variation or release operation ends, the regular symbol display unit 16 starts a new symbol variation based on the reserved lottery result of the regular symbol.

The start winning device 13 is a variable winning device called a so-called electric chew having a pair of movable blades in the opening. The start winning device 13 opens the movable blade for a predetermined time when a win display is made on the normal display unit 16. When a ball wins the start winning device 13, a special drawing lottery process is performed. In the liquid crystal display device 8, symbol variation is performed based on a special drawing lottery result. Specifically, the three-digit symbols start to fluctuate at the same time, stop after a predetermined time has elapsed, and if three identical numbers are lined up, the jackpot is processed. If a lottery process for a new special figure is performed while the special figure is changing or the jackpot process, the lottery result is temporarily stored (held), and the special figure hold display unit 9 can hold up to four special figures. Lights up according to the number of lottery results. When the previous symbol variation or jackpot process ends, the liquid crystal display device 8 starts a new symbol variation based on the reserved special drawing lottery result.

The big winning device 14 is a variable winning device called a so-called attacker, and is composed of an opening and a lid member, and exhibits a closed state and an open state of the opening as the lid member moves. When winning the jackpot, the winning device 14 performs a process that continues for 15 rounds with one jackpot process, for example, 10 rounds after winning or closing after 25 seconds.

The ball discharge port 15 is opened at the lowermost part of the game board 3 and discharges the balls that have finished flowing down on the board surface of the game board 3 to the outside of the gaming machine.

Referring to FIG. 2, the pachinko gaming machine 1 includes a main control board 100 on which the main circuit 110 is mounted, a special figure hold display unit 9, a general figure display unit 16, and a general figure hold display unit 17 connected to the main circuit 110. A sub-control board on which a sub-control circuit 120 connected to the main circuit 110 and controlling the decorative lamps 5 and the amplifier 40 and the speaker 4 is mounted, and a display control connected to the sub-control circuit 120 to control the liquid crystal display device 8 A display control board on which a circuit 130 (corresponding to a display control device for gaming machines of the present invention) is mounted, a payout control board on which a payout control circuit 140 connected to the main circuit 110 and controls the payout device 141, and a payout A launch control board mounted with a launch control circuit 150 connected to the control circuit 140 and controlling the launch device 151 based on a rotation operation signal from the launch handle 7, and the passing gate 11 A gate passage detector 161 that is provided side by side and connected to the main circuit 110, a start prize detector 162 that is provided side by side and connected to the main circuit 110, and that is connected to the main prize circuit 14 and connected to the main circuit 110. A large prize detector 163, an electric Chu solenoid 166 that opens and closes the movable vanes of the start winning apparatus 13 that is connected to the main circuit 110 and is an electric chew, and a large prize solenoid that opens and closes the large prize apparatus 14 connected to the main circuit 110. 167 and a power supply circuit 168 that supplies a predetermined voltage to each substrate.

In addition, each board | substrate with which each circuit which controls the pachinko game machine 1 is mounted is arrange | positioned at the back side of the pachinko game machine 1, and the display control board with which the display control circuit 130 is mounted is the back side of the liquid crystal display device 8. Is arranged.

The main circuit 110 includes a central processing unit (CPU) 111, a read only memory (ROM) 112 for storing a program, a random access memory (RAM) 113 to which a work area, various counters, and the like are allocated, and an input / output (I / O). 114 and the like.

In addition, although each circuit of each other board | substrate is generally a structure provided with CPU and memory separately, it is abbreviate | omitting in FIG.

The sub control circuit 120 outputs sound from the speaker 4 through the amplifier 40 in accordance with the sound control signal input from the main circuit 110. The sub control circuit 120 controls the lighting / extinguishing of the decorative lamps 5 in accordance with the lamp control signal input from the main circuit 110.

The payout control circuit 140 controls the payout device 141 according to the prize ball payout signal input from the main circuit 110 and causes the storage tray 6 to pay out a predetermined number of prize balls.

The firing control circuit 150 activates the launching device 151 in accordance with the rotation operation of the launch handle 7 by the player. According to the rotation operation amount of the firing handle 7, it is possible to adjust the ball firing strength (ball flight distance) by the launching device 151. The ball fired from the launching device 151 is released onto the game board 3 and flows down by its own weight.

The display control circuit 130 executes a process for displaying an image on the liquid crystal display device 8 in accordance with the display control command input from the sub control circuit 120.

FIG. 3 is a circuit block diagram showing the configuration of the display control circuit 130. The display control circuit 130 includes a display control CPU 131, a program ROM 133 connected to the display control CPU 131 via the first bus 132, and a VDP connected to the display control CPU 131 via the first bus 132 (present invention). 134, a character ROM 136 connected to the VDP 134 via a second bus 135 and a level shifter (corresponding to the buffer means of the present invention) 200, and a VDP 134 via the second bus 135. A VRAM (Video Random Access Memory) 137 and an interface circuit (I / F) 138 connected to the VDP 134 are provided.

The program ROM 133 stores a control program including program codes and various parameters. For example, when a 32-128 Mbit ROM is used as the program ROM 133, the program code is about several hundred kilobits and the rest are various parameters.

The character ROM 136 stores compressed image data such as symbols and characters corresponding to display contents.

The VRAM 137 is a memory for developing symbols and characters in the frame buffer.

The display control CPU 131 has its own RAM (not shown), and executes a control program stored in the program ROM 133 based on a display control command from the sub-control circuit 120. Specifically, the display control CPU 131 analyzes the contents of the display control command received from the sub-control circuit 120 according to the control program stored in the program ROM 133, and reads out various necessary parameters from the program ROM 133 based on the analysis result. A screen information (display list) that summarizes the code, address (display position), rotation, enlargement / reduction, display order, etc. of each image (design or character) to be displayed on the screen for one frame is calculated to create the VDP 134. To send. Further, the display control CPU 131 transmits information necessary for processing of the VDP 134, such as the resolution of the liquid crystal display device 8, information about the dot clock, and information about the read timing to the character ROM 136, to the VDP 134.

The VDP 134 reads the compressed image data from the character ROM 136 according to the screen information (display list), draws it in the frame buffer on the VRAM 137, creates an image for one frame, and outputs it as a digital RGB signal to the interface circuit 138. . Specifically, the VDP 134 reads out and decompresses the necessary symbols and characters from the character ROM 136 storing the symbols and characters according to the screen information (display list), and reads the addresses and display colors of the dots of the symbols and characters that have been read out. , Rotation, enlargement and reduction are calculated based on the screen information (display list), and the calculation result is developed in the frame buffer on the VRAM 137. Subsequently, the VDP 134 sends a digital RGB signal to the interface circuit 138 based on the image for one frame developed in the VRAM 137. The VRAM 137 may be built in the VDP 134.

FIG. 4 is a principal block diagram showing an aspect in which an address level shifter 200a and a data level shifter 200b are connected between a 3.3V drive VDP 134 and a 1.8V drive character ROM 136. FIG. The level shifters 200a and 200b are arranged between the VDP 134 and the character ROM 136 having different voltages, and convert the voltage level of the connected signals. Specifically, the VDP 134 reads the image data stored at a predetermined address of the character ROM 136 in accordance with the screen information (display list), and sends a 3.3V level address signal Address (1) indicating the address to the level shifter 200a. Output. The level shifter 200a outputs to the character ROM 136 an address signal Address (2) obtained by reducing the voltage level of the address signal Address (1) to 1.8V level. As a result, the character ROM 136 outputs a 1.8V level data signal Data (3) indicating the data stored at the predetermined address of the character ROM 136 to the level shifter 200b based on the address signal Address (2). The level shifter 200b outputs the data signal Data (4) obtained by boosting the voltage level of the data signal Data (3) to the 3.3V level to the VDP 134 (the VDP 134 can acquire the data signal Data (4)).

Here, data transmission / reception between the VDP and the ROM in the conventional display control apparatus for gaming machines will be described again in detail with reference to FIG. Between the VDP and the ROM, the wiring for transmitting the read, address, and data signals shown in FIG. 6 and the wiring for transmitting the CS (chip select) signal are also connected. In addition, when data having a size of 32 bits or more is read while the data bus between the VDP and the ROM is connected with a 32-bit width, for example, the VDP divides the data into a plurality of 32-bit pages, and the first page The address signal is output in order and the data signal is received.

The VDP first validates the CS (chip select) signal to the ROM from which data is acquired, and simultaneously outputs an address signal indicating the address where the data of the first page is stored to the ROM, and reads it several ns later. Enable the (Read) signal. The CS signal, the address signal, and the read signal output from the VDP are output to the ROM with a delay time of 5 ns through a level shifter that is a buffer means. The ROM reads the data stored in the address based on the CS signal and the address signal into its own buffer, and outputs the data signal 102.5 ns (corresponding to the data output time of the present invention) after receiving the address signal. To do. The data signal output from the ROM is output to the VDP again with a delay time of 5 ns by passing through a level shifter which is a buffer means. Since the data signal can be acquired thereafter, the VDP acquires the data signal when 115 ns (corresponding to the data acquisition time of the present invention) elapses after the output of the address signal. Thereafter, the VDP invalidates the read signal based on the elapse of a predetermined valid time (corresponding to the valid time of the present invention) after outputting the address signal, and then outputs the address signal for the next page. Therefore, the read time which is the time from the output of the first address signal to the output of the next address signal is set to 120 ns. In addition, since the ROM outputs a data signal after 22.5 ns (corresponding to the data output time of the present invention) after the address signal is output for the second and subsequent pages, the read time for the second and subsequent pages is a delay time in the level shifter. Is set to 40 ns (data acquisition time is 35 ns).

The data signal output to the VDP is valid for a while after the VDP acquires the data signal, but originally becomes invalid at the same time as the read signal from the VDP becomes invalid. However, this read signal is also delayed by 5 ns between VDP and ROM, and the data signal output from the level shifter to VDP becomes invalid 5 ns after the data signal output from ROM becomes invalid. The data signal output to the VDP is valid for 10 ns after switching the signal to invalid.

FIG. 5 is a timing chart showing data transmission / reception between the VDP 134 and the character ROM 136 in the gaming machine display control apparatus according to the first embodiment. Since the character ROM 136 of the first embodiment is not changed from the conventional display control device for gaming machines, it takes from the time when the character ROM 136 acquires the address signal Address (2) to the time when the data signal Data (3) is output. The time (corresponding to the data output time of the present invention) is 102.5 ns for the first time (first page) and 22.5 ns for the second time (second page) and thereafter, as in the conventional display control device for gaming machines. The time from when the VDP 134 outputs the address signal Address (1) until the data signal Data (4) is acquired (corresponding to the data acquisition time of the present invention) is the same as that of the conventional display control device for gaming machines.

The VDP 134 of the first embodiment outputs the next address signal Address (1) before acquiring the data signal Data (4) corresponding to the previous address signal Address (1). In the conventional display control device for gaming machines, the data signal Data (4) corresponding to the output address signal Address (1) is acquired and then the next address signal Address (1) is output. 1 VDP 134 outputs the next address signal Address (1) earlier than the conventional display control device for gaming machines by a round-trip delay time (10 ns) generated from address output to data acquisition, After 5 ns, the data signal Data (4) of the address signal Address (1) output previously is acquired. This is because the read signal is switched to invalid before the next address signal Address (1) is output, but the data signal Data (4) is invalidated along with the delay time in the level shifters 200a and 200b. Therefore, if the data signal Data (4) is in a valid period, the VDP 134 outputs the next address signal Address (1) even after outputting the next address signal Address (1). It is based on the fact that it is possible to acquire the data signal Data (4) corresponding to.

Therefore, the read time of the first page, which is the time from the output of the first address signal Address (1) to the output of the next address signal Address (1), is 110 ns, which is 10 ns shorter than the conventional display control device for gaming machines. The lead time for the second and subsequent pages is 30 ns, which is 10 ns shorter than the conventional display control device for gaming machines. In other words, the VDP 134 according to the first embodiment can read data from the character ROM 136 in a time shorter by approximately the number of pages × 10 ns than the conventional display control device for gaming machines. (To be precise, the VDP of the conventional display control device for gaming machines has acquired the last data 5 ns ahead of the end of the last read time, and the VDP 134 of the first embodiment has finished the last read time. (Since the last data is acquired 5 ns after, the time that can be shortened is the number of pages × 10 ns-10 ns.)

According to the first embodiment, it is possible to increase the transfer rate and reduce the load on the VDP 134 by shortening the read time in units of one page by the delay time generated in the level shifters 200a and 200b. Further, by increasing the transfer speed, it becomes possible to transfer a larger amount of image data.

Here, taking the case of a bus width of 32 bits as an example, the transfer rates of the conventional display control device for gaming machines and the display control device for gaming machines according to the first embodiment are compared.

When data transfer for 8 pages (32 bits x 8 = 32 bytes) is performed, with a conventional display control device for gaming machines, the transfer time is 120 ns + 40 ns x 7-5 ns = 395 ns, and the transfer rate is 32 bytes / 395 ns = 81 Mbytes. On the other hand, in the display control device for gaming machines according to the first embodiment, the transfer time is 110 ns + 30 ns × 7 + 5 ns = 325 ns, the transfer rate is 32 bytes / 325 ns = 98 Mbyte / s, and the transfer rate is about 20% up.

In addition, when data transfer of 1000 pages (32 bits × 1000 = 4 Kbytes) is performed, in the conventional display control device for gaming machines, the transfer time is 120 ns + 40 ns × 999-5 ns = 40075 ns, and the transfer rate is 4 Kbytes / 40075 ns = In contrast to the 100 Mbyte / s, in the display control device for gaming machine according to the first embodiment, the transfer time is 110 ns + 30 ns × 999 + 5 ns = 30085 ns, the transfer rate is 4 Kbytes / 30085 ns = 133 Mbyte / s, and the transfer rate Increases by about 33%.

By increasing the transfer rate in this way, the transfer time can be shortened or a large amount of data can be transferred per unit time, so the load on data transfer can be reduced and the load on other processing can be directed. Become.

If the time from when the VDP 134 switches the read signal to invalid until the data signal Data (4) is acquired is shorter than the delay time (10 ns) generated in the level shifter 200, the data signal Data (4) can be acquired. The timing for switching the read signal to invalid can be made a little earlier than that of the first embodiment. Similarly, the next address signal Address (1) output from the VDP 134 may be simultaneously or invalidated when the read signal is invalidated. Therefore, it can be made a little faster than the first embodiment, and the transfer rate can be further increased.

In the first embodiment, the display device is the liquid crystal display device 200. However, a PDP (Plasma Display Panel), an organic EL (Electroluminescence), an SED (Surface-conduction Electron-emitter Display), a CRT (Cathode Ray Tube), etc. Of course, other display devices may be used.

As described above, the first embodiment of the present invention has been described. However, this is merely an example, and the present invention is not limited to this, and the knowledge of those skilled in the art can be obtained without departing from the scope of the claims. Various modifications based on this are possible.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic front view of a pachinko gaming machine as an example of a gaming machine equipped with a gaming machine display control device according to Embodiment 1 of the present invention. A circuit block diagram of a pachinko gaming machine. The circuit block diagram of a display control board. The principal part block diagram which shows the level shifter in FIG. 3 and its front and back in detail. 3 is a timing chart showing data transmission / reception between the VDP and the character ROM in the display control device for a gaming machine according to the first embodiment. The timing chart showing the data transmission / reception between VDP and character ROM in the conventional display control apparatus for game machines.

Explanation of symbols

1 Pachinko machine (game machine)
8 Liquid crystal display device (display device)
DESCRIPTION OF SYMBOLS 10 Display device 100 for game machines Main control board 110 Main circuit 120 Sub control circuit 130 Display control circuit 131 Display control CPU
132 1st bus 133 Program ROM
134 VDP (LSI for image processing)
135 Second bus 136 Character ROM (data storage means)
137 VRAM
138 Interface circuit 200, 200a, 200b Level shifter (buffer means)

Claims (2)

Data storage means for storing image data to be displayed on display means provided in the gaming machine, an image processing LSI for reading out image data by the data storage means and outputting it to the display means, and for the image processing In a display control apparatus for a gaming machine comprising a buffer means disposed between an LSI and the data storage means,
The image processing LSI outputs an address signal for reading image data stored at a predetermined address of the data storage means, and based on the address signal after a predetermined data acquisition time has elapsed since the output of the address signal. Configured to acquire a data signal output from the data storage means,
The data storage means is configured to output the image data stored at the predetermined address as a data signal after a predetermined data output time has elapsed since the acquisition of the address signal.
When the buffer unit acquires the address signal output by the image processing LSI, the buffer unit outputs the address signal to the data storage unit after a predetermined delay time has elapsed since the acquisition, and the data storage unit outputs the address signal. When the data signal is acquired, the data signal is configured to be output to the image processing LSI after the delay time has elapsed since acquisition.
The image processing LSI outputs the address signal after outputting the address signal a plurality of times in order to call image data of a size that cannot be output from the data storage means by a single data signal. A display control device for a gaming machine, wherein a next address signal is output before a data acquisition time elapses, and a data signal based on the previous address signal is acquired after the next address signal is output. Data storage means for storing image data to be displayed on display means provided in the gaming machine, an image processing LSI for reading out image data by the data storage means and outputting it to the display means, and for the image processing In a display control apparatus for a gaming machine comprising a buffer means disposed between an LSI and the data storage means,
The LSI for image processing outputs an address signal for reading image data stored at a predetermined address of the data storage means, validates the read signal simultaneously with or after outputting the address signal, and outputs the read signal. The read signal is invalidated after elapse of a predetermined valid time after being enabled, and a data signal output from the data storage means is acquired based on the address signal after elapse of a predetermined data acquisition time after outputting the address signal. Configured to
The data storage means outputs the image data stored at the predetermined address as a data signal after a predetermined data output time elapses after acquiring the address signal, and when the read signal is recognized as invalid, the data signal Is also configured to be invalid,
When the buffer means acquires the address signal and read signal output from the image processing LSI, the buffer means outputs the address signal and read signal to the data storage means after a predetermined delay time has elapsed since the acquisition, When the data signal output by the storage means is acquired, the data signal is output to the image processing LSI after the delay time has elapsed since acquisition,
The image processing LSI outputs the address signal after outputting the address signal a plurality of times in order to call image data of a size that cannot be output from the data storage means by a single data signal. The read signal is invalidated for a time not exceeding twice the delay time before the data acquisition time elapses, and a data signal based on the previous address signal is acquired after outputting the next address signal. A display control device for gaming machines.

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