JP2008218468A - Three-dimensional integrated circuit device and manufacturing method thereof - Google Patents

Three-dimensional integrated circuit device and manufacturing method thereof Download PDF

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JP2008218468A
JP2008218468A JP2007049628A JP2007049628A JP2008218468A JP 2008218468 A JP2008218468 A JP 2008218468A JP 2007049628 A JP2007049628 A JP 2007049628A JP 2007049628 A JP2007049628 A JP 2007049628A JP 2008218468 A JP2008218468 A JP 2008218468A
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thin film
film semiconductor
semiconductor layer
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Takashi Noguchi
隆 野口
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Univ Of Ryukyus
国立大学法人 琉球大学
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<P>PROBLEM TO BE SOLVED: To provide a three-dimensional integrated circuit device having a thin-film semiconductor layer formed on a glass substrate. <P>SOLUTION: The three-dimensional integrated circuit device 10 has a structure in which a plurality of single crystal or semi-single crystal thin-film semiconductor layers 13, 16 are formed on the glass substrate 11 via an interlayer insulating layer 14, and active elements Tr21, Tr22 are formed on one or more layers of the thin-film semiconductor layers 13, 16. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a three-dimensional integrated circuit device and a manufacturing method thereof.

In an integrated circuit device such as an LSI, it is desired to realize a new function and to achieve high integration.
Therefore, an alternative method is being studied for miniaturization according to the scaling law (proportional reduction) that has been conventionally performed.

  In the SRAM cell, as a structure realizing high integration, a basic memory cell is constituted by TFT (thin film transistor) made of polycrystalline silicon (polysilicon), and is three-dimensionally formed on an LSI integrated on a conventional silicon wafer. A so-called TFT stack type structure has been proposed which is stacked on the substrate and highly integrated.

However, this TFT stack type structure has a problem of manufacturing cost and a variation in element characteristics of a fine polycrystalline silicon TFT.
Therefore, returning to the conventional planar two-dimensional CMOS bulk structure, integration is being promoted by a miniaturization technique depending on photography.

  Recently, there has been an increasing demand for further reduction in operating voltage and higher density, and there is a demand for a method for integrating high-performance TFTs with little characteristic variation and equivalent to single crystals at higher density. .

On the other hand, as an application of a TFT to a flat display or the like, a technique for manufacturing a TFT on a panel on glass has been rapidly advanced.
In this field, as in the case of LSI, miniaturization, high performance, and realization of system functions are required, including development of new manufacturing processes.
In addition to a pixel and a peripheral circuit as a display, various functional systems such as a sensor, a memory, an A / D converter, a D / A converter, and a CPU are integrated on a single glass substrate. Aiming at “System on Glass”, research and development based on silicon TFT by low-temperature formation process is progressing.

When a TFT is formed on a silicon substrate or an SOI (Silicon on insulator) substrate, since a silicon wafer is used, the substrate is opaque and the area is limited to the size of the wafer or less.
Instead, a process of 1,000 ° C. or higher is possible during manufacturing, and an insulating film (oxide film) can be formed by thermal oxidation. In addition, since the wafer is a silicon single crystal, it is easy to make a crystal and epitaxy is easy.

On the other hand, when a TFT is formed over a glass substrate, the glass is transparent and can have a large area, and the integrated circuit device can have a flexible configuration.
However, high-temperature processes cannot be performed during production, and crystals are difficult to produce because the substrate is glass.

As a three-dimensional structure on the glass substrate, a three-dimensional non-volatile dot TFT memory array on the glass substrate and a three-dimensional 1T1C (one transistor and one capacitor) TFT array by realizing a ferroelectric film by a pulse laser in the ultraviolet region are proposed. Has been.
However, in this structure, since the silicon thin film on which an active element such as a transistor is formed is only one layer, further integration is difficult.

By the way, an amorphous thin film semiconductor layer has good film formability but cannot be heated.
Further, the mobility of carriers such as electrons is low in the amorphous layer. Therefore, the transistors that can be formed in the amorphous layer are limited to those that do not require high-speed operation such as switching.
Therefore, in order to form a TFT that requires high-speed operation, the thin film semiconductor layer needs to be crystallized. Whether to form a crystalline thin film semiconductor layer or a process for crystallizing an amorphous thin film semiconductor layer? Either method will be adopted.

As a method for forming a silicon crystal thin film on a glass substrate, a method is proposed in which two amorphous silicon thin film layers are deposited on a SiO 2 substrate and crystallized by irradiation with a solid YAG laser (Non-patent Document 1). reference).
By this method, the upper silicon layer is efficiently crystallized, so that a polycrystalline thin film is formed only by the upper silicon layer, and TFT characteristics with high mobility can be obtained.

When a CMOS transistor is formed on a glass substrate, a polysilicon (polycrystalline silicon) TFT is the only possible configuration at present.
And in this polysilicon TFT, the mobility of the conductive carrier which influences a characteristic has been improved by increasing a crystal grain (for example, refer patent document 1).

Crystallization of Double-Layered Silicon Thin Films by Solid Green Laser Annealing, T. Sugawara, Y. Uraoka, T. Hayama, T. Fuyuki and A. Miura, Digest of Tech. Papers, AM-FPD'06, 8.4, p. 317 (2006) JP 11-87545 A

However, in principle, the polysilicon TFT has a problem that the characteristics of the element become non-uniform as the element becomes finer due to large polycrystalline grains.
In particular, in order to lower the operating voltage, it is necessary to make the element small, and the influence of variations in element characteristics increases.

In addition, the method described in Non-Patent Document 1 has an advantage that the crystallization process is simple because laser crystallization is performed at a time after forming a two-layer thin film. Since laser crystallization is performed at a time after the formation, the lower silicon layer is not sufficiently crystallized.
Therefore, even if an active element is formed on the lower silicon layer, there is a possibility that sufficiently good element characteristics cannot be obtained.

As another method for forming a plurality of thin film semiconductor layers, there is a method in which two wafers each having one or more thin film semiconductor layers are prepared and bonded together.
However, this method is difficult to mass-produce and the manufacturing cost is high.

  In order to solve the above-described problems, the present invention provides a three-dimensional integrated circuit device in which a thin film semiconductor layer is formed on a glass substrate and a method for manufacturing the same.

  In the three-dimensional integrated circuit device of the present invention, a single-crystal or quasi-single-crystal thin film semiconductor layer is stacked on a glass substrate via an interlayer insulating layer, and one or more of the plurality of thin film semiconductor layers In this thin film semiconductor layer, an active element is formed.

  The method for manufacturing a three-dimensional integrated circuit device according to the present invention includes a step of forming an amorphous first thin film semiconductor layer on a glass substrate having an insulating layer formed on the surface, and the amorphous first thin film semiconductor layer. A step of crystallizing the layer to form a single-crystal or quasi-single-crystal first thin-film semiconductor layer, and forming an interlayer insulating layer on the first thin-film semiconductor layer; A step of forming an opening reaching one thin film semiconductor layer, a step of epitaxially growing a semiconductor epitaxial layer in the opening of the interlayer insulating layer, and an amorphous second layer thin film semiconductor on the interlayer insulating layer and the semiconductor epitaxial layer A step of forming a layer, and a step of crystallizing the amorphous second thin film semiconductor layer to form a single crystal or quasi-single crystal second thin film semiconductor layer, A plurality of thin film semiconductor layers including one thin film semiconductor layer and a second thin film semiconductor layer are stacked via an interlayer insulating layer, and one or more thin film semiconductors among the plurality of thin film semiconductor layers are formed. An active element is formed in the layer.

According to the above-described configuration of the three-dimensional integrated circuit device of the present invention, the plurality of thin film semiconductor layers are formed of a single crystal or a quasi-single crystal. Active elements such as transistors formed in the thin film semiconductor layer can be operated at high speed.
In addition, compared to a conventionally proposed configuration in which a thin film semiconductor layer is formed of polysilicon (polycrystalline silicon), there is almost no variation in the characteristics of active elements such as transistors due to polycrystalline silicon grain boundaries. Is possible.
Since a plurality of thin film semiconductor layers are formed, the area occupied by each circuit element and the connection portion between the circuit elements can be reduced, so that circuit elements can be integrated at high density. .

  Therefore, it is possible to realize an integrated circuit device having high-performance active elements that operate at high speed and integrated at high density.

  According to the manufacturing method of the above-described three-dimensional integrated circuit device of the present invention, in the crystallization process of the amorphous second thin film semiconductor layer, the semiconductor epitaxial layer is used as a seed and melt crystallization is performed in the lateral direction (film surface direction). Thus, the thin film semiconductor layer of the second layer can be a single crystal or a quasi-single crystal in a good state.

  Therefore, the manufacturing method of the present invention makes it possible to manufacture an integrated circuit device having high-performance active elements that have high mobility of conductive carriers in the thin film semiconductor layer and operate at high speed.

As an embodiment of the present invention, a schematic configuration diagram (cross-sectional view) of a three-dimensional integrated circuit device is shown in FIG.
In the three-dimensional integrated circuit device 10, an integrated circuit having a three-dimensional structure is formed on a glass substrate 11.

As shown in FIG. 1, a first thin film semiconductor layer 13 is formed on a glass substrate 11 via a protective layer 12 for protecting glass, and on the first thin film semiconductor layer 13, The insulating layer 14 covers it.
An opening reaching the first thin film semiconductor layer 13 is formed in the insulating layer 14, and the semiconductor epitaxial layer 15 is filled in the opening.
A second thin-film semiconductor layer 16 is formed on the insulating layer 14 and the semiconductor epitaxial layer 15 in the opening.
That is, the insulating layer 14 is formed as an interlayer insulating layer between the two thin film semiconductor layers 13 and 16.

Thin film transistors Tr21 and Tr22 are formed in the second thin film semiconductor layer 16. That is, the channel 31 and the source / drain regions 32 and 33 of the thin film transistors Tr 21 and Tr 22 are formed in the second thin film semiconductor layer 16.
In the thin film transistors Tr21 and Tr22, the insulating layer 17 formed on the second thin film semiconductor layer 16 is removed.
A gate 20 is formed on the second thin film semiconductor layer 16 of the channel 31 via a gate insulating layer 19. An insulating layer 21 is formed to cover the gate 20, and an electrode layer 18 connected to the source / drain regions 33 of the thin film transistors Tr 21 and Tr 22 is formed between the insulating layer 21 and the insulating layer 17.

In the first thin film semiconductor layer 13, active elements such as transistors or diodes and other circuit elements are formed in a portion not shown.
The second thin film semiconductor layer 16 may also be formed with active elements such as thin film transistors or diodes and other circuit elements in addition to the thin film transistors Tr21 and Tr22 of FIG.

As the protective layer 12 for protecting the glass substrate 11, for example, a SiO 2 layer, a SiN layer, and a layer obtained by stacking these layers can be used.

  In the three-dimensional integrated circuit device 10 according to the present embodiment, the first thin film semiconductor layer 13 and the second thin film semiconductor layer 16 are particularly formed of a single crystal or a quasi-single crystal. .

  The term “quasi-single crystal” refers to crystal grains that have a certain preferred crystal plane orientation, are regularly arranged in a position, are composed of crystal grains having a substantially uniform size in terms of electron conduction, and are adjacent to each other. The boundaries are preferentially arranged in a certain direction to match each other, and since the defect density at the grain boundaries is reduced, the electron conduction is superior to the conventional polycrystalline phase thin film, which can be artificially realized. An energy metastable crystalline phase (specifically, literature; Possibility of Quasi-Single-Crystalline Semiconductor Films, T. Noguchi, S. Usui, DP Gosainand Y. Ikeda, Mat. Res. Soc. Symp. Vol.557, p.213 (1999).).

  Compared with the conventionally proposed configuration in which the thin film semiconductor layers 13 and 16 are formed of single crystal or quasi-single crystal, the thin film semiconductor layer is formed of polysilicon (polycrystalline silicon). Variations in characteristics of active elements such as transistors due to silicon crystal grain boundaries can be almost eliminated.

Next, as an application example of the three-dimensional integrated circuit device of FIG. 1, a circuit configuration diagram of an SRAM cell configured using the two transistors Tr21 and Tr22 of FIG. 1 is shown in FIG.
This SRAM cell has six transistors Tr11, Tr12, Tr13, Tr14, Tr21, Tr22.
These six transistors Tr11, Tr12, Tr13, Tr14, Tr21, Tr22 are all formed as thin film transistors (TFTs) on the thin film semiconductor layers 13, 16.
One of the source / drain regions of the lower two transistors Tr11 and Tr12 is connected to the ground potential.
The potential Vdd is supplied to one of the source / drain regions of the upper two transistors Tr21 and Tr22.
The other of the source / drain regions of the two left transistors Tr11 and Tr21 is connected to one of the gates of the two right transistors Tr12 and Tr22 and the source / drain region of the transistor Tr13.
The other of the source / drain regions of the right two transistors Tr12, Tr22 is connected to one of the gates of the left two transistors Tr11, Tr21 and the source / drain region of the transistor Tr14.
The other of the source / drain regions of the transistor Tr13 is connected to the bit line BL.
The gates of the two outer transistors Tr13 and Tr14 are connected to the word line WL.
The connection relationship of the six transistors Tr11, Tr12, Tr13, Tr14, Tr21, Tr22 is the same as that of a general SRAM cell formed in a bulk semiconductor layer.

In the SRAM cell shown in FIG. 2, four transistors Tr11, Tr12, Tr13, Tr14 are formed in the first thin film semiconductor layer 13, and two transistors Tr21, Tr22 are formed in the second thin film semiconductor layer 16. Has been.
As described above, by dividing the six TFTs into the two thin film semiconductor layers 13 and 16, the area occupied by the SRAM cell can be reduced as compared with the case where all the TFTs are formed in one thin film semiconductor layer. Therefore, it is possible to integrate SRAM cells with higher density.

FIG. 2 shows the case where the three-dimensional integrated circuit device 10 shown in FIG. 1 is applied to an SRAM cell. However, the three-dimensional integrated circuit device 10 shown in FIG. 1 is applied to various other devices. Is possible.
For example, the present invention can be applied to a pixel portion and a peripheral circuit portion of a flat panel display (FPD) such as a liquid crystal display.
Further, for example, it is also possible to configure a sensor or an imaging device (such as a CMOS imaging device) that receives light from the glass substrate 11 into the thin film semiconductor layer 13 and receives and detects the incident light.

Next, a method for manufacturing the three-dimensional integrated circuit device 10 shown in FIG. 1 will be described with reference to FIGS. 3A to 3E.
3A to 3E, the glass substrate 11 and the protective layer 12 are shown in an integrated manner in order to simplify the drawings.

First, as shown in FIG. 3A, a first thin film semiconductor layer 13 is formed on a glass substrate 11 having a protective layer 12 formed on the surface.
Although not shown, the first thin film semiconductor layer 13 is formed as an amorphous thin film semiconductor layer and then crystallized to form a single crystal or quasi-single crystal thin film semiconductor layer.

As a method for forming the amorphous thin film semiconductor layer, a method capable of forming a film at a low temperature that does not affect the glass substrate 11 is employed.
Examples of methods that can be used for film formation at low temperatures include (1) a method in which a film is formed by PE CVD (plasma CVD) and then a dehydrogenation process is performed at 300 ° C. to 400 ° C., and (2) sputtering is performed at room temperature. And a method of forming a film.
As a method for crystallizing the amorphous thin film semiconductor layer, ELA (excimer laser annealing) or ultraviolet irradiation can be considered.

  The amorphous thin film semiconductor layer is irradiated with a linear or planar ultraviolet beam (for example, an excimer laser or a solid laser) in a pulsed manner, and is crystallized to obtain a specific orientation, for example, (100 ) It is possible to form single crystals or quasi-single crystals whose crystal plane is the preferred orientation. When a linear ultraviolet beam is used, the ultraviolet beam is scanned to crystallize a wide area.

  Thereafter, although not shown, a TFT gate is formed on the first thin film semiconductor layer 13 or a TFT channel and source / drain regions are formed in the first thin film semiconductor layer 13 as necessary. Or form.

Next, as shown in FIG. 3B, an insulating layer 14 is formed on the crystallized first thin film semiconductor layer 13. At this time, the gate of the TFT formed on the first thin film semiconductor layer 13 is covered with the insulating layer 14.
Subsequently, as shown in FIG. 3C, etching is performed on a part of the insulating layer 14 to form an opening 14 </ b> A reaching the first thin film semiconductor layer 13.

Next, the semiconductor epitaxial layer 15 is grown from the first thin film semiconductor layer 13 exposed in the opening 14A by filling the opening of the insulating layer 14 by epitaxial growth.
For example, a silicon epitaxial layer is epitaxially grown as the semiconductor epitaxial layer 15 at about 450 ° C. by a UHV (ultra-high vacuum) CVD method using Si 2 H 6 gas.
Note that epitaxial growth may be performed by MBE (molecular beam epitaxy) instead of UHV CVD.
Thereafter, if necessary, the surface is planarized by, for example, a CMP (Chemical Mechanical Polishing) method.

Next, a second thin film semiconductor layer 16 is formed on the insulating layer 14 and the semiconductor epitaxial layer 15.
Although not shown, the second thin film semiconductor layer 16 is first formed into an amorphous thin film semiconductor layer and then crystallized to form a single crystal or quasi-single crystal thin film semiconductor layer. As the film forming method and the crystallization method, the method described in the step of forming the first thin film semiconductor layer 13 can be employed.
In particular, since the semiconductor epitaxial layer 15 is present in the lower layer, the second thin film semiconductor layer 16 can be a good single crystal or quasi-single crystal.

After forming the second thin film semiconductor layer 16, the TFT gate 20, channel 31, source / drain regions 32 and 33, insulating layer 17, wiring layer 18, insulating layer 21 and the like shown in FIG. Form.
In this way, the three-dimensional integrated circuit device 10 shown in FIG. 1 can be manufactured.

  With the above manufacturing method, a single-crystal or quasi-single-crystal semiconductor layer can be formed stepwise by a low-temperature process (≦ 500 ° C.).

Note that in the case where a silicon layer is formed as the first thin film semiconductor layer 13 or the second thin film semiconductor layer 16, the wavelength of ultraviolet rays irradiated for amorphous crystallization should be 380 nm or less. desirable.
When the wavelength is 380 nm or less in this way, absorption in silicon increases, and ultraviolet rays do not enter the back of the silicon layer. For this reason, it becomes difficult to transmit heat to a glass substrate, and the deformation | transformation by the heat of a glass substrate, etc. can be prevented.

  In particular, when the first thin film semiconductor layer 13 and the second thin film semiconductor layer 16 are 100 nm or less in thickness, ultraviolet irradiation is suitable for amorphous crystallization.

In addition, when irradiating an amorphous semiconductor layer with ultraviolet rays, it is desirable to irradiate the semiconductor layer in a pulse form rather than continuous irradiation. By irradiating the ultraviolet rays in the form of pulses, it becomes difficult for heat to be transmitted to the glass substrate, and deformation of the glass substrate due to heat can be prevented.
The pulse width of the pulsed ultraviolet light is preferably 1000 nsec (nanoseconds) or less.

  In the manufacturing method described above, an element such as a transistor is formed on the first thin film semiconductor layer 13 and then the second thin film semiconductor layer 16 is formed. However, the second thin film semiconductor layer 16 is formed. After that, an element may be formed in the first thin film semiconductor layer 13.

According to the present embodiment described above, since the two thin film semiconductor layers 13 and 16 are formed of a single crystal or a quasi-single crystal, the mobility of the conductive carriers can be increased, so that the thin film semiconductor Active elements such as the transistors Tr21 and Tr22 formed in the layers 13 and 16 can be operated at high speed.
In addition, compared to a conventionally proposed configuration in which a thin film semiconductor layer is formed of polysilicon (polycrystalline silicon), there is almost no variation in the characteristics of active elements such as transistors due to polycrystalline silicon grain boundaries. Is possible.

Further, according to the above-described manufacturing method, after the first thin film semiconductor layer 13 is formed by crystallization of the amorphous layer, the insulating layer 14 is formed on the first thin film semiconductor layer 13, and this insulating layer The semiconductor epitaxial layer 15 is epitaxially grown in the openings 14, and the second thin film semiconductor layer 16 is formed on the insulating layer 14 and the semiconductor epitaxial layer 15.
Thereby, in the crystallization process of the amorphous layer when forming the second thin film semiconductor layer 16, melt crystallization occurs in the lateral direction (film surface direction) using the semiconductor epitaxial layer 15 as a seed. The thin film semiconductor layer 16 can be a single crystal or quasi-single crystal in a good state.

In the above-described embodiment, the thin film semiconductor layer is the two layers 13 and 16, but the present invention includes the case where the thin film semiconductor layer is three or more layers.
In particular, between the second thin film semiconductor layer and the third thin film semiconductor layer, between the third thin film semiconductor layer and the fourth thin film semiconductor layer,. By connecting the semiconductor epitaxial layers in the formed openings, three or more single-crystal or quasi-single-crystal thin-film semiconductor layers can be formed, and further integration can be achieved.

  Note that the three-dimensional integrated circuit device of the present invention has a structure in which a plurality of single-crystal or quasi-single-crystal thin-film semiconductor layers (that is, two or more layers) are formed on a glass substrate. In some cases, a polycrystalline or amorphous thin film semiconductor layer may be included in addition to a plurality of single crystal or quasi-single crystal thin film semiconductor layers.

In the above-described embodiment, the case where the first thin film semiconductor layer 13 and the second thin film semiconductor layer 16 are silicon layers has been mainly described. However, the present invention can use other semiconductor layers. It is.
Examples of other semiconductor layers include a Ge (germanium) layer, a SiGe layer, and a compound semiconductor layer (GaAs, ZnS, etc.).

Here, for example, a manufacturing method in the case where the first thin film semiconductor layer 13 is a silicon layer and the second thin film semiconductor layer 16 is a germanium layer will be described.
In this case, since the first thin film semiconductor layer 13 and the second thin film semiconductor layer 16 are made of different materials, a method for forming the semiconductor epitaxial layer 15 is devised.

First, the silicon layer of the single-layer or quasi-single-crystal thin film semiconductor layer 13 is formed by the method described above.
Next, after an insulating layer 14 is formed on the first thin film semiconductor layer 13, an opening reaching the first thin film semiconductor layer 13 is formed in the insulating layer 14.

Next, the semiconductor epitaxial layer 15 is selectively epitaxially grown in the opening of the insulating layer 14.
At this time, a gas such as GeH 4 (germane) gas is added simultaneously with the SiH 4 gas or Si 2 H 6 gas, and the flow rate ratio of the GeH 4 gas is gradually increased as the semiconductor epitaxial layer 15 is grown. . Thereby, from the lower side, epitaxy is continuously generated in the vertical direction of Si → SiGe → Ge, and the surface portion of the semiconductor epitaxial layer 15 can be made of single crystal Ge with a certain predetermined thickness.

Subsequently, the surfaces of the insulating layer 14 and the semiconductor epitaxial layer 15 are planarized as necessary.
Next, an amorphous germanium layer is deposited on the insulating layer 14 and the semiconductor epitaxial layer 15.
Thereafter, the amorphous germanium layer is irradiated with a laser beam with a uniform beam. As a result, using the single crystal Ge on the surface portion of the selectively grown semiconductor epitaxial layer 15 as a seed, melt crystallization occurs in the lateral direction (film surface direction), and the germanium layer is single-crystallized to form a single crystal or quasi-single crystal. A second thin film semiconductor layer 16 is formed of a crystalline germanium layer.

  Even when the lower thin film semiconductor layer and the upper thin film semiconductor layer are made of different materials, if the semiconductor epitaxial layer between these thin film semiconductor layers is epitaxially grown by gradually changing the gas flow ratio, the semiconductor epitaxial layer It is possible to make the surface part of the layer of the same material as the upper thin film semiconductor layer. Thus, the upper thin film semiconductor layer can be a single crystal or a quasi-single crystal in a good state.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1 is a schematic configuration diagram (cross-sectional view) of a three-dimensional integrated circuit device according to an embodiment of the present invention. FIG. 2 is a circuit configuration diagram of a cell to which the three-dimensional integrated circuit device of FIG. 1 is applied. A to E are diagrams illustrating a method of manufacturing the three-dimensional integrated circuit device of FIG.

Explanation of symbols

  10 three-dimensional integrated circuit device, 11 glass substrate, 12 protective layer, 13 first thin film semiconductor layer, 14 insulating layer (interlayer insulating layer), 15 semiconductor epitaxial layer, 16 second thin film semiconductor layer, 17 insulating layer , 18 electrode layers, 31 channels, 32, 33 source / drain regions, Tr11, Tr12, Tr13, Tr14, Tr21, Tr22 transistors, BL bit lines, WL word lines

Claims (4)

  1. A single-crystal or quasi-single-crystal thin-film semiconductor layer is stacked on a glass substrate with an interlayer insulating layer interposed therebetween.
    An active element is formed in one or more of the thin film semiconductor layers of the plurality of thin film semiconductor layers. A three-dimensional integrated circuit device, wherein:
  2.   A plurality of the thin film semiconductor layers stacked one above the other through the interlayer insulating layer are connected by a semiconductor epitaxial layer formed by filling an opening formed in the interlayer insulating layer. The three-dimensional integrated circuit device according to claim 1.
  3. Forming an amorphous first thin film semiconductor layer on a glass substrate having an insulating layer formed on the surface;
    Crystallizing the amorphous thin-film semiconductor layer to form a single-crystal or quasi-single-crystal first thin-film semiconductor layer;
    Forming an interlayer insulating layer on the first thin film semiconductor layer and then forming an opening reaching the first thin film semiconductor layer in the interlayer insulating layer;
    Epitaxially growing a semiconductor epitaxial layer in the opening of the interlayer insulating layer;
    Forming an amorphous second thin film semiconductor layer on the interlayer insulating layer and the semiconductor epitaxial layer;
    Crystallizing the amorphous second thin film semiconductor layer to form a single crystal or quasi-single crystal second thin film semiconductor layer,
    A plurality of thin film semiconductor layers including the first thin film semiconductor layer and the second thin film semiconductor layer are stacked via an interlayer insulating layer;
    An active element is formed in one or more thin film semiconductor layers of the plurality of thin film semiconductor layers. A method of manufacturing a three-dimensional integrated circuit device.
  4.   When the amorphous first thin film semiconductor layer is crystallized, or when the amorphous second thin film semiconductor layer is crystallized, the thin film semiconductor layer is irradiated with an ultraviolet beam. The method for manufacturing a three-dimensional integrated circuit device according to claim 3.
JP2007049628A 2007-02-28 2007-02-28 Three-dimensional integrated circuit device and manufacturing method thereof Pending JP2008218468A (en)

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Cited By (3)

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Publication number Priority date Publication date Assignee Title
JP2013505578A (en) * 2009-09-16 2013-02-14 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated A method for solid-phase recrystallization of thin films using pulse train annealing.
JP2017152725A (en) * 2011-09-23 2017-08-31 株式会社半導体エネルギー研究所 Semiconductor device
JP2018032865A (en) * 2010-09-10 2018-03-01 株式会社半導体エネルギー研究所 Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013505578A (en) * 2009-09-16 2013-02-14 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated A method for solid-phase recrystallization of thin films using pulse train annealing.
JP2018032865A (en) * 2010-09-10 2018-03-01 株式会社半導体エネルギー研究所 Semiconductor device
JP2017152725A (en) * 2011-09-23 2017-08-31 株式会社半導体エネルギー研究所 Semiconductor device

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