JP2008217472A - Memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of avoiding or reducing the risk of unintended rewriting of a data caused by reading repeatedly the data from a nonvolatile memory. <P>SOLUTION: An access controller part 34 input with an operation switch request signal input from an address comparison part 33 switches an operation from a usual reading access to a normal read access, when a reading address output from a host system 1 in this time is consistent with a reading address output from a host system 1 in the last. That is, the access controller part 34 reading-accesses a memory buffer part 44, without read-access to a memory access array 43. The risk of unintended rewriting is thereby avoided or reduced by reading repeatedly the data stored in the memory access array 43. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for avoiding or reducing the possibility that data is unintentionally rewritten by repeatedly reading data from a nonvolatile memory.

  Among non-volatile memories, NAND flash memories are used in large quantities in SD memory cards and the like in order to enable high integration, simple manufacturing cost reduction, and easy writing by users. .

  Recently, NAND flash memory has been adopted in game machines and the like. When the NAND flash memory is used in a game machine or the like, writing does not occur and continuous reading occurs. That is, a NAND flash memory is increasingly used as a ROM.

  However, in game machines and the like, since a specific program is often read repeatedly, it has begun to be pointed out that the program may be rewritten unintentionally. Such a phenomenon is called a “Read Disturb” phenomenon, and a mechanism in which this phenomenon occurs will be briefly described below.

  FIG. 8 is a schematic diagram of a NAND flash memory. The NAND flash memory includes bit lines 51 and word lines 52, 53, and 54, memory cells 62 and 63, a selection transistor 64, and the like that are arranged in a lattice pattern.

  Consider a case where binary data (“0” or “1”) stored in the memory cell 62 is read. In this case, the memory cell 62 is called a selected cell 62 and the memory cell 63 is called a non-selected cell 63. First, the bit line 51 to which the selected cell 62 belongs is specified by the selection transistor 64. Next, a low gate voltage V (Low) = 0 V is applied to the word line 52 to which the selected cell 62 belongs. Then, a high gate voltage V (High) to 5 V is applied to the word line 53 to which the non-selected cell 63 belongs. At this time, since the non-selected cell 63 is in a weak write state, electrons are trapped and accumulated in the floating gate of the non-selected cell 63. That is, when the binary data stored in the selected cell 62 is repeatedly read, the threshold voltage of the non-selected cell 63 shifts, and the binary data stored in the non-selected cell 63 changes from “1” to “0”. May be rewritten unintentionally.

  However, even if the binary data stored in the non-selected cell 63 is unintentionally rewritten, the function of the non-selected cell 63 is restored when the data is erased collectively before being newly written. be able to. However, when writing does not occur and continuous reading occurs, the function of the non-selected cell 63 cannot be recovered.

  The following patent documents can be cited as documents providing means for avoiding the “Read Disturb” phenomenon described above.

US Patent Application Publication No. 2005/0210184

  The above-mentioned patent document provides means for avoiding the “Read Disturb” phenomenon by a control method inside a memory cell. However, the method disclosed herein is a method applicable to a memory having a specific cell structure, and is not applicable to other cell structures. That is, it is not a measure that can avoid the “Read Disturb” phenomenon without depending on the cell structure of the memory.

  Accordingly, in view of the above problems, the present invention provides means capable of avoiding or reducing the “Read Disturb” phenomenon even in various types of nonvolatile memories without being restricted by the memory cell structure. With the goal.

  In order to solve the above-mentioned problem, the invention according to claim 1 is a memory system comprising a memory for storing data to be processed by a host system, and a memory controller for controlling read access to the memory. A memory cell array that stores data that can be processed by the host system, and a memory buffer unit that receives and stores data read by the host system from the memory cell array, and the memory controller inputs from the host system Address comparison means for comparing a read address (first address) with a read address (second address) input from the host system before inputting the first address from the host system; and the first address Is included in the second address In this case, memory buffer control means for controlling read access to the memory buffer unit and outputting read data related to the first address stored in the memory buffer unit to the host system; A memory that controls read access to the memory cell array and outputs read data related to the first address stored in the memory cell array to the host system when an address is not included in the second address Cell array control means.

  According to a second aspect of the present invention, there is provided a memory cell array that stores data that can be processed by a host system, a memory buffer unit that is connected to the memory cell array and stores data read by the host system from the memory cell array, Address comparison means for comparing a read address (first address) input from the host system with a read address (second address) input from the host system before inputting the first address from the host system; When the first address is included in the second address, the read access to the memory buffer unit is controlled, and the read data related to the first address stored in the memory buffer unit is Memory buffer control means for output to host system If the first address is not included in the second address, the read access to the memory cell array is controlled, and the read data related to the first address stored in the memory cell array is stored in the host system. And a memory cell array control means for outputting to the memory cell array.

  According to a third aspect of the present invention, in the memory system according to the first or second aspect, the second address includes a read address related to an input immediately before the first address is input from the host system. It is characterized by.

  According to a fourth aspect of the present invention, in the memory system according to the first or second aspect, the second address is a read address related to a predetermined number of inputs immediately before the first address is input from the host system, It is characterized by including.

  According to a fifth aspect of the present invention, in the memory system according to the first or second aspect, the second address is a read address related to a predetermined number of inputs immediately before the first address is input from the host system. Of these, the read address includes a read address that satisfies a predetermined condition.

  According to a sixth aspect of the present invention, in the memory system according to the first or second aspect, the second address includes a read address relating to read data in which an error occurs when the host system processes the read address. It is characterized by.

  According to a seventh aspect of the present invention, in the memory system according to any one of the first to sixth aspects, the second address is set when the host system is turned off immediately before the host system is turned on. A second address, the second address being processed as input before the first address is input from the host system when the host system is powered on. And

  According to an eighth aspect of the present invention, in the memory system according to any one of the first to fifth aspects, the second address is received from the host system when the host system is powered on. It includes a fixed address that is processed as input before inputting one address.

  The invention according to claim 9 is a memory system comprising a memory for storing data to be processed by a host system, and a memory controller for controlling read access to the memory, wherein the memory can be processed by the host system. A memory cell array for storing data; and a memory buffer unit for inputting and storing data read by the host system from the memory cell array, wherein the memory controller is set in advance with a read address input from the host system. Address comparing means for comparing the predetermined address with the predetermined address, and when the read address is included in the predetermined address, the read access to the memory buffer unit is controlled, and the memory buffer unit stores in advance Said reading Memory buffer control means for outputting read data related to the address to the host system, and if the read address is not included in the predetermined address, control the read access to the memory cell array to control the memory cell array And memory cell array control means for outputting read data relating to the read address stored in the host system to the host system.

  The invention according to claim 10 is a memory cell array that stores data that can be processed by a host system, a memory buffer unit that is connected to the memory cell array, stores data read by the host system from the memory cell array, and Address comparison means for comparing a read address input from the host system with a predetermined address set in advance, and when the read address is included in the predetermined address, control the read access to the memory buffer unit Then, when the memory buffer unit control means for outputting read data related to the read address stored in advance in the memory buffer unit to the host system, and the read address is not included in the predetermined address, The memory cell And controls the read access to the array, characterized in that it comprises: a memory cell array control means for outputting the read data according to the read address said memory cell array is stored in the host system.

  According to an eleventh aspect of the present invention, in the memory system according to the ninth or tenth aspect, the predetermined address includes a read address that is likely to be repeatedly input from the host system. And

  According to a twelfth aspect of the present invention, in the memory system according to the ninth or tenth aspect, the predetermined address is read data that is likely to cause an error when processed by the host system. The read address is included.

  According to a thirteenth aspect of the present invention, in the memory system according to any one of the first to twelfth aspects, the memory buffer unit control means operates from a read access to the memory cell array to a read access to the memory buffer unit. The memory cell array control means includes means for maintaining an operation for read access to the memory cell array.

  A fourteenth aspect of the present invention is the memory system according to any one of the first to thirteenth aspects, wherein the memory buffer unit control means outputs the data stored in the memory buffer unit to the host system. Means for notifying the host system that the preparation to be performed is completed, and the memory cell array control means indicates that the preparation for outputting the data stored in the memory cell array to the host system is completed. Means for notifying the host system.

  When newly reading data repeatedly read by the host system, data already stored in the memory buffer unit can be read without reading data newly transferred from the memory cell array to the memory buffer unit. Here, the memory buffer unit is a buffer unit included in the memory that stores read data transferred from the memory cell array.

  Specifically, when the read address newly output by the host system matches the read address previously output by the host system, the access controller unit does not specify the memory cell array but the memory buffer unit. Read access can be controlled.

  Then, in order to newly read data repeatedly read by the host system, data to be newly transferred from the memory cell array to the memory buffer section is not read, so that the “Read Disturb” phenomenon can be avoided or reduced. In addition, since no time is required for the read operation inside the memory cell array, high-speed read access can be realized.

{First embodiment}
<Constituent Elements of Information Processing Device According to the Present Invention>
Hereinafter, the first embodiment will be described with reference to the drawings. FIG. 1 is a block diagram of an information processing apparatus according to the present invention. The information processing apparatus shown in FIG. 1 is, for example, a game machine, and includes a host system 1 and a memory system 2.

  The host system 1 processes data stored in the memory 4 included in the memory system 2. Therefore, the host system 1 outputs a read command to the memory system 2 and reads data from the memory system 2. In the present invention, the host system 1 can read data for one page in the memory 4 by one reading. When the information processing apparatus shown in FIG. 1 is a game machine, the host system 1 is a game machine body.

  In order to distinguish a read command output from the host system 1 to the memory system 2 from a random read command described later, it is defined as a normal read command. The host system 1 according to the present invention does not output a random read command to the memory system 2. The reason why the host system 1 does not output a random read command to the memory system 2 will be described below.

  The memory 4 can respond to various read commands in order to differentiate it from competing products. Then, in order for the host system 1 to be able to cope with various competing products, it is desirable that the host system 1 can cope with various read commands that can be handled by various competing products. However, switching of various read commands by the host system 1 hinders the host system 1 from processing read data at high speed. Therefore, the host system 1 according to the present invention supports only the normal read command that can be dealt with in common by various competing products.

  The memory system 2 stores data processed by the host system 1 in the memory 4. When the normal read command is input from the host system 1, the memory system 2 outputs the data read in the memory 4 to the host system 1. When the information processing apparatus shown in FIG. 1 is a game machine, the memory system 2 is a game cartridge. The memory system 2 includes a memory controller 3 and a memory 4.

  The memory controller 3 controls read access to the memory 4. Specifically, the memory controller 3 compares the read address input this time from the host system 1 with the read address previously input from the host system 1 in the address comparison unit 33 provided in the memory controller 3.

  If the current read address matches the previous read address, the memory controller 3 does not access to the memory cell array 43 included in the memory 4 and does not access the memory buffer unit 44 included in the memory 4. Read access. As a result, no read operation is performed inside the memory cell array 43, so that the “Read Disturb” phenomenon can be avoided or reduced. Furthermore, high-speed read access can be realized. When the current read address does not match the previous read address, the memory controller 3 performs read access to the memory cell array 43.

  The memory 4 stores data to be processed by the host system 1. When the memory 4 receives a read access to the memory buffer unit 44 from the memory controller 3, the memory 4 outputs the data already stored in the memory buffer unit 44 to the memory controller 3. Further, when the memory 4 receives a read access to the memory cell array 43 from the memory controller 3, the memory 4 outputs the data stored in the memory cell array 43 to the memory controller 3 through a new transfer to the memory buffer unit 44. To do.

  The memory controller 3 includes an interface unit 31, an address decoder unit 32, an address comparison unit 33, an access controller unit 34, a first RDY / BSY selector unit 35, a second RDY / BSY selector unit 36, and the like.

  The interface unit 31 is an interface for exchanging normal read commands and read data between the host system 1 and the memory system 2.

  The address decoder unit 32 receives a normal read command from the host system 1 and extracts a read address from the normal read command. Then, the address decoder unit 32 outputs the read address to the address comparison unit 33 and the access controller unit 34.

  The address comparison unit 33 compares the current read address with the previous read address. If the current read address matches the previous read address, the address comparison unit 33 outputs an operation switching request signal to the access controller unit 34. Then, the memory controller 3 can switch the operation from read access to the memory cell array 43 to read access to the memory buffer unit 44.

  If the current read address and the previous read address do not match, the address comparison unit 33 outputs an operation switching unnecessary signal to the access controller unit 34. Then, the memory controller 3 can not switch the operation from the read access to the memory cell array 43.

  The access controller unit 34 controls read access to the memory 4. Specifically, when an operation switching request signal is input from the address comparison unit 33, the access controller unit 34 outputs a random read command and a random read control signal to the memory 4. The random read command is a read command for realizing read access to the memory buffer unit 44.

  In addition, when an operation switching unnecessary signal is input from the address comparison unit 33, the access controller unit 34 outputs a normal read command and a normal read control signal to the memory 4. The normal read command is a read command for realizing read access to the memory cell array 43.

  The first RDY / BSY selector unit 35 and the second RDY / BSY selector unit 36 are selectors for notifying the host system 1 of an RDY / BSY signal indicating the operation state of the memory 4. Specifically, when the host system 1 reads data already stored in the memory buffer unit 44, the host system 1 prepares to read the data after the access controller unit 34 outputs a random read command to the memory 4. Is ready.

  Further, when the host system 1 reads data newly transferred from the memory cell array 43 to the memory buffer unit 44, the host system 1 transfers the data after the memory cell array 43 newly transfers the data to the memory buffer unit 44. Ready to read.

  The memory 4 includes a memory input / output unit 41, a logic controller unit 42, a memory cell array 43, a memory buffer unit 44, and the like.

  The memory input / output unit 41 is an input / output unit for exchanging normal read commands, random read commands, read data, and the like between the memory controller 3 and the memory 4.

  The logic controller unit 42 controls read access to the memory cell array 43 or the memory buffer unit 44. Specifically, the logic controller unit 42 controls read access to the memory buffer unit 44 when a random read command and a random read control signal are input. The logic controller unit 42 controls read access to the memory cell array 43 when a normal read command and a normal read control signal are input.

  The memory cell array 43 stores data processed by the host system 1. When the memory cell array 43 receives a read access from the logic controller unit 42, the memory cell array 43 outputs the stored data to the memory controller 3 through a new transfer to the memory buffer unit 44.

  In the present invention, a single-level cell (SLC) NAND flash memory cell array is used as the memory cell array 43. However, a non-volatile memory cell array such as a multi-level cell (MLC) NAND flash memory cell array can also be used. However, in order to implement the present invention, the nonvolatile memory according to the nonvolatile memory cell array needs to include the memory buffer unit 44.

  The memory buffer unit 44 stores read data transferred from the memory cell array 43. In the first embodiment, the memory buffer unit 44 can store data for one page of the memory cell array 43. When the memory buffer unit 44 receives a read access from the logic controller unit 42, the memory buffer unit 44 outputs already stored data to the memory controller 3.

  If the current read address matches the previous read address, the memory buffer unit 44 holds the previous read data already stored as it is. If the current read address does not match the previous read address, the memory buffer unit 44 updates the previously stored previous read data to the current read data newly transferred from the memory cell array 43. To do.

  In the present invention, components such as the address comparison unit 33 and the access controller unit 34 are arranged in the memory controller 3. However, these components may be arranged in the memory 4 in order to increase the functionality of the memory 4. That is, these components may be arranged at any location in the memory system 2.

  However, in order to implement the present invention, the memory buffer unit 44 needs to directly input read data from the memory cell array 43 and receive a random read access from the access controller unit 34. That is, the memory buffer unit 44 and the memory cell array 43 need to be directly connected without going through the memory input / output unit 41.

<Flow of processing in which memory system outputs read data>
Next, a flow of processing in which the memory system 2 outputs read data to the host system 1 will be described with reference to FIG. FIG. 2 is a flowchart showing a flow of processing in which the memory system 2 outputs read data to the host system 1. Step S shown in FIG. 2 corresponds to step S shown in FIG.

  The address decoder unit 32 inputs a normal read command from the host system 1 via the interface unit 31 (step S1). The address decoder unit 32 does not input a random read command from the host system 1 but inputs only a normal read command from the host system 1. This does not depend on whether the read address that the host system 1 outputs this time matches the read address that the host system 1 previously output.

  The address decoder unit 32 extracts a read address from the normal read command (step S2). In the present invention, the host system 1 can read data for one page of the memory cell 43 by one reading. Therefore, the read address extracted by the address decoder unit 32 is a page address for one page in the memory cell array 43. Then, the address decoder unit 32 outputs the read address to the address comparison unit 33 and the access controller unit 34.

  The address comparison unit 33 receives the read address from the address decoder unit 32 and stores it. The address comparing unit 33 compares the read address input and stored this time with the read address input and stored the previous time (step S3).

  First, a case where the current read address matches the previous read address will be described. The address comparison unit 33 updates the previous read address to the current read address (step S4). Then, the address comparison unit 33 outputs an operation switching request signal to the access controller unit 34. Further, the address comparison unit 33 outputs a binary signal “1” to the first RDY / BSY selector unit 35.

  The access controller unit 34 inputs a read address from the address decoder unit 32. In addition, the access controller unit 34 inputs an operation switching request signal from the address comparison unit 33. Then, the access controller unit 34 switches the operation from normal read access to random read access (step S5). A method by which the access controller unit 34 switches operations will be described with reference to FIG. FIG. 3 is a block diagram showing a flow of processing in which the access controller unit 34 switches operations.

  Based on the operation switching request signal input from the address comparison unit 33, the access controller unit 34 outputs a random read command to the memory input / output unit 41 without outputting a normal read command to the memory input / output unit 41. Here, the random read command includes a random read command ID, a read column address, and a random read start command ID.

  The random read command ID is an identification number for distinguishing the random read command from other read commands such as a normal read command. The random read start command ID is an identification number for distinguishing the random read start command from other read start commands such as a normal read start command. In the present invention, hexadecimal numbers are used as identification numbers.

  The read column address is not a column address inside the memory cell array 43 but a column address inside the memory buffer unit 44. In the present invention, the host system 1 can read all the data for one page of the memory cell array 43 by one reading. Therefore, the read column address is set to the first column 0 in the memory buffer unit 44.

  The read page address is not included in the random read command. This is because the memory buffer unit 44 can store only one page of data in the memory cell array 43. Then, the data already stored in the memory buffer unit 44 is read to the last column in the order of the first column 0, column 1, and column 2.

  Further, the access controller unit 34 outputs a random read control signal to the logic controller unit 42 based on the operation switching request signal input from the address comparison unit 33. Here, the random read control signal is a control signal for the memory 4 to fetch a random read command from the memory controller 3 and for the memory 4 to output read data related to the random read command to the memory controller 3.

  The access controller 34 outputs a binary signal “0” to the second RDY / BSY selector 36 before outputting the random read command to the memory input / output unit 41. The address comparison unit 33 has already output the binary signal “1” to the first RDY / BSY selector unit 35. Then, the second RDY / BSY selector unit 36 can output the binary signal “0” (Low signal) to the host system 1 via the first RDY / BSY selector unit 35.

  In other words, before the access controller unit 34 outputs a random read command to the memory input / output unit 41, the host system 1 cannot acquire the data already stored in the memory buffer unit 44.

  After outputting the random read command to the memory input / output unit 41, the access controller unit 34 outputs the binary signal “1” to the second RDY / BSY selector unit 36. Then, the second RDY / BSY selector unit 36 can output the binary signal “1” (High signal) to the host system 1 via the first RDY / BSY selector unit 35.

  That is, after the access controller unit 34 outputs a random read command to the memory input / output unit 41, the host system 1 can acquire data already stored in the memory buffer unit 44 (step S6). . A method in which the host system 1 acquires data already stored in the memory buffer unit 44 will be described below.

  The memory input / output unit 41 inputs a random read command from the access controller unit 34 and outputs the random read command to the logic controller unit 42 via an I / O terminal included in the memory input / output unit 41. The logic controller unit 42 inputs a random read control signal from the access controller unit 34. In addition, the logic controller unit 42 inputs a random read command from the memory input / output unit 41. Then, the logic controller unit 42 controls read access to the memory buffer unit 44 based on the random read command input from the memory input / output unit 41.

  The memory buffer unit 44 has already stored the previous read data. When the memory buffer unit 44 receives a read access from the logic controller unit 42, the memory buffer unit 44 outputs the previous read data to the memory input / output unit 41 as the current read data.

  The memory input / output unit 41 inputs the current read data from the memory buffer unit 44 and outputs it to the memory controller 3 via an I / O terminal included in the memory input / output unit 41. Then, the host system 1 can acquire the current read data via the interface unit 31.

  The case where the current read address matches the previous read address will be summarized. Based on the operation switching request signal input from the address comparison unit 33, the access controller unit 34 can perform random read control on the memory 4 without performing normal read control on the memory 4.

  Then, the host system 1 can read data already stored in the memory buffer unit 44 without reading data newly transferred from the memory cell array 43 to the memory buffer unit 44. Therefore, the “Read Disturb” phenomenon can be avoided or reduced. In addition, since no time is required for the read operation in the memory cell array 43, high-speed read access can be realized.

  Next, a case where the current read address does not match the previous read address will be described. The address comparison unit 33 updates the previous read address to the current read address (step S7). The address comparison unit 33 then outputs an operation switching unnecessary signal to the access controller unit 34. Further, the address comparison unit 33 outputs a binary signal “0” to the first RDY / BSY selector unit 35.

  The access controller unit 34 inputs a read address from the address decoder unit 32. In addition, the access controller unit 34 inputs an operation switching unnecessary signal from the address comparison unit 33. Then, the access controller unit 34 maintains the operation for normal read access (step S8). A method of maintaining the operation by the access controller 34 will be described with reference to FIG.

  The access controller unit 34 outputs a normal read command to the memory input / output unit 41 based on the operation switching unnecessary signal input from the address comparison unit 33. Here, the normal read command includes a normal read command ID, a read column address, a read page address, and a normal read start command ID.

  The normal read command ID is an identification number for distinguishing the normal read command from other read commands. The normal read start command ID is an identification number for distinguishing the normal read start command from other read start commands.

  The read column address is a column address in the read target page of the memory cell array 43. In the present invention, the host system 1 can read all the data for one page of the memory cell array 43 by one reading. Therefore, the read column address is set to the first column 0 in the read target page of the memory cell array 43.

  The read page address is the page address of the read target page of the memory cell array 43. In FIG. 3, the access controller unit 34 inputs the page P1 of the memory cell array 43 from the address decoder unit 32 as a read address. Therefore, the read page address is set to page P1 of the memory cell array 43. Then, the data stored in the page P1 of the memory cell array 43 is read to the last column in the order of the first column 0, column 1, and column 2.

  Further, the access controller unit 34 outputs a normal read control signal to the logic controller unit 42 based on the operation switching unnecessary signal input from the address comparison unit 33. Here, the normal read control signal is a control signal for the memory 4 to fetch a normal read command from the memory controller 3 and for the memory 4 to output read data related to the normal read command to the memory controller 3.

  The access controller unit 34 does not output the binary signal “0” or “1” to the second RDY / BSY selector unit 36. However, the address comparison unit 33 has already output the binary signal “0” to the first RDY / BSY selector unit 35. Then, the logic controller unit 42 can output the RDY / BSY signal indicating the operation state of the memory 4 to the host system 1 via the first RDY / BSY selector unit 35.

  That is, the host system 1 inputs an RDY / BSY signal indicating the operation state of the memory 4 and confirms that the operation state of the memory 4 is the READY state. It is possible to acquire the data transferred to (step S9). A method in which the host system 1 acquires data newly transferred from the memory cell array 43 to the memory buffer unit 44 will be described below.

  The memory input / output unit 41 receives a normal read command from the access controller unit 34 and outputs it to the logic controller unit 42 via an I / O terminal provided in the memory input / output unit 41. The logic controller unit 42 inputs a normal read control signal from the access controller unit 34. In addition, the logic controller unit 42 inputs a normal read command from the memory input / output unit 41. Then, the logic controller unit 42 controls read access to the memory cell array 43 based on the normal read command input from the memory input / output unit 41.

  When the memory cell array 43 receives a read access from the logic controller unit 42, the memory cell array 43 performs an operation of reading the current read data. Then, the memory cell array 43 transfers the current read data to the memory buffer unit 44.

  The memory buffer unit 44 inputs the current read data from the memory cell array 43. Then, since the memory buffer unit 44 can store only the read data for one page of the memory cell array 43, the previous read data is updated to the current read data. Then, the memory buffer unit 44 outputs the current read data to the memory input / output unit 41.

  The memory input / output unit 41 inputs the current read data from the memory buffer unit 44 and outputs it to the memory controller 3 via an I / O terminal included in the memory input / output unit 41. Then, the host system 1 can acquire the current read data through the interface unit 31 after confirming that the operation state of the memory 4 is the READY state.

  Next, a flow of processing in which the memory system 2 outputs read data to the host system 1 when the host system 1 sequentially outputs read commands to the memory system 2 will be described with reference to FIG. FIG. 4 is a diagram illustrating a time-series change in the read address comparison result and the read operation location according to the first embodiment. It shows that the host system 1 outputs read commands to the memory system 2 one after another as it moves from the upper stage to the lower stage.

  A dotted line immediately below the double line in FIG. 4 indicates that the host system 1 has successively output read commands to the memory system 2. In the first row below the double line in FIG. 4, the previous read address output from the host system 1 to the memory system 2 is page P1. The memory buffer unit 44 already stores the read data of the page P1.

  In the first row below the double line in FIG. 4, the current read address output from the host system 1 to the memory system 2 is page P1. The current read address matches the previous read address (step S3). Therefore, the access controller unit 34 switches the operation from normal read access to random read access (step S5). Then, the host system 1 reads the read data of the page P1 already stored in the memory buffer unit 44 as the current read data (step S6).

  The address comparison unit 33 updates the previous read address to the current read address (step S4). However, since the current read address matches the previous read address, the address comparison unit 33 does not need to update the read address. The memory buffer unit 44 holds the read data of the page P1 already stored as it is.

  In the third row below the double line in FIG. 4, the current read address output from the host system 1 to the memory system 2 is page P2. The current read address does not match the previous read address (step S3). Therefore, the access controller unit 34 maintains the operation for the normal read access (step S8). Then, the host system 1 reads the read data of the page P2 newly transferred from the memory cell array 43 to the memory buffer unit 44 as the current read data (step S9).

  The address comparison unit 33 updates the previous read address to the current read address (step S7). The memory buffer unit 44 stores the read data of the page P2 newly transferred from the memory cell array 43.

  In the fifth row below the double line in FIG. 4, the current read address and the previous read address are the same (step S3). Therefore, the same processing flow as described in the first line below the double line in FIG. 4 is executed. Further, in the seventh row below the double line in FIG. 4, the current read address and the previous read address do not match (step S3). Therefore, the same processing flow as described in the third line below the double line in FIG. 4 is executed.

  As a method for setting the previous read address when the host system 1 is turned on, the dotted line immediately below the double line in FIG. First, when the host system 1 is previously turned off, the last read address output from the host system 1 to the memory system 2 is used as the previous read address when the host system 1 is turned on again. How to set up. Next, there is a method of setting a specific read address as the previous read address each time the host system 1 is turned on.

{Second embodiment}
In the first embodiment, when the current read address matches the previous read address, the access controller unit 34 can access the memory buffer unit 44 instead of the memory cell array 43. it can. Therefore, the “Read Disturb” phenomenon can be avoided or reduced. Here, even if the host system 1 outputs the read addresses of the page P1 and the page P2 alternately, means for avoiding or reducing the “Read Disturb” phenomenon are described in the second to fourth. The embodiment will be described.

  FIG. 5 is a diagram showing a time-series change in the read address comparison result and the read operation location according to the second embodiment. The read address stored by the address comparison unit 33 is the read address output by the host system 1 with the latest three outputs. In FIG. 5, the latest three read addresses are shown from the left end to the right end in the order in which the host system 1 outputs them. For example, “pages P1, P2, and P3” indicate that the host system 1 has output read addresses in the order of P1, P2, and P3. In addition, the memory buffer unit 44 can store the data read three times recently.

  When the current read address is included in the latest three read addresses, the access controller unit 34 performs read access to the memory buffer unit 44. The memory buffer unit 44 holds the read data already stored as it is. Further, when the current read address is not included in the latest three read addresses, the access controller unit 34 performs read access to the memory cell array 43. The memory buffer unit 44 updates the earliest read data among the read data already stored to the current read data.

  In the second embodiment, the memory buffer unit 44 can store read data of the last three times. Then, the random read command shown in FIG. 3 needs to include the read page address of the memory buffer unit 44. For example, in the first line below the double line in FIG. 5, the current read address (page P1) matches the earliest read address (page P1) among the three most recent read addresses. Therefore, the memory buffer unit 44 may set the read page address in an area for storing the read data of the page P1.

  Regardless of whether the current read address is included in the latest three read addresses or not, the address comparison unit 33 updates the stored read address. That is, of the latest three read addresses, the earliest read address is deleted, and the current read address is added.

{Third embodiment}
FIG. 6 is a diagram illustrating a time-series change in the read address comparison result and the read operation location according to the third embodiment. The read address stored by the address comparison unit 33 is the read address output by the host system 1 with the latest five outputs. Further, the memory buffer unit 44 can store the top two read data having the highest number of reads out of the latest five read data.

  If the current read address is included in the top two most frequently read addresses, the access controller unit 34 performs read access to the memory buffer unit 44. If the current read address is not included in the second highest read address with the highest output count, the access controller unit 34 performs read access to the memory cell array 43.

  If the current read address is not included in the second highest read address with a large number of outputs, the current read data is newly transferred from the memory cell array 43 to the memory buffer unit 44. Then, the memory buffer unit 44 needs to include not only an area for storing the top two read data having a large number of reads, but also an area for newly inputting the current read data from the memory cell array 43.

  As an example to which the third embodiment is applied, the address comparison unit 33 stores a histogram of the number of outputs for the read address output by the host system 1. Then, the address comparison unit 33 refers to the stored histogram, selects a read address with a large number of outputs, and compares it with the read address output this time by the host system 1.

  As an embodiment in which the address comparison unit 33 stores a histogram of the number of outputs, first, the address comparison unit 33 for the read address output by the host system 1 between the time when the host system 1 is turned on and the time when it is turned off. Stores a histogram of the number of outputs. Then, a read address with a large number of outputs can be set as a read address to be compared with a read address newly output by the host system 1 when the host system 1 is turned on next time.

  As an embodiment in which the address comparison unit 33 stores a histogram of the number of outputs, the address comparison unit 33 stores a histogram of the number of outputs for the read address output by the host system 1 at a predetermined number of outputs. A read address satisfying a predetermined condition with a large number of outputs is set as a comparison address, and read data related to the comparison address is stored in the memory buffer unit 44.

  After the read data relating to the comparison address is stored in the memory buffer unit 44, the address comparison unit 33 erases the histogram of the output count already stored. When the read address output by the host system 1 at the next predetermined number of outputs matches the comparison address that has already been set, the access controller unit 34 performs read access to the memory buffer unit 44.

  For the read address output by the host system 1 at the next predetermined number of outputs, the address comparison unit 33 newly stores a histogram of the number of outputs. A read address satisfying a predetermined condition with a large number of outputs is set as a new comparison address, and read data relating to the new comparison address is stored in the memory buffer unit 44. Here, if the read data related to the new comparison address is already stored in the memory buffer unit 44, it is not necessary to newly transfer the read data related to the new comparison address from the memory cell array 43 to the memory buffer unit 44. . Thereafter, the same processing flow is continued.

{Fourth embodiment}
FIG. 7 is a diagram showing a time-series change in the read address comparison result and the read operation place according to the fourth embodiment. The read address stored in the address comparison unit 33 is a predetermined address for three pages of the memory cell array 43 set in advance. Even when the host system 1 sequentially outputs read commands to the memory system 2, the address comparison unit 33 does not update the predetermined address. Further, the memory buffer unit 44 can store read data relating to a predetermined address.

  As the predetermined address set in advance, first, a read address that is likely to be repeatedly output by the host system 1 is given. This is convenient when it is assumed that the host system 1 is likely to repeatedly read specific data when designing data stored in the memory cell array 43.

  As the predetermined address set in advance, a read address relating to read data that is assumed to be highly likely to cause an error when the host system 1 processes next. For example, when an error occurs when the host system 1 processes read data, for example, when data is transferred from the memory cell array 43 to the memory buffer unit 44, an error occurs in the data, and other data An error may occur. When an error occurs in other data, a case is considered in which data stored in a memory cell that is not a read target is unintentionally rewritten. This is convenient when read data that is likely to cause an error when the host system 1 performs processing is specified due to the structure of the memory cell array 43.

{Fifth embodiment}
In the first to fourth embodiments, the “Read Disturb” phenomenon can be avoided or reduced for data repeatedly read by the host system 1. Here, the present invention can be implemented even when an error actually occurs with respect to data that the host system 1 repeatedly reads.

  Each time the host system 1 processes read data and an error occurs, the address comparison unit 33 stores a read address related to the read data in which the error has occurred. The memory buffer unit 44 stores read data that has been subjected to error correction. When the host system 1 is turned off, when the host system 1 is turned on, the address comparison unit 33 sets the read address related to the read data in which the error stored in the address comparison unit 33 has occurred. Store as it is.

  When the host system 1 repeatedly reads data subjected to error correction in the future, the access controller unit 34 can read and access the memory buffer unit 44 instead of the memory cell array 43. Therefore, the further “Read Disturb” phenomenon can be avoided or reduced.

It is a block diagram of the information processor concerning the present invention. It is a flowchart which shows the flow of a process in which a memory system outputs read data to a host system. It is a block diagram which shows the flow of the process which an access controller part switches operation. It is a figure which shows the time-series change of the read address comparison result and read operation place which concern on 1st Embodiment. It is a figure which shows the time-series change of the read address comparison result and read operation place which concern on 2nd Embodiment. It is a figure which shows the time-series change of the read address comparison result and read operation place which concern on 3rd Embodiment. It is a figure which shows the time series change of the read address comparison result and read operation place which concern on 4th Embodiment. 1 is a schematic diagram of a NAND flash memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Host system 2 Memory system 3 Memory controller 4 Memory 31 Interface part 32 Address decoder part 33 Address comparison part 34 Access controller part 35 1st RDY / BSY selector part 36 2nd RDY / BSY selector part 41 Memory input / output part 42 Logic controller part 43 Memory cell array 44 Memory buffer unit 51 Bit lines 52, 53, 54 Word line 62 Selected cell 63 Non-selected cell 64 Selected transistor

Claims (14)

A memory for storing data to be processed by the host system;
A memory controller for controlling read access to the memory;
A memory system comprising:
The memory is
A memory cell array for storing data that can be processed by the host system;
A memory buffer unit for storing data read by the host system from the memory cell array;
Including
The memory controller is
Address comparison means for comparing a read address (first address) input from the host system with a read address (second address) input from the host system before inputting the first address from the host system. When,
When the first address is included in the second address, the read access to the memory buffer unit is controlled, and the read data related to the first address stored in the memory buffer unit is stored in the host Memory buffer control means for outputting to the system;
When the first address is not included in the second address, the read access to the memory cell array is controlled, and the read data related to the first address stored in the memory cell array is sent to the host system. Memory cell array control means for outputting;
A memory system comprising: A memory cell array for storing data that can be processed by the host system;
A memory buffer connected to the memory cell array and storing data read by the host system from the memory cell array;
Address comparison means for comparing a read address (first address) input from the host system with a read address (second address) input from the host system before inputting the first address from the host system. When,
When the first address is included in the second address, the read access to the memory buffer unit is controlled, and the read data related to the first address stored in the memory buffer unit is stored in the host Memory buffer control means for outputting to the system;
When the first address is not included in the second address, the read access to the memory cell array is controlled, and the read data related to the first address stored in the memory cell array is sent to the host system. Memory cell array control means for outputting;
A memory system comprising: The memory system according to claim 1 or 2,
The second address is
A read address according to an input immediately before inputting the first address from the host system;
A memory system comprising: The memory system according to claim 1 or 2,
The second address is
A read address according to a predetermined input just before inputting the first address from the host system;
A memory system comprising: The memory system according to claim 1 or 2,
The second address is
Among the read addresses related to the predetermined number of inputs immediately before inputting the first address from the host system, the read address satisfies a predetermined condition,
A memory system comprising: The memory system according to claim 1 or 2,
The second address is
A read address relating to read data in which an error has occurred when the host system has processed,
A memory system comprising: The memory system according to any one of claims 1 to 6,
The second address is
The second address when the host system is turned off immediately before the host system is turned on, and the first address is input from the host system when the host system is turned on. The second address processed as previously entered,
A memory system comprising: The memory system according to any one of claims 1 to 5,
The second address is
A fixed address that is processed as input prior to inputting the first address from the host system when the host system is powered on;
A memory system comprising: A memory for storing data to be processed by the host system;
A memory controller for controlling read access to the memory;
A memory system comprising:
The memory is
A memory cell array for storing data that can be processed by the host system;
A memory buffer unit for storing data read by the host system from the memory cell array;
Including
The memory controller is
Address comparison means for comparing a read address input from the host system with a predetermined address set in advance;
When the read address is included in the predetermined address, the read access to the memory buffer unit is controlled, and the read data related to the read address stored in the memory buffer unit in advance is sent to the host system. Memory buffer control means for outputting;
A memory that controls read access to the memory cell array and outputs read data related to the read address stored in the memory cell array to the host system when the read address is not included in the predetermined address Cell array control means;
A memory system comprising: A memory cell array for storing data that can be processed by the host system;
A memory buffer connected to the memory cell array and storing data read by the host system from the memory cell array;
Address comparison means for comparing a read address input from the host system with a predetermined address set in advance;
When the read address is included in the predetermined address, the read access to the memory buffer unit is controlled, and the read data related to the read address stored in the memory buffer unit in advance is sent to the host system. Memory buffer control means for outputting;
A memory that controls read access to the memory cell array and outputs read data related to the read address stored in the memory cell array to the host system when the read address is not included in the predetermined address Cell array control means;
A memory system comprising: The memory system according to claim 9 or 10,
The predetermined address is
Read address that is likely to be repeatedly input from the host system,
A memory system comprising: The memory system according to claim 9 or 10,
The predetermined address is
A read address associated with read data that is assumed to be highly likely to cause an error when processed by the host system;
A memory system comprising: The memory system according to any one of claims 1 to 12,
The memory buffer control means
Means for switching operation from read access to the memory cell array to read access to the memory buffer unit;
Including
The memory cell array control means includes:
Means for maintaining operation in read access to the memory cell array;
A memory system comprising: The memory system according to any one of claims 1 to 13,
The memory buffer control means
Means for notifying the host system that the data stored in the memory buffer is ready to be output to the host system;
Including
The memory cell array control means includes:
Means for notifying the host system that the data stored in the memory cell array is ready to be output to the host system;
A memory system comprising:

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