JP2008084459A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device having a function useful for evading an error in a writing operation or erasing operation by recognizing the internal state. <P>SOLUTION: A main memory cell array 6 is constituted of a plurality of main memory cells for recording an input information. When an instruction to write or erase is given, a write/erase control circuit 4 controls to repeat voltage application for the writing or erasing operation with respect to a target memory cell selected by an address decoder, until the data writing or erasing operation is completed, and to write a characteristic value showing the number of times of repeating the voltage application, required by the target memory cell before the data writing or erasing operation is completed, into an auxiliary memory cell corresponding to the block in which the target memory cell belongs, in a plurality of auxiliary memory cells constituting an auxiliary memory cell array 7. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having a function useful for avoiding errors in a write operation and an erase operation.

  An EEPROM such as a flash memory, which is a typical nonvolatile semiconductor memory device, changes the threshold voltage by injecting hot carriers into the charge storage layer of the memory cell transistor and applies the same voltage accordingly. Whether or not the inversion layer is formed changes, and whether or not a read current is generated when the voltage is applied changes. Whether or not the read current is detected is correlated with “0” and “1” in the binary signal to determine whether or not the target memory cell is in the write state.

  At this time, the value of the threshold voltage differs for each memory cell transistor due to variations in manufacturing conditions. Further, when the write or erase operation is repeated, this variation is further increased due to, for example, deterioration of the oxide film in the memory cell.

  Therefore, normally, when performing a write or erase operation, each time such an operation is performed, a read operation is performed on the memory cell to be written or erased to confirm that writing has been performed correctly or the registered information is Whether or not the data has been correctly erased is confirmed (verification processing), and if writing or erasure has not been performed correctly, an error can be avoided by repeatedly performing the writing or erasing operation. On the other hand, if the writing or erasing operation is repeated a predetermined number of times or more, if the writing or erasing is not performed correctly, the block including the memory cell to be written or erased is defective. Recognize and output a signal to that effect.

  At this time, a means for holding the address of the block (bad block) recognized as defective is provided, and the address designated as a write target from the outside is compared with the address of the defective block. Conventionally, a nonvolatile semiconductor memory device including a block replacement unit that designates a block as a target block has been provided (see, for example, Patent Document 1).

JP 7-29392 A

  According to the configuration of Patent Document 1, when the address of a block to be written matches the address of a defective block, a write error can be avoided by automatically designating a substitute block as the target block.

  By the way, when there is a bias in the memory cell designated as the target of writing or erasing, the probability that a writing error or erasing error will occur due to repeated writing and erasing is increased as described above. It is possible that a writing or erasing error occurs in a block including, and such an error does not occur in another block. That is, if the internal state of each block of the nonvolatile semiconductor memory device is recognized before a write or erase error actually occurs, there is a probability that the error has occurred before the actual error occurs. The existence of a high block can be known, and an error can be avoided in advance. However, the nonvolatile semiconductor memory device described in Patent Document 1 does not have such a function, and if the target block and the defective block match, only the alternative block is designated, and at the stage before the defective block is generated. Recognizing the internal state does not have the effect of suppressing the occurrence of bad blocks.

  In view of the above problems, an object of the present invention is to provide a nonvolatile semiconductor memory device having a function useful for avoiding errors in a write operation and an erase operation by making the internal state recognizable.

  In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention is a target of writing or erasing among a plurality of nonvolatile main memory cells storing user data and the plurality of main memory cells. A plurality of non-volatile storages for storing an internal state indicating a write or erase characteristic of the main memory cell for each block which is a structural unit composed of an address decoder for selecting a target memory cell and a predetermined number of the main memory cells An auxiliary memory cell; and a write / erase control circuit for controlling the writing or erasing of the user data to the target memory cell and controlling the writing of the internal state to the auxiliary memory cell. When the write / erase control circuit is instructed to write or erase the target memory cell, Control is performed to repeatedly execute a voltage application process for writing or erasing the target memory cell until data writing or erasing is completed, and the target memory cell is required until data writing or erasing is completed. The first characteristic is that control is performed to write the characteristic value indicating the number of repetitions of the voltage application process to the auxiliary memory cell corresponding to the block to which the target memory cell belongs.

  According to the first characteristic configuration of the nonvolatile semiconductor memory device according to the present invention, the internal state indicating the write or erase characteristic of the main memory cell is recorded in the auxiliary memory cell inside the nonvolatile semiconductor memory device. The internal state of the main memory cell can be recognized by reading the information recorded in the auxiliary memory cell before performing the writing process or the erasing process. In particular, in the auxiliary memory cell, a characteristic value indicating the number of repetitions of the voltage application process required for correctly writing or erasing the main memory cell is recorded for each block to which the main memory cell belongs. By recognizing the number of repetitions represented by this characteristic value, the probability of occurrence of an error can be known in advance.

  That is, as the number of voltage application processes to the main memory cell increases, the deterioration of the oxide film in the main memory cell progresses, and as a result, there is a high probability that a defective memory cell cannot be correctly written or erased. Become. In a configuration having a plurality of main memory cells, particularly when a write process or an erase process is frequently performed on some main memory cells, such a main memory cell may become a defective memory cell. If such a memory cell is further designated as a target for the write process or erase process, the voltage application process is repeated many times until a correct write or erase operation is performed, which requires a lot of processing time. And the burden on the microprocessor increases. According to the configuration of the nonvolatile semiconductor memory device according to the present invention, it is likely that such a defective memory cell can be obtained by reading information stored in the auxiliary memory cell in a stage before performing the writing process or the erasing process. Since the presence of a high main memory cell can be recognized, even if such a memory cell exists, a measure that the memory cell is not used can be taken in advance. Thus, it is possible to avoid a situation where a writing process or an erasing process is performed.

  As the above characteristic value, the number of repetitions itself may be adopted, or a range to which the number of repetitions belongs may be adopted. In the former case, it is possible to recognize the number of repetitions by reading the characteristic value, and in the latter case, it is possible to recognize the range of the number of repetitions (for example, 10 to 19 times) by reading the characteristic value. .

  According to the nonvolatile semiconductor memory device of the invention, in addition to the first characteristic configuration, the write / erase control circuit counts the number of repetitions of the voltage application process and temporarily counts the number of repeated executions. When a write or erase instruction is given to the target memory cell, control is performed to write or erase data to the target memory cell, and the counter circuit is executed after the execution. The comparison is performed between the number of repeated executions recorded in the memory and the number of repetitions represented by the characteristic value recorded in the auxiliary memory cell corresponding to the block to which the target memory cell belongs. In this case, the number of repeated executions is set as the characteristic value in the block to which the target memory cell belongs. Te, to carry out control writing in the auxiliary memory cell corresponding to the second feature.

  According to the second characteristic configuration of the nonvolatile semiconductor memory device according to the present invention, the information recorded in the auxiliary memory cell is a plurality of main memory cells included in the block to which the corresponding main memory cell belongs. Since the number of times of voltage application required at the present time for correctly executing the writing process or the erasing process is recorded as the number itself or a range of the number of times, by reading such information, the latest of the main memory cell is always updated. The internal state can be recognized.

  In addition to the second characteristic configuration, the nonvolatile semiconductor memory device according to the present invention includes a plurality of the auxiliary memory cells corresponding to the same block, and the write / erase control circuit includes the target memory cell. A third feature is that the different auxiliary memory cells are designated as write destinations in accordance with the range of the number of repetitions.

  As described above, the repeated execution required until the writing or erasing process is repeated with respect to the same main memory cell, so that the deterioration of the main memory cell proceeds, and accordingly the writing or erasing is correctly performed. The number of times increases. Since this degree of deterioration cannot normally be automatically repaired with time, the number of voltage application processes required until the same main memory cell is correctly written or erased increases with time. Or tend to maintain the same number of times, and this applies to each of the plurality of main memory cells as well. That is, when viewed in units of blocks composed of a plurality of main memory cells, the number of repetitions of each of a plurality of main memory cells belonging to the same block increases with time or maintains the same number of times. It can be seen that the number of repetitions recorded in the auxiliary memory cell every time also increases with time or maintains the same number.

  Therefore, according to the third characteristic configuration of the nonvolatile semiconductor memory device according to the present invention, the write destination is changed according to the range of the number of repetitions, so that the auxiliary memory cell is not erased, It is possible to update information on the number of repetitions of a plurality of main memory cells belonging to the corresponding block. For example, by assigning each auxiliary memory cell according to the range of the number of repetitions, and when the number of repetitions within each range is realized for the first time, writing to the auxiliary memory cell corresponding to the range is performed. From the write state of the plurality of auxiliary memory cells corresponding to the block, the number of repetitions of the plurality of main memory cells belonging to the block can be recognized. Further, since the erase process is not performed, the processing time additionally performed on the auxiliary memory cell after the completion of the writing or erasing process of the user data to the main memory cell is short. It is not a configuration that additionally requires a processing burden. Further, since the configuration is such that the erasing process is not performed on the auxiliary memory cell, the erasing means for erasing the data recorded in the auxiliary memory cell can be provided, whereby the memory is stored by the auxiliary memory cell. The number of repetitions is not erased by mistake, and the information is stabilized.

  In addition to the second or third feature configuration, the nonvolatile semiconductor memory device according to the present invention includes an auxiliary memory cell for storing write information and an erase information storage as the auxiliary memory cell corresponding to the same block. And when the write / erase control circuit is given a write instruction to the target memory cell, the write information storage auxiliary memory cell is stored in the write destination of the characteristic value. When the erase instruction is given to the target memory cell, the erase information storing auxiliary memory cell is designated as the write destination of the characteristic value.

  According to the fourth characteristic configuration of the nonvolatile semiconductor memory device according to the present invention, the information recorded in the write information storing auxiliary memory cell and the erase information storing auxiliary memory cell corresponding to the same block, respectively. By separately reading, the number of repetitions required for the write operation and the number of repetitions required for the erase operation can be recognized separately, so that the detailed internal state of the main memory cell can be known. .

  According to the nonvolatile semiconductor memory device of the present invention, in addition to any one of the second to fourth characteristic configurations, the block includes a plurality of the main blocks that are simultaneously controlled by the write / erase control circuit. A fifth feature is that the memory cell is used.

  The nonvolatile semiconductor memory device according to the present invention includes a plurality of main memory cells arranged in a matrix in the row direction and the column direction in addition to any one of the second to fifth characteristic configurations. A plurality of word lines to which the main memory cells in the same row are connected in common, and a plurality of bit lines to which the main memory cells in the same column are connected in common. The decoder selects the word line and the bit line connected to the target memory cell corresponding to the address specified by the input address signal, and the write / erase control circuit selects the selected bit line. A sixth feature is that writing or erasing of the target memory cell is performed by giving an instruction to apply a predetermined voltage.

  In addition to the sixth characteristic configuration, the nonvolatile semiconductor memory device according to the present invention has the characteristic that the write / erase control circuit reads from the auxiliary memory cell selected based on the address signal. A seventh feature is that the comparison processing is performed between the number of repetitions represented by the value and the number of repetitions.

  According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory device that outputs the characteristic value recorded in each of the plurality of auxiliary memory cells, in addition to any one of the first to seventh characteristic configurations. It is an eighth feature to have

  According to the eighth characteristic configuration of the nonvolatile semiconductor memory device of the present invention, the information recorded in the auxiliary memory cell is output from the output circuit and read out, thereby writing or erasing the main memory cell. The internal state of the main memory cell can be recognized without performing the above.

  According to the configuration of the present invention, since the internal state of the main memory cell is recorded in the auxiliary memory cell in the nonvolatile semiconductor memory device, it is recorded in the auxiliary memory cell before performing the writing process or the erasing process. By reading the stored information, the state of the main memory cell can be recognized. In particular, in the auxiliary memory cell, the characteristic value indicating the number of times of voltage application processing required to correctly perform writing or erasing to the main memory cell is recorded for each block to which the main memory cell belongs. By reading the characteristic value recorded in the memory cell and recognizing the number of voltage application processes represented by the characteristic value, it is possible to know in advance the probability of occurrence of such an error at a stage before a write or erase error actually occurs. it can.

  Embodiments of a nonvolatile semiconductor memory device according to the present invention (hereinafter referred to as “device of the present invention” as appropriate) will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of the apparatus of the present invention. As shown in FIG. 1, the device 1 of the present invention comprises an input / output circuit 2, an interface circuit 3, a write / erase control circuit 4, a main memory cell array 6, and an auxiliary memory cell array 7. The main memory cell array 6 includes a plurality of nonvolatile memory cells (hereinafter referred to as “main memory cells”) arranged in a matrix in the row direction and the column direction. Are connected to a common word line, and main memory cells in the same column are connected to a common bit line. In addition, in the peripheral portion of the main memory cell array 6, a predetermined word line is selected similarly to the row decoder 22 configured to select a predetermined word line and apply a predetermined voltage to the selected word line. In addition, a column decoder 23 configured to be able to apply a predetermined voltage to the selected bit line, and a block decoder 21 that activates the row decoder 22 and the column decoder 23 are provided. The device 1 of the present invention has a configuration including a plurality of one block including the main memory cell array 6, the block decoder 21, the row decoder 22, and the column decoder 23.

  The input / output circuit 2 is a circuit for inputting / outputting an address, data (user data, external command, internal state data, etc.) or various control signals to / from an external circuit.

  The interface circuit 3 analyzes the signal given from the input / output circuit 2 and gives each command signal such as writing or erasing to the writing / erasing control circuit 4, and gives address signals to the block decoder 21, row decoder 22, column decoder 23. (Hereinafter, these decoders are collectively referred to as “address decoders” where appropriate).

  The block decoder 21 activates the row decoder 22 and the column decoder 23 included in a target block (hereinafter referred to as “target block”) based on the address signal. The row decoder 22 and the column decoder 23 select a word line and a bit line connected to a target memory cell (hereinafter referred to as “target memory cell”) based on an address signal, and are designated by the write / erase control circuit 4. A predetermined pulse voltage corresponding to the processed content is applied (hereinafter, the pulse voltage application processing is referred to as “voltage application processing”).

  The write / erase control circuit 4 gives a predetermined voltage application instruction to the row decoder 22 and the column decoder 23 based on a command signal (write command, erase command, etc.) given from the interface circuit 3. For example, when a write command signal is given from the interface circuit 3, the write / erase control circuit 4 gives a write voltage application instruction to the row decoder 22 and the column decoder 23. Of the row decoder 22 and the column decoder 23 provided in each block, the row decoder 22 and the column decoder 23 associated with the target block activated by the block decoder 21 determine in advance based on the write voltage application instruction. The write pulse voltage thus written is applied to the target memory cell, whereby writing is performed on the target memory cell. Similarly, when the write / erase control circuit 4 receives an erase command signal from the interface circuit 3, the row decoder 22 and the column decoder 23 associated with the target block are determined in advance based on the erase voltage application instruction. An erasing pulse voltage is applied to the target memory cell, thereby erasing the target memory cell. In particular, by setting all memory cells belonging to the target block as the target memory cell, the erase operation can be performed in a block unit.

  The write / erase control circuit 4 gives a write or erase voltage application instruction to the row decoder 22 and the column decoder 23, and then confirms whether the write or erase operation has been correctly performed on the target memory cell. The verifying means and a counter circuit to be described later are provided.

  The auxiliary memory cell array 7 is composed of a plurality of nonvolatile memory cells (hereinafter referred to as “auxiliary memory cells”), and the internal state of the block to which each main memory cell belongs is determined for each block by the plurality of auxiliary memory cells. Is recorded. Similarly to the main memory cell array 6, also in the peripheral portion of the auxiliary memory cell array 7, a row decoder 24 and a column decoder 25 (hereinafter referred to as appropriate) for selecting a word line and a bit line connected to each auxiliary memory cell. These decoders are collectively referred to as “auxiliary address decoders”). The nonvolatile memory cell used for the auxiliary memory cell and the main memory cell described above may be any type as long as it is a memory cell in which data is stored by separately writing and erasing data such as a flash memory cell. It doesn't matter.

  The main memory cell array 6 and the auxiliary memory cell array 7 include read sense amplifiers 31 and 32 for outputting and reading information recorded in the internal memory cells to the outside. When a read command of information recorded at a predetermined address related to the main memory cell array 6 is given to the interface circuit 3, a read voltage is applied to the target memory cell specified based on the address signal by the address decoder. The read information is read from the input / output circuit 2 through the sense amplifier 31. When a read command for the auxiliary memory cell array 7 is given to the interface circuit 3, a read voltage is applied by the auxiliary address decoder to the auxiliary memory cell specified based on the address signal, and the read information is read. Is read from the input / output circuit 2 via the sense amplifier 32. The details of the operation of reading information recorded in the auxiliary memory cell array 7 will be described later.

  FIG. 2 is a flowchart showing an operation procedure when writing or erasing user data to the apparatus 1 of the present invention. Hereinafter, with reference to a flowchart shown in FIG. 2, an operation procedure when information is written to or erased from the device 1 of the present invention will be described.

  First, a write command or an erase command and a target address signal are input from the outside to the input / output circuit 2 (step # 1). The input / output circuit 2 gives a signal input from the outside to the interface circuit 3.

  When the interface circuit 3 analyzes the signal supplied from the input / output circuit 2 and detects a write command or an erase command, the interface circuit 3 gives a write instruction or an erase instruction to the write / erase control circuit 4. The interface circuit 3 gives an address signal to the address decoder, and the address decoder responds to the address signal and a command (write or erase) given by the write / erase control circuit 4 according to a predetermined word line and A predetermined voltage application process determined for each command is applied to the bit line (step # 2).

  After the voltage application process, the write / erase control circuit 4 gives a read instruction to the target memory cell after the pulse voltage is applied in step # 2 (step # 3). Also in this case, as in the case of writing or erasing, a read operation is performed by applying a predetermined pulse voltage for reading to a predetermined word line and bit line.

  The write / erase control circuit 4 confirms (verify processing) whether or not the write or erase operation has been correctly performed in step # 2 based on the information read in step # 3 (step # 4). If the writing or erasing operation has not been performed correctly (when a writing error or erasing error has occurred: No in step # 4), the process returns to step # 2 again to perform the writing or erasing operation again. At this time, the counter circuit counts the number of repetitions of step # 2. This counter circuit is configured to temporarily hold the number of repetitions of step # 2, and at least a series of write or erase operations (that is, a series of operations according to step # 1 to step # 8) to the target memory cell is completed. It is assumed that the number of repeated executions is held until this time. That is, the information held in the counter circuit may be reset at the timing when another write or erase operation is performed on another target memory cell.

  In the verify process in step # 4, for example, in the case of a write operation, it is determined whether the information to be written input from the input / output circuit 2 matches the information read from the target memory cell. In the case of the erase operation, it may be performed by determining whether or not information indicating an erase state is read from the target memory cell.

  If it is determined in step # 4 that the write or erase operation has been performed correctly (Yes in step # 4), the information recorded in the auxiliary memory cell corresponding to the target block is read from the auxiliary memory cell array 7 (step # 6). .

  FIG. 3 is a block diagram schematically showing an example of the configuration of the auxiliary memory cell array 7. When the main memory cell array 6 is configured by assembling a plurality (units B0 to Bn) of one unit (block) composed of a plurality of main memory cells, each memory cell of the auxiliary memory cell array 7 The main memory cell array 6 is configured to correspond to each block. Further, there are separate auxiliary memory cells for storing write information and auxiliary memory cells for storing erase information.

  3, auxiliary memory cells W00, W01,..., W0m are areas in which write information in the block B0 in the main memory cell array 7 (the description of the write information will be described later) is recorded. W1m is an area in which write information in the block B1 in the main memory cell array 7 is recorded, and auxiliary memory cells Wn0, Wn1,..., Wnm are write in the block Bn in the main memory cell array 7. This is an area where information is recorded. Similarly, the auxiliary memory cells E00, E01,..., E0m are areas in which erase information in the block B0 in the main memory cell array 7 is recorded (explanation will be described later), and the auxiliary memory cells E10, E1m is an area where erase information in the block B1 in the main memory cell array 7 is recorded, and auxiliary memory cells En0, En1,..., Enm are erases in the block Bn in the main memory cell array 7. This is an area where information is recorded. In FIG. 3, the auxiliary memory cell array 7 is described as if it were configured in a matrix form of two columns and multiple rows, but this is an example, and the configuration of the matrix is that of FIG. It is not limited to.

  Here, the write information in the block B0 means the number of repetitions of the main memory cell having the largest number of repetitions of the voltage application process necessary for correctly writing information among the plurality of main memory cells belonging to the block B0. And In other words, if the voltage application process is performed at least the number of times recorded as the write information in the block B0, the write process can be correctly performed on any main memory cell belonging to the block B0. Therefore, by reading the information recorded in the auxiliary memory cells W00, W01,..., W0m, a voltage application process required at the present time for performing a correct write operation on any main memory cell belonging to the block B0. Can be recognized.

  Similarly, the erase information in the block B0 means the number of repetitions of the memory cell having the largest number of repetitions of the voltage application process necessary for correctly erasing the information among the plurality of main memory cells belonging to the block B0. And Therefore, by reading the information recorded in the auxiliary memory cells E00, E01,..., E0m, the voltage application processing required at the present time for correctly performing the erasing operation on any main memory cell belonging to the block B0. Can be recognized. The same applies to the other blocks.

  In the following description, the number of repetitions of the voltage application process necessary for correctly writing or erasing any main memory cell belonging to a certain block Y is referred to as “maximum number of repetitions”.

  In FIG. 3, a plurality of auxiliary memory cells are associated with one block for both writing information storage and erasing information storage. Based on the information recorded in the plurality of auxiliary memory cells, the maximum number of repetitions necessary at the present time for correctly performing the write operation or the erase operation on the main memory cell belonging to the target block can be recognized.

  Here, as an initial state, it is assumed that all of the plurality of auxiliary memory cells associated with one block are in an erased state (corresponding to data “1”). When the maximum number of repetitions is in the range of 0 to 9 times, the auxiliary memory cell Xi0 (X = WorE, i = 0, 1,..., M; the same applies below) is in the write state (data “0”). In the range from 10 to 19 times, the auxiliary memory cell Xi1 is further in the write state, and in the range from 21 to 29 times, the auxiliary memory cell Xi2 is further in the write state. And Further, the auxiliary memory cell Xnm is configured to be in a writing state when the maximum number of repetitions is a predetermined number (for example, 90 times) or more. Thus, one value (hereinafter referred to as “characteristic value” as appropriate) is associated with the range to which the maximum number of repetitions belongs, and the characteristic value is recorded in the auxiliary memory cell. Hereinafter, a writing method for the auxiliary memory cell will be described with reference to FIG.

  FIG. 4 is a schematic block diagram showing a recording state in the auxiliary memory cells W00 to W0m in which write information related to the block B0 is stored. For example, when the auxiliary memory cell W00 is in the write state and the auxiliary memory cells W01 to W0m are in the erased state as in the state S1, the maximum number of repetitions of the block B0 is 0 or more and 9 or less according to the rules described above. I understand that. That is, it can be seen that the number of repetitions of the voltage application process necessary to correctly perform the write operation on any main memory cell belonging to the block B0 is 0 or more and 9 or less. Similarly, when the auxiliary memory cells W00 and W01 are in the write state and the auxiliary memory cells W02 to W0m are in the erased state as in the state S2, the maximum number of repetitions of the block B0 may be 10 times or more and 19 times or less. It can be seen that the number of repetitions of the voltage application process necessary for correctly performing the write operation on any main memory cell belonging to the block B0 is 10 or more and 19 or less.

  Assume that the target block in step # 6 is the block B0, and the read action in step # 6 is caused by the first write operation to the main memory cell belonging to the block B0. In this case, as described above, when all of the auxiliary memory cells W00 to W0m are in the erased state (corresponding to the state S0 in FIG. 4), the information (characteristic value) recorded in the auxiliary memory cells W00 to W0m is read. In this state, it is recognized that the write processing has not yet been performed for any of the plurality of main memory cells belonging to the block B0 (in such a state, the maximum number of repetitions of the block B0 is hereinafter referred to as “unmeasured number” for convenience. ). At this time, the number of repetitions of the voltage application process required to correctly perform the write operation on the target memory cell in step # 5 is read from the counter circuit and compared with the maximum number of repetitions read in step # 6 ( Step # 7). For example, when the number of repetitions held in the counter circuit is 0 (that is, when writing is performed correctly by the first voltage application process), the number of repetitions measured in step # 5 is “0”. And the maximum number of repetitions “unmeasured times” read in step # 6 are different (No in step # 7), and therefore “0 times” held by the counter circuit is the maximum of the block B0. In order to record the number of repetitions, information is written in the corresponding auxiliary memory cell (step # 8), and the process is terminated. According to the rules described above, among the write information storing auxiliary memory cells W00 to W0m corresponding to the main memory cells belonging to the block B0, the memory cell W00 is set in the write state (data “0”), and the auxiliary memory cells W01 to W0m are set. Is maintained in the erased state (data “1”). That is, in FIG. 4, the auxiliary memory cells W00 to W0m transition from the state S0 to the state S1.

  Thereafter, a write instruction is issued to another main memory cell belonging to the block B0, and the voltage application process repeated until the target memory cell is correctly written is 7 times. When the characteristic value recorded in the auxiliary memory cells W00 to W0m corresponding to the block B0 is read in step # 6, it is recognized that the maximum number of repetitions related to the block B0 is 0 or more and 9 or less. Since this information is equal to the number of repeated executions “7 times”, the number of repeated executions (7 times) matches the maximum number of repetitions (0 to 9 times) represented by the read characteristic value (step # 7). Yes), the process is terminated without newly writing information to the auxiliary memory cell. On the other hand, for example, when the number of repeated executions is 11, the number of repeated executions (11) does not match the maximum number of repetitions (0 to 10) represented by the characteristic value (No in step # 7). In order to indicate that the maximum number of repetitions is “11 times or more and 20 times or less”, memory cells W00 and W01 among the write information storing auxiliary memory cells W00 to W0m corresponding to the main memory cells belonging to the block B0 are selected. The write state (data “0”) is set, and the auxiliary memory cells W02 to W0m are maintained in the erased state (data “1”) as they are. That is, actually, additional writing is performed on the auxiliary memory cell W01, and the other auxiliary memory cells W00 and W02 to W0m are maintained as they are. By performing such control, the auxiliary memory cells W00 to W0m transition from the state S1 shown in FIG. 4 to the state S2.

  Similar to the auxiliary memory cells W00 to W0m, information is written also in the other auxiliary memory cells according to such a rule, and as the maximum number of repetitions of the corresponding block increases, the auxiliary memory cells are additionally added. By sequentially writing, the maximum number of repetitions for the corresponding block can be updated. That is, when the maximum number of repetitions is updated, it is only necessary to additionally write to the auxiliary memory cell, so that the erasing process for the auxiliary memory cell is unnecessary. Therefore, after the end of the writing process to the main memory cell (that is, after the end of each step related to step # 1 to step # 5), additional processing required for updating the maximum number of repetitions (step # 6 to step # 8). Since the erasing process is unnecessary, the processing time is short, and the processing load is not additionally required for the microprocessor. Further, since the configuration is such that the erasing process is not performed on the auxiliary memory cell, the erasing means for erasing the data recorded in the auxiliary memory cell can be provided, whereby the memory is stored by the auxiliary memory cell. The number of repetitions is not erased by mistake, and the information is stabilized.

  In the case of the erasing operation, the maximum number of repetitions can be similarly updated in a short processing time by performing the same procedure as the above-described writing operation.

  Each time a write operation or an erase operation is performed in this way, the number of repeated voltage application processes performed during the write or erase operation and the characteristic value recorded in the auxiliary memory cell of the block to which the corresponding main memory cell belongs are represented. When the comparison is made with the maximum number of repetitions and the value is different from the maximum number of repetitions, the auxiliary memory cell array 7 is automatically updated so that the maximum number of repetitions is set as the number of repeated executions. Always records information about the latest maximum number of repetitions for all the blocks at the present time. Therefore, by reading the information recorded in the auxiliary memory cell array 7 separately, it becomes possible to confirm the entire write or erase characteristics of the main memory cell array 6 at the present time.

  FIG. 5 is a flowchart showing a procedure for reading information recorded in the auxiliary memory cell array 7. Hereinafter, with reference to the flowchart shown in FIG. 5, the operation procedure when reading the internal state of the main memory cell array 6 from the device 1 of the present invention will be described.

  First, an internal state read command is input from the outside to the input / output circuit 2 (step # 11). The input / output circuit 2 gives an externally input signal to the interface circuit 3, the interface circuit 3 analyzes the input signal to recognize that it is an internal state read command, and writes the internal state read command. This is given to the erase control circuit 4. The write / erase control circuit 4 gives a voltage application instruction corresponding to the read instruction to the auxiliary address decoder (row decoder 24 and column decoder 25). At this time, when an internal state read command is input from the input / output circuit 2, the type of information to be read (write information or erase information) and the target block to be read can be specified. The converted contents are converted into an address signal of the corresponding auxiliary memory cell and supplied to the auxiliary address decoder. A predetermined read voltage is applied to the word line or bit line connected to the designated auxiliary memory cell in the auxiliary address decoder. As a result, the recorded information is output from the input / output circuit 2 via the sense amplifier 32 (step # 12). If the information to be read from the input / output circuit 2 cannot be specified or if all the information is to be read, the auxiliary address decoder determines that all the auxiliary memory cells constituting the auxiliary memory cell array 7 are used. Thus, the read voltage can be sequentially applied, and such information can be output from the input / output circuit 2 via the sense amplifier 32.

  By analyzing the information recorded in the auxiliary memory cell read from the input / output circuit 2 in this manner, the maximum number of repetitions (strictly speaking, the maximum number of repetitions) for each block constituting the main memory cell array 6 is analyzed. Range). Therefore, when a write or erase process is repeatedly performed on a predetermined main memory cell or a main memory cell belonging to a predetermined block, the maximum number of repetitions of the block is larger than the maximum number of repetitions of other blocks. Therefore, by confirming the information read from the auxiliary memory cell array 7, it is possible to recognize such a state at a stage before writing or erasing failure occurs. Therefore, since a measure can be taken not to use the main memory cell belonging to the block before a write failure or an erase failure occurs, a write error or an erase error does not occur without causing a write error or an erase error. Compared with the conventional method of designating an alternative block when this occurs, the burden on the microprocessor can be greatly reduced.

  In the above-described embodiment, every time the number of repetitions exceeds 10, a writing process is performed on a different auxiliary memory cell. However, the rule regarding writing of the auxiliary memory cell is an example, and It is not limited. For example, as the number of repetitions increases, the writing interval for a new auxiliary memory cell may be shortened, or conversely, it may be lengthened. In particular, by adopting the latter configuration, for example, there is an initial failure in some main memory cells, and a write process is performed on the memory cells even though not much time has passed since the start of use. Alternatively, when it is necessary to repeat the voltage application process in order to correctly perform the erasing process, writing to the auxiliary memory cell is newly performed only by increasing the number of repetitions by several times. The fact that the number of repetitions of the block to which the main memory cell belongs is larger than that of the other blocks can be immediately recognized by reading the recording state of the auxiliary memory cell array 7, and the existence of such a defective state. Can know immediately. In addition, writing may be performed on a new auxiliary memory cell every time the number of repetitions increases by one according to the range of the number of repetitions or over the entire range. In the case of this configuration, the characteristic value recorded in the auxiliary memory cell matches the number of repetitions as it is.

The block diagram which shows schematic structure of this invention apparatus The flowchart which shows the operation | movement procedure at the time of writing or erasing information with respect to this invention apparatus. A block diagram schematically showing a configuration example of an auxiliary memory cell array The figure for demonstrating the writing method with respect to an auxiliary memory cell A flowchart showing a procedure for reading information recorded in the auxiliary memory cell array

Explanation of symbols

1: Nonvolatile semiconductor memory device according to the present invention 2: Input / output circuit 3: Interface circuit 4: Write / erase control circuit 6: Main memory cell array 7: Auxiliary memory cell array 21: Block decoder 22: Row decoder 23: Column decoder 24: Row decoder 25: Column decoder 31: Sense amplifier 32: Sense amplifier

Claims (8)

A plurality of nonvolatile main memory cells for storing user data;
An address decoder for selecting a target memory cell to be written or erased from among the plurality of main memory cells;
A plurality of non-volatile auxiliary memory cells storing an internal state indicating a write or erase characteristic of the main memory cell for each block which is a structural unit constituted by a predetermined number of the main memory cells;
A write / erase control circuit for controlling the writing or erasing of the user data to the target memory cell, and for controlling the writing of the internal state to the auxiliary memory cell,
The write / erase control circuit comprises:
When an instruction for writing or erasing the target memory cell is given, control is performed to repeatedly execute a voltage application process for writing or erasing the target memory cell until data writing or erasing is completed. Control for writing the characteristic value indicating the number of repetitions of the voltage application process required by the target memory cell until the writing or erasing is completed to the auxiliary memory cell corresponding to the block to which the target memory cell belongs. A non-volatile semiconductor memory device. The write / erase control circuit comprises:
A counter circuit that counts the number of repetitions of the voltage application process and temporarily records the number of repeated executions counted;
When a write or erase instruction is given to the target memory cell, control is performed to write or erase data to the target memory cell, and the number of repeated executions recorded in the counter circuit after the execution And the repetition count represented by the characteristic value recorded in the auxiliary memory cell corresponding to the block to which the target memory cell belongs. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the control is performed to write the corresponding auxiliary memory cell as the characteristic value in the block to which the target memory cell belongs. A plurality of the auxiliary memory cells corresponding to the same block exist;
3. The nonvolatile semiconductor memory device according to claim 2, wherein the write / erase control circuit designates the different auxiliary memory cell as a write destination according to a range of the number of repetitions of the target memory cell. As the auxiliary memory cells corresponding to the same block, each has a write information storage auxiliary memory cell and an erase information storage auxiliary memory cell,
When the write / erase control circuit is instructed to write to the target memory cell, the write information storage auxiliary memory cell is designated as the write destination of the characteristic value, and the erase instruction to the target memory cell is given. 4. The nonvolatile semiconductor memory device according to claim 2, wherein, when the data is written, the auxiliary memory cell for erasing information storage is designated as a write destination of the characteristic value. 5.   5. The nonvolatile semiconductor memory according to claim 2, wherein the block includes a plurality of the main memory cells that are simultaneously erase-controlled by the write / erase control circuit. 6. apparatus. A memory cell array in which a plurality of main memory cells are arranged in a matrix in the row direction and the column direction, a plurality of word lines to which the main memory cells in the same row are connected in common, and the main columns in the same column A plurality of bit lines to which memory cells are connected in common,
The address decoder selects the word line and the bit line connected to the target memory cell corresponding to the address specified by the input address signal;
6. The write / erase control circuit performs control of applying a predetermined voltage to the selected bit line, thereby writing or erasing the target memory cell. The nonvolatile semiconductor memory device according to any one of the above.   The write / erase control circuit performs the comparison process between the number of repetitions represented by the characteristic value read from the auxiliary memory cell selected based on the address signal and the number of repetitions. The nonvolatile semiconductor memory device according to claim 6.   8. The nonvolatile semiconductor memory device according to claim 1, further comprising an output circuit that outputs the characteristic value recorded in each of the plurality of auxiliary memory cells. 9.

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