JP2007250090A - Automatic replacement method for defective cell in nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an automatic replacement method for a defective cell in a nonvolatile semiconductor memory device by which even when a defective cell occurs when data in use by a user are erased, the defective cell can be automatically replaced with a redundant cell by the device itself. <P>SOLUTION: The automatic replacement method for the defective cell in the nonvolatile semiconductor memory device includes: steps (S17 and S18) in which replacement permitting information showing that an unused redundant cell is used for replacement and a replacement address being the address of a memory cell showing that the memory cell has been replaced with the unused redundant cell, are written on a volatile memory corresponding to the unused redundant cell; and steps (S16-2 and S18-2) in which when memory cells other than the above memory cell are desired to read out during the period of the steps (S17 and S18), the read of the unused redundant cell is inhibited. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for automatically replacing a defective cell in a nonvolatile semiconductor memory device having a redundant cell for replacing a defective cell, and more particularly to a nonvolatile semiconductor memory for replacing a defective cell detected at the time of data erasure with a redundant cell. The present invention relates to a method for automatically replacing defective cells in an apparatus.

  In a nonvolatile semiconductor memory device typified by a flash memory, a redundant cell for replacing a defective cell is generally mounted as a measure for improving the yield as the memory capacity increases.

  There are three types of redundant cells mounted in a nonvolatile semiconductor memory device: column redundancy that relieves defects in bit lines, row redundancy that relieves defects in word lines, and block redundancy that relieves defects in blocks. It is common. These types and their numbers are determined from various viewpoints such as process, failure mode, chip size, and repair rate.

  In general, defective cells are found by screening before shipment and replaced with redundant cells to reduce the defective rate. However, this requires a lot of test time and enormous test costs. The usage rate of the redundant cell is most often shortly after the trial production, and is relatively low at the time of mass production when the process is stable, and the usage rate is stabilized at a low level.

  Even after shipment to the market, if the number of times of writing and erasing increases during user use, various characteristics of the flash cell deteriorate, and defective cells that cannot be used appear. Defects due to rewriting of data during user use exist on the order of tens to hundreds of ppm.

  As a result, there are many cases where a defective product is used even though there are redundant cells that can be used in the nonvolatile semiconductor memory device (chip) when used by the user.

In relation to the technology described above, the defective address is automatically identified, and whether the defective content of the defective address is a row defect, a column defect, or a bit defect is automatically recognized and replaced with a redundant cell. Has already been proposed (see Patent Document 1), which automatically suppresses the increase in the test process and test cost. However, a specific method for automatically replacing a defective cell at the time of user use after shipment is not shown.
Japanese Patent Application Laid-Open No. 2000-57995

  The present invention provides a method for automatically replacing a defective cell in a nonvolatile semiconductor memory device, which can automatically replace a defective cell with a redundant cell even when a defective cell occurs during data erasing during user use. .

  According to the aspect of the defective cell automatic replacement method in the nonvolatile semiconductor memory device of the present invention, there is an unused redundant cell when the erase operation is not completed even after a predetermined time has elapsed after the erase operation on the memory cell is started. A step of determining whether or not when there is an unused redundant cell, a step of determining whether or not the memory cell has already been replaced with a redundant cell, and the memory cell has already been replaced with a redundant cell. In the volatile memory corresponding to the replaced redundant cell, replacement prohibition information indicating that the replaced redundant cell is prohibited to be replaced is written, and memory cells other than the memory cell are read during that time. If so, the step of prohibiting reading of the replaced redundant cell, and the step corresponding to the unused redundant cell are performed. Replacement permission information indicating that the unused redundant cell is used for replacement in the memory, and a replacement address which is an address of the memory cell indicating that the memory cell is replaced with the unused redundant cell In the meantime, when reading memory cells other than the memory cells, the unused redundant cells are prohibited from being read, and the non-volatile memory corresponding to the unused redundant cells is replaced with And writing the permission information and the replacement address, and re-starting the erasing operation when it is determined that it has been written correctly.

  According to the aspect of the defective cell automatic replacement method in the nonvolatile semiconductor memory device of the present invention, there is an unused redundant cell when the erase operation is not completed even after a predetermined time has elapsed after the erase operation on the memory cell is started. A step of determining whether or not when there is an unused redundant cell, a step of determining whether or not the memory cell has already been replaced with a redundant cell, and the memory cell has already been replaced with a redundant cell. A first flag information indicating that the replaced redundant cell is a defective cell, and an address of the replaced redundant cell when the memory cell has already been replaced by a redundant cell. And storing the first address in the first register and the first flag information when receiving an interrupt processing instruction A step of determining whether or not data has been written; and a volatility corresponding to the redundant cell at the first address when it is determined that the first flag information has been written, upon receiving an interrupt processing instruction And erasing replacement prohibition information indicating that the redundant cell at the first address is prohibited to be replaced.

  According to the aspect of the defective cell automatic replacement method in the nonvolatile semiconductor memory device of the present invention, there is an unused redundant cell when the erase operation is not completed even after a predetermined time has elapsed after the erase operation on the memory cell is started. A step of determining whether or not when there is an unused redundant cell, a step of determining whether or not the memory cell has already been replaced with a redundant cell, and the memory cell has already been replaced with a redundant cell. A first flag information indicating that the replaced redundant cell is a defective cell, and an address of the replaced redundant cell when the memory cell has already been replaced by a redundant cell. Storing the first address in the first register and the memory cell is already replaced by a redundant cell Writing replacement prohibition information indicating that the replaced redundant cell is prohibited to be replaced in a nonvolatile memory corresponding to the replaced redundant cell, and further determining whether or not it has been correctly written; A step of writing second flag information indicating that the replacement prohibition information has been correctly written when it is determined that the replacement prohibition information has been correctly written; A step of storing a second address, which is an address of an unused redundant cell to be replaced, in the second register, and the second address is stored in the second register when an interrupt processing instruction is received. A step of determining whether or not the first flag information has been written after the step of storing in the memory, and an interruption process When a command is received and it is determined that the first flag information has been written, the command is written in the volatile memory corresponding to the redundant cell of the first address, and the redundancy of the first address is And a step of erasing the replacement prohibition information indicating that the cell is prohibition of replacement.

  According to the present invention, there is provided a method for automatically replacing a defective cell in a nonvolatile semiconductor memory device, in which even if a defective cell occurs during data erasing during user use, the device itself can automatically replace the defective cell with a redundant cell. It is possible to provide.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals.

  In the embodiment of the present invention, a block that has failed to be erased in an erase operation in a nonvolatile semiconductor memory device is automatically relieved with block redundancy (auto block redundancy). A block is an erasing unit for erasing at the time of erasing, and has a plurality of memory cells. Block redundancy is a redundant block used to replace a defective block when the block is defective.

  In each of the following embodiments, simultaneous read (Dual-Read) execution, reset (Reset), suspend (Suspend), and resume (Resume) can be input to the nonvolatile semiconductor memory device when auto block redundancy is being executed. ) How to deal with each command is explained.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the nonvolatile semiconductor memory device 1000 according to the first embodiment. As shown in FIG. 1, a nonvolatile semiconductor memory device 1000 includes a memory cell array including a main body cell array 1 and a redundancy array 2, a control circuit 3, hit (HIT) signal generation circuits 100 to 10n, a write and erase circuit 4, and an OR circuit. 5, an AND circuit 6, a decoder 7, a timer 8, a verify circuit 9, and a read control circuit 11.

  The hit signal generation circuits 100 to 10n are provided corresponding to the n blocks included in the redundancy array 2, and there are n hit signal generation circuits 100 to 10n.

  Each hit signal generation circuit, for example, the hit signal generation circuit 100 includes a volatile memory (latch) 10, a nonvolatile memory (fuse ROM) 20, a redundancy address comparison circuit 30, AND circuits 60, 80, 90, and a NAND circuit 70, respectively. Prepare.

  In the main cell array 1, a plurality of blocks (BLK0, BLK1,..., BLKm) 11A are arranged. A sense amplifier 11B is connected to each of the blocks (BLK0, BLK1,..., BLKm) 11A, and a decoder 7 is also connected to each block.

  Each of the blocks (BLK0, BLK1,..., BLKm) 11A includes a plurality of memory cells, and the memory cells in the block are erased at a time during the erase operation. The decoder 7 decodes the read block address output from the control circuit 3 and selects a block specified by the block address. However, an AND circuit 6 is interposed between the control circuit 3 and the decoder 7, and when a hit signal described later is generated, a block in the main body cell array 1 is not selected. The sense amplifier 11B detects a signal read from the memory cell in the block, amplifies it, and outputs it to the verify circuit 9 and the read control circuit 11.

  In the redundancy array 2, a plurality of redundant blocks (R / D0, R / D1,..., R / Dn) 12A are arranged. Hit signal generation circuits 100 to 10n and a sense amplifier 12B are connected to the redundant block (R / D0, R / D1,..., R / Dn) 12A, respectively. Each of the redundant blocks (R / D0, R / D1,..., R / Dn) 12A includes a plurality of memory cells, and the memory cells in the redundant block are erased collectively during the erase operation. When the hit signal generation circuit 100 is taken as an example, the hit signal generation circuits 100 to 10n select a redundant block designated by the hit signal output from the redundancy address comparison circuit 30. However, the hit signal can be masked as will be described later by the AND circuit 90. The sense amplifier 12B detects a signal read from the memory cell in the redundant block, amplifies it, and outputs it to the verify circuit 9 and the read control circuit 11.

  The nonvolatile memory, for example, the nonvolatile memory 20 included in each of the hit signal generation circuits 100 to 10n is a block address of a defective block in the block 11A of the main cell array 1 replaced with the redundant block 12A, and replacement of the redundant block. Permission information (Enable bit) and replacement prohibition information (Disable bit) are stored. Since the flash memory itself is a non-volatile memory, the replacement information needs to be retained even when the power supply is cut off, and is stored in the non-volatile memory.

  FIG. 2 shows a bit configuration of the nonvolatile memory 20. The nonvolatile memory 20 has a storage set S0, and the storage set S0 corresponds to the redundant block R / D0. In the storage set, the replaced block address and the usage information of the corresponding redundant block are written, and the usage status of the redundant block can be confirmed by reading out the information. The storage set has, for example, an 11-bit bit string from 0 to 10, and the block address (hereinafter referred to as replacement address) of the defective block replaced with the redundant block corresponding to this storage set is stored in the 0th to 8th ranks. In the ninth place, a replacement prohibition bit (Disable) indicating that the replacement of the redundant block corresponding to the storage set is prohibited is stored, and in the tenth position, the redundant block corresponding to the storage set is used for replacement. A replacement permission bit (Enable) indicating that the data is stored is stored.

  Therefore, the non-volatile memory included in each of the n hit signal generation circuits 100 to 10n has a plurality of storage sets S0 to Sn as a whole, and each of the storage sets S0 to Sn is a redundant block R / D0 to R /. It corresponds to each of Dn. This is summarized in one table as shown in FIG.

  The replacement address stored in the nonvolatile memory 20 is written and stored in the volatile memory 10 together with the replacement permission bit and the replacement prohibition bit. The volatile memory 10 outputs the replacement address to the redundancy address comparison circuit 30. When a read block address is output to read a specific block from the control circuit 3, the redundancy address comparison circuit 30 outputs the read block address output from the control circuit 3 and the replacement address output from the volatile memory 10. Compare When the two addresses match, the redundancy address comparison circuit 30 outputs a hit signal to one input of the AND circuit 90.

  The output of the AND circuit 80 is input to the other input of the AND circuit 90, and the outputs of the AND circuit 60 and the NAND circuit 70 are input to the AND circuit 80. The AND circuit 60 is supplied with a replacement permission bit and a replacement prohibition bit stored in the volatile memory 10 via signal lines 40 and 50, respectively.

  Accordingly, the AND circuit 60 sends an affirmative signal to the AND circuit 80 when the replacement permission bit is written and the replacement prohibition bit is not written. At that time, if a mask to be described later is not applied from the NAND circuit 70, the redundant block R / D0 is selected as a block to be read when the redundancy address comparison circuit 30 outputs a hit signal. In this case, the OR circuit 5 and the AND circuit 6 in FIG. 1 mask the blocks in the main cell array 1 so that they cannot be read out. When no hit signal is generated from any of the hit signal generation circuits 100 to 10n, the block in the main body cell array 1 designated by the block address is selected.

  When storing the replacement information, that is, the replacement permission bit, the replacement prohibition bit, and the replacement address in the nonvolatile memory 20, the replacement information to be stored exists in a general-purpose register (not shown) in the control circuit 3. Therefore, first, replacement information is written from the control circuit 3 to the volatile memory 10, and then data of the volatile memory 10 is written to the nonvolatile memory 20.

  Whether or not the written data has been correctly stored (verify) is determined by checking whether the data in the nonvolatile memory 20 is stored once in the volatile memory 10 and read by the control circuit 3 to match the written data. It is done by judging.

  The write / erase circuit 4 writes data to the memory cells in the main cell array 1 and the redundancy array 2 or erases the blocks in the main cell array 1 and the redundant blocks in the redundancy array 2. The verify circuit 9 verifies whether writing or erasing has been normally performed after the writing operation or the erasing operation, and outputs the verification result to the control circuit 3.

  In addition, the timer 8 measures the elapsed time from the start of the operation and makes the control circuit 3 recognize the elapsed time. For example, the timer 8 measures the elapsed time from the start of the erase operation on the block or redundant block by the write and erase circuit 22 and notifies the control circuit 3 that the elapsed time has exceeded a predetermined time. Further, the control circuit 3 controls the operations of the hit (HIT) signal generation circuits 100 to 10 n, the write and erase circuit 4, the timer 8, the verify circuit 9, and the read control circuit 11 in the nonvolatile semiconductor memory device 1000. .

  Next, the erase operation in the nonvolatile semiconductor memory device 1000 of the first embodiment will be described.

  FIG. 4 is a flowchart showing the erasing operation in the nonvolatile semiconductor memory device 1000, and FIG. 5 is a flowchart showing the operation of the “automatic redundancy block replacement (auto block redundancy) routine” in the erasing operation. The "automatic redundant block replacement routine" is installed redundantly when it detects that a certain period of time has elapsed since the start of the erase operation of the block when the erase operation cannot be completed due to a bad block that can no longer be used. This is a routine for automatically replacing a flash cell block with a defective block.

  The operations shown in the flowcharts of FIGS. 4 and 5 are executed by controlling each circuit in the apparatus by the control circuit 3. Here, as described above, an example will be described in which a block (defective block) that has failed to be erased in the erasing operation is automatically replaced with a redundant block to repair the defective block.

  As shown in FIG. 4, an erase command for a part of the memory cell array is input to the control circuit 3 (step S1), and the erase operation is started. Here, the block address to be erased is, for example, a block in which addresses from “BLKx1” to “BLKxk” are continuous.

  First, the control circuit 3 sets the block address BA of the read block address to “BLKx1” (step S2). Next, erasure of the block is started (step S3). In block erasing, for example, the writing and erasing circuit 4 sequentially executes the following pre-erasing writing (preprogramming), erasing, and weak writing.

  As the threshold value of the memory cell in one block, “1” (erased state) or “0” (written state) is mixed. First, writing before erasure is performed so that the threshold values of all the memory cells in one block are set to “0” (programming state) equal to or higher than the program verify voltage. Next, batch erasure is performed on all the memory cells in the block. With this operation, the threshold values of all the memory cells in one block are lowered to an erase verify (EV) voltage or lower. At this time, there may be a memory cell (over-erased cell) whose threshold value is too low at the time when the batch erasing operation is completed. Therefore, weak writing (Weak Program) is performed on the memory cell whose threshold value is lower than the over-erase verify (OEV) voltage set to a voltage value lower than the erase verify voltage. Thereafter, erasing and weak writing are repeated until it can be confirmed that the threshold values of all the memory cells are distributed in a region higher than the overerase verify voltage and lower than the erase verify voltage.

  Here, when a defective cell is generated in a cell in the block, the above-described repetitive operation is not completed. Accordingly, block erasure is started in step S3, and if it is determined that erasure of the block does not end even if a predetermined time (for example, 2 seconds) exceeds a predetermined time as measured by the timer 8, automatic redundancy block replacement is performed. The (auto block redundancy) routine is entered (steps S4 to S6). That is, when executing the erase operation, if the erase execution time exceeds the predetermined time, it is determined that the block to be erased is a defective block, and the automatic redundant block replacement routine is entered.

  On the other hand, when the block erase is completed, it is determined whether or not the block address BA is the last address “BLKxk” of the block to be erased (step S7). When the block address BA is the last address, the erase operation is terminated. On the other hand, when the block address BA is not the last address, the block address BA is incremented (step S8), and erasure of a new block is started.

  With the above steps S2 to S8, block erasure is performed on the block to be erased. Then, as described above, when block erasure is started for any of the blocks and the erasure of the block is not completed even if the predetermined time is exceeded, the routine proceeds to an automatic redundant block replacement routine.

  The “automatic redundant block replacement routine” will be described below with reference to FIG.

  First, the control circuit 3 reads replacement information of each volatile memory (for example, the volatile memory 10) of each hit signal generation circuit 100 to 10n, and whether there is an unused storage set, that is, an unused redundant block. Determine whether or not. Thereby, it is searched whether or not there is a vacancy in the redundant block (step S11). Specifically, this is performed by checking whether there is a storage set in which neither the replacement enable bit nor the replacement prohibition bit is written.

  The availability of redundant blocks also depends on the use status of redundant blocks at the time of a shipping test. If there is no free space in the redundant block (all used), timeout error processing is performed.

  On the other hand, if there is a vacancy in the redundant block, it is determined whether the replacement target block, that is, the defective block is a redundant block that has already been replaced (step S12).

  If the block to be replaced is not a redundant block, the process proceeds to step S15. If the block to be replaced is a redundant block, replacement information indicating that the redundant block is used for replacement is deleted. Specifically, writing is performed to the replacement prohibition bit of the storage set in the nonvolatile memory in the hit signal generation circuit corresponding to the redundant block (step S13).

  The deletion of the replacement information originally corresponds to an erasing operation. However, since erasure in the non-volatile memory has a longer execution time than writing, the replacement information is deleted by providing a replacement prohibiting bit and writing to the bit. That is, the replacement information is invalidated while the replacement permission bit is still written.

  As described above, in the case of, for example, the redundant block R / D0, this writing is first performed by the control circuit 3 to the replacement prohibiting bit of the volatile memory 10, and then from the volatile memory 10 to the nonvolatile memory 20. Is written.

  Next, a determination (verification) is made as to whether the writing to the nonvolatile memory 20 has been correctly executed. That is, contrary to the above, the storage set in the non-volatile memory 20 is read out to the volatile memory 10, and whether or not the data in the volatile memory 10 matches the data that the control circuit 3 tried to write into the non-volatile memory 20. The control circuit 3 determines. That is, it is determined whether or not the replacement prohibition bit has been normally written (step S14). If the replacement prohibition bit has been written normally, the process proceeds to step S15.

  In step S15 and subsequent steps, a redundant block that is not used, that is, an empty block is found, and a block to be erased (bad block) is replaced with a redundant block that is not used. More specifically, in step S15, the address N of the redundant block is set to “0”. Next, it is determined whether or not the redundant block specified by the address N can be used (step S16). Specifically, it is checked whether or not both the replacement permission bit and the replacement prohibition bit are written, and if they are not written together, they can be used.

  If the redundant block at address N is not used, the replacement address is written to the storage set in the nonvolatile memory corresponding to the redundant block, and then the replacement permission bit is written (step S17). In this writing, similarly to step S13, the replacement address and the replacement permission bit are once written in the volatile memory and then written in the nonvolatile memory. At this time, the block address BA of the block to be erased is written as a replacement address.

  Subsequently, as in step S14, the control circuit 3 compares the replacement address and replacement permission bit output from the volatile memory corresponding to the redundant block at the address N with information to be written in the nonvolatile memory, and replaces the replacement address. Then, it is determined (verified) whether or not the replacement permission bit has been normally written in the storage set of the nonvolatile memory (step S18).

  When the replacement address and the replacement permission bit are normally written, the process proceeds to step S4, and the block erase is started again. This completes the automatic redundant block replacement routine. After all the erase operations are completed, the verify circuit 9 verifies whether or not the erase has been normally performed, and outputs the verification result to the control circuit 3.

  On the other hand, if the replacement address and the replacement permission bit are not normally written, writing is performed to the replacement prohibition bit of the nonvolatile memory corresponding to the redundant block at the address N (step S19). More specifically, if the replacement address and the replacement permission bit are not normally written, the writing is repeated within the set number of times, and when the number of times is exceeded, the redundant block is unusable and the replacement prohibiting bit is written. This writing is also performed after once writing to the volatile memory, as in step S13.

  Subsequently, it is determined whether or not the replacement prohibition bit is normally written (step S20). This process is also the same as step S14.

  If the replacement prohibition bit has been written normally, the process proceeds to step S21 to search for another redundant block that can be replaced. First, it is determined whether or not the address N is the last address, that is, the address of the redundant block R / Dn (step S21). When address N is the last address, timeout error processing is performed because there is no redundant block that is not used. On the other hand, when the address N is not the last address, the address N is incremented (step S22), the process proceeds to step S16, and it is determined again whether or not the redundant block at the address N is used (step S16). After step S16, the same processing as described above is repeated. In step S20, if the replacement prohibition bit is not normally written, timeout error processing is performed.

  It should be noted that an automatic replacement recognition bit indicating replacement by an automatic redundant block replacement routine is further provided in the storage set of the non-volatile memory, and if this automatic replacement recognition bit is written in step S17, the test in the test process is performed. It is possible to distinguish between replacement and replacement by an automatic redundant block replacement routine. Thereby, the traceability of the nonvolatile semiconductor memory device can be improved. When returned as a defective product, it is possible to distinguish between the redundant block usage rate in the test process and the redundant block usage rate in the automatic redundant block replacement routine, which can be used for determining conditions such as a stress test.

  Further, if an unused redundant block, in this case, a redundant block used for replacement is previously erased in the test process, it is not necessary to erase the redundant block after writing to the non-volatile memory 20. The operation time can be greatly shortened. That is, after the process in step S18, the process moves to step S4, and it is not necessary to perform the erase operation on the replaced redundant block, and the process can directly move to step S8, so that the erase time can be shortened.

  Furthermore, if an unused redundant block is defective, it is possible to reduce the erase time by writing in a replacement prohibiting bit in advance and preventing erroneous selection in a series of "automatic redundant block replacement routine" processing. High speed can be achieved. In addition, since it is necessary to perform a test without using the “automatic redundant block replacement routine” in the test process before shipment, a means for selecting whether or not to execute the “automatic redundant block replacement routine” may be provided. Good.

  By the way, in the nonvolatile semiconductor memory device, it is generally possible to read blocks other than the block to be erased even during the erase operation. Therefore, during execution of the automatic redundant block replacement routine, it is necessary to be able to perform read-out (Dual-Read) execution in which blocks other than the block to be erased are read.

  However, since the replacement information has a bit width, a skew occurs when the replacement information is stored in the nonvolatile memory cell via the volatile memory. As a result, since it takes time to store accurate replacement information, it is necessary to prevent problems during reading of blocks other than the block to be erased during this time.

  In the automatic redundant block replacement routine, the contents of the volatile memory may become unstable and inaccurate in the following cases. When data is written from the control circuit 3 to the volatile memory in any one of the hit signal generation circuits 100 to 10n, or when the write to the nonvolatile memory is correctly executed (verification), the storage content of the nonvolatile memory is volatilized. This is the case when data is written to the memory.

  The read block address is sent to all the hit signal generation circuits 100 to 10n, and as described above, a hit signal is generated based on the replacement address stored in the volatile memory. Therefore, a hit signal generation circuit having a volatile memory in a state of storing an incorrect replacement address can generate an erroneous hit signal when a read block address is output from the control circuit 3 as simultaneous execution of reading. There is sex.

  To avoid this. In the present embodiment, the hit signal is masked so that the hit signal is not generated based on the replacement address stored in the volatile memory in which writing is being performed while the volatile memory is being written. multiply.

  Specifically, in the flowchart of FIG. 5, a period including the steps “write of **” and “was ** written?”, That is, a period of steps S13 and S14, a step S17 and a step. A mask signal as shown in FIG. 6 is applied to the signal line 200 of FIG. 1 during the period of S18 and further during the period of steps S19 and S20. The signal line 200 is connected to all the hit signal generation circuits 100 to 10n and is configured to send the same mask signal.

  At the same time, since the control circuit 3 knows which redundant block is currently being operated for replacement information, the current replacement information among the signal lines 300 to 30n connected to the hit signal generation circuits 100 to 10n. A signal can be sent to the signal line connected to the hit signal generation circuit that is operating during the operation.

  FIG. 7 shows a flowchart in which the above operation is added to FIG. In step S12-2 and step S16-2, masking is started on the signal line 200 as shown in FIG. 6, and masking is ended in step S14-2, step S18-2, and step S20-2.

  As a result, the NAND circuit 70 of the hit signal generation circuit 100 and the NAND circuits of the other hit signal generation circuits mask the redundant blocks that are currently operating the replacement information so that no hit signal is generated. Can do.

  The contents of the block that has received the read instruction is output to the read control circuit 11 as a read data output. If the user mistakenly tries to read a block to be erased, the control circuit 3 controls the read control circuit 11 to output a sequence flag indicating the reading of the block to be erased.

  According to this embodiment, in the “automatic redundant block replacement routine” during the erasing operation, the volatile memory in the hit signal generation circuit of the redundant block that is currently operating the replacement information stores an incorrect value However, it is possible to avoid generating an erroneous hit signal for simultaneous execution of reading. As a result, even if a defective cell occurs during user use, the device itself can automatically replace the defect with a redundant cell, so that it is possible to greatly reduce the defects that occur after market shipment, Simultaneous read execution during the erase operation can be performed accurately.

(Second Embodiment)
Next, a defective cell automatic replacement method in the nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described.

  In this embodiment, when the nonvolatile semiconductor memory device is in the “automatic redundancy block replacement routine” in the erase operation described in the first embodiment, an interrupt processing command such as reset is input. Assume the case.

  In general, when the replacement information is interrupted while the replacement information is being written in the nonvolatile memory, the replacement information is set in the volatile memory without guaranteeing whether the information has been correctly written in the nonvolatile memory. If the information stored in the volatile memory is accurate, a hit signal is generated so that it can be replaced with a redundant block suitable for reading to the defective block until the power is turned off. Then there is no guarantee that it will be replaced properly. In addition, if it was interrupted while checking whether data could be written correctly to the non-volatile memory, there was a possibility that the data that was being written to the volatile memory was interrupted and the unintended block was replaced with a redundant block. .

  As described in the first embodiment, since replacement information is stored in a nonvolatile memory cell via a volatile memory, it takes time to store accurate replacement information. There is a need to. Unless the power is turned off, the state of the nonvolatile memory can be corrected from the information of the volatile memory. Therefore, it is desirable to return the state of the volatile memory to a state where the current state can be restored as much as possible in order to operate again.

  The configuration of the nonvolatile semiconductor memory device according to the second embodiment is shown in FIG. 1 is different from FIG. 1 showing the configuration of the nonvolatile semiconductor memory device of the first embodiment in that the first flag storage unit 401 and the first register 410 are further connected to the control circuit 3. Others are the same as FIG. The first flag storage unit 401 and the first register 410 may be included in the control circuit 3.

  FIG. 9 is a flowchart showing an “automatic redundant block replacement routine” of the nonvolatile semiconductor memory device including the operation of the present embodiment. FIG. 9 is different in that step S12-2 and step S12-3 described below are added to the automatic redundant block replacement routine shown in FIG.

  When it is determined in FIG. 9 whether or not the defective block is a redundant block that has been replaced (step S12), the control circuit 3 determines that the defective block is a redundant block. First flag information indicating that the redundant cell is a defective cell is written in the first flag storage unit 401 (step S12-2). Next, the address of the redundant block that has been replaced and has become defective is stored in the first register 410 (step S12-3).

  If the defective block is a redundant block, a defect has already been found in the inspection prior to shipment and has been replaced with a redundant block. There may be a case where a defect has occurred due to replacement with a block.

  FIG. 10 is a flowchart showing the operation of this embodiment when an interruption command such as reset is accepted. When an interruption command such as reset or suspend is input during the automatic redundant block replacement routine, it is confirmed whether or not the first flag information is written in the first flag storage unit 401 (step 31). Here, when it is confirmed that the first flag information is written, writing is performed to the replacement permission bit of the volatile memory of the redundant block of the address stored in the first register 410 (step 32). Then, the replacement prohibition bit in the volatile memory of the redundant block at the address stored in the first register 410 is erased (step 33).

  According to this embodiment of the present invention, when the same block is erased again after the interruption, the same replaced redundant block can be seen again. Therefore, in the erase operation, the cell is detected again as a defective cell, and the “automatic redundant block replacement routine” is executed again, and the above-described problem can be avoided.

(Third embodiment)
Next explained is a defective cell automatic replacement method in the nonvolatile semiconductor memory device according to the third embodiment of the invention.

  In the present embodiment, when the nonvolatile semiconductor memory device is in the “automatic redundancy block replacement routine” in the erase operation described in the first embodiment, the suspend and resume commands, that is, the suspend process And a case where a command for a return process is input. In this case as well, the state of the nonvolatile memory can be corrected from the information in the volatile memory as long as the power is not turned off, so the volatile memory is used for returning to the "automatic redundant block replacement routine" operation after accepting the resume command. It is desirable to return the state of the volatile memory to a state where it can be restored as much as possible.

  FIG. 11 shows a configuration of a nonvolatile semiconductor memory device according to the third embodiment. The second flag storage unit 402 and the second register 420 are further connected to the control circuit 3, which is different from FIG. 8 showing the configuration of the nonvolatile semiconductor memory device of the second embodiment. Same as 8. The first flag storage unit 401, the second flag storage unit 402, the first register 410, and the second register 420 may be included in the control circuit 3.

  FIG. 12 is a flowchart showing an “automatic redundant block replacement routine” of the nonvolatile semiconductor memory device including the operation of the present embodiment. FIG. 12 is different in that step S14-2 described below is added to the automatic redundant block replacement routine shown in FIG.

  Also in the present embodiment, as in the second embodiment, it is determined whether the defective block is a redundant block that has been replaced (step S12), and it is determined that the defective block is a redundant block. When it is, the control circuit 3 writes the first flag information indicating that the redundant cell is a defective cell in the first flag storage unit 401 (step S12-2). Then, the address of the redundant block that has been replaced and has become defective is stored in the first register 410 (step S12-3).

  Thereafter, writing is performed to the replacement prohibition bit in the nonvolatile memory provided in the hit signal generation circuit corresponding to the defective redundant block (step S13). Further, it is determined (verify) whether or not the writing to the nonvolatile memory has been correctly executed (step S14). If the replacement prohibition bit is correctly written, the control circuit 3 writes second flag information indicating that in the second flag storage unit 402 (step S14-2).

  FIG. 13 is a flowchart showing the operation of the present embodiment when a suspend command, which is an interrupt command based on the assumption that a return (resume) command is accompanied, is accepted. When a suspend command is input during the automatic redundant block replacement routine, first, the address of the redundant block to be replaced when the command is input is stored in the second register 420 (step S41).

  Next, it is determined whether or not the first flag information is written in the first flag storage unit 401, that is, whether or not the replaced redundant block is a defective block (step S42). If the first flag information has been written, then whether or not the second flag information has been written to the second flag storage unit 402, that is, the replacement prohibition bit of the redundant block to the nonvolatile memory is set. It is determined whether writing has been executed (step S43).

  If the second flag information is not written, the process immediately goes to step S46. When the second flag information is written, the replacement permission bit of the volatile memory of the redundant block of the address stored in the second register, that is, the redundant block to be replaced when the suspend command is input is erased. (Step S44). Further, the replacement prohibiting bit of the volatile memory of the redundant block is also erased (step S45), and the process goes to step S46.

  In step S46, the redundancy block of the address stored in the first register, that is, the write to the replacement permission bit of the volatile memory of the redundant block that has been replaced, which has become defective is written (step S46). The replacement prohibiting bit of the volatile memory is erased (step S47).

  Even if the operation described in the flowchart of FIG. 13 is not accompanied by a return (resume) command and results in the same interruption as that described in the second embodiment, the same operation is performed again after the interruption. When the block is erased, the same replaced redundant block can be seen again.

  FIG. 14 is a flowchart showing the operation of this embodiment from when a return (resume) command is received to when the process returns to the “automatic redundant block replacement routine”.

  First, when a return command is received, it is determined whether both the first and second flag information are written (step S51). Here, when it is determined that both the first and second flag information are written, a replacement prohibition bit of the volatile memory indicating that the redundant block of the address stored in the first register is prohibition of replacement. Is written (step S52).

  Thereafter, when returning to the “automatic redundant block replacement routine”, the replacement operation can be resumed from the redundant block of the address stored in the second register 420, that is, the redundant cell to be replaced at the time of command input. . In this case, the replacement enable bit and replacement prohibition bit of the redundant block at the address stored in the second register 420 are both erased (steps S44 and S45), so the replacement routine for the unused redundant block is immediately resumed. it can.

  In the case where the determination (verification) that the replacement prohibition bit has been written in the nonvolatile memory of the redundant block that has already been replaced and that has failed has already been made, according to this embodiment, the suspend and Resume can be executed. That is, when a resume command is received, the replacement operation can be resumed from the redundant cell that was to be replaced when the suspend command was input. Even if the resume command is not input, since the volatile memory is returned to the state at the start of the “automatic redundant block replacement routine”, the “automatic redundant block replacement routine” can be restarted from the beginning.

  As described above, in the above-described embodiments of the present invention, the example of the redundant block that repairs the defect in units of blocks has been described, but the redundant bit line that repairs the defect in units of bit lines and the defect in units of word line are repaired. All of the above embodiments can be applied to redundant word lines to be operated, and further to operations in units of memory cells.

  Therefore, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. 1 is a diagram showing a bit configuration of a nonvolatile memory (fuse ROM) corresponding to each redundant block in the nonvolatile semiconductor memory device according to the first embodiment of the invention. 1 is a diagram showing a bit configuration of a nonvolatile memory (fuse ROM) corresponding to all redundant blocks in the nonvolatile semiconductor memory device according to the first embodiment of the invention. 3 is a flowchart showing an erase operation in the nonvolatile semiconductor memory device according to the first embodiment of the present invention. 6 is a flowchart showing the operation of an automatic redundant block replacement routine in the erase operation of the first embodiment. The figure which shows the waveform of the mask signal in the automatic redundant block replacement routine of 1st Embodiment. 9 is another flowchart showing the operation of the automatic redundant block replacement routine in the erase operation of the first embodiment. The block diagram which shows the structure of the non-volatile semiconductor memory device which concerns on the 2nd Embodiment of this invention. 9 is a flowchart showing the operation of an automatic redundant block replacement routine in the erase operation of the second embodiment. The flowchart which shows operation | movement when the interruption command is received in the automatic redundant block replacement routine of 2nd Embodiment. The block diagram which shows the structure of the non-volatile semiconductor memory device which concerns on the 3rd Embodiment of this invention. 10 is a flowchart showing the operation of an automatic redundant block replacement routine in the erase operation of the third embodiment. The flowchart which shows operation | movement when the interruption command is received in the automatic redundant block replacement routine of 3rd Embodiment. 10 is a flowchart showing an operation when a return (resume) command is accepted in the third embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Main body cell array, 2 ... Redundancy array, 3 ... Control circuit, 4 ... Write and erase circuit, 5 ... OR circuit, 6 ... AND circuit, 7 ... Decoder, 8 ... Timer, 9 ... Verify circuit, 11 ... Read control circuit , 11A ... block, 11B, 12B ... sense amplifier, 12A ... redundant block, 100 to 10n ... hit (HIT) signal generation circuit, 10 ... volatile memory (latch), 20 ... nonvolatile memory (fuse ROM), 30 ... Redundancy address comparison circuit, 60, 80, 90 ... AND circuit, 70 ... NAND circuit, 1000 ... non-volatile semiconductor memory device, 401 ... first flag storage unit, 402 ... second flag storage unit, 410 ... first Register, 420 ... second register.

Claims (5)

Searching for whether there is an unused redundant cell when the erasing operation is not completed even after a predetermined time has elapsed since the erasing operation on the memory cell started;
Determining whether the memory cell has already been replaced by a redundant cell when the unused redundant cell exists; and
When the memory cell has already been replaced with a redundant cell, replacement prohibition information indicating that the replaced redundant cell is prohibited to be replaced is written into a volatile memory corresponding to the replaced redundant cell, If the memory cell other than the memory cell is to be read, the replacement redundant cell is prohibited from being read; and
The replacement permission information indicating that the unused redundant cell is used for replacement in the volatile memory corresponding to the unused redundant cell, and that the memory cell is replaced with the unused redundant cell. Writing a replacement address that is an address of the memory cell, and in the meantime, when reading a memory cell other than the memory cell, prohibiting reading of the unused redundant cell; and
The replacement permission information and the replacement address are written in the nonvolatile memory corresponding to the unused redundant cell, and the erase operation is started again when it is determined that it has been correctly written. A defective cell automatic replacement method in a nonvolatile semiconductor memory device. Searching for whether there is an unused redundant cell when the erasing operation is not completed even after a predetermined time has elapsed since the erasing operation on the memory cell started;
Determining whether the memory cell has already been replaced by a redundant cell when the unused redundant cell exists; and
Writing first flag information indicating that the replaced redundant cell is a defective cell when the memory cell has already been replaced by a redundant cell;
Storing the first address, which is the address of the replaced redundant cell, in a first register when the memory cell has already been replaced by a redundant cell;
Determining whether or not the first flag information has been written when receiving an interrupt processing instruction;
When an instruction for interruption processing is received and it is determined that the first flag information is written, the first flag information is written in the volatile memory corresponding to the redundant cell of the first address, And a step of erasing replacement prohibition information indicating that replacement of a redundant cell at an address is prohibited. A method for automatically replacing defective cells in a nonvolatile semiconductor memory device. Searching for whether there is an unused redundant cell when the erasing operation is not completed even after a predetermined time has elapsed since the erasing operation on the memory cell started;
Determining whether the memory cell has already been replaced by a redundant cell when the unused redundant cell exists; and
Writing first flag information indicating that the replaced redundant cell is a defective cell when the memory cell has already been replaced by a redundant cell;
Storing the first address, which is the address of the replaced redundant cell, in a first register when the memory cell has already been replaced by a redundant cell;
When the memory cell has already been replaced with a redundant cell, replacement prohibition information indicating that the replaced redundant cell is prohibited to be replaced is written in a nonvolatile memory corresponding to the replaced redundant cell, and further Determining whether has been written correctly;
Writing second flag information indicating that the replacement prohibition information has been correctly written when it is determined that the replacement prohibition information has been correctly written;
Storing a second address, which is an address of an unused redundant cell that was intended to replace the memory cell, in a second register when receiving an interrupt processing instruction;
Determining whether or not the first flag information has been written after the step of storing the second address in a second register when receiving an interrupt processing instruction;
When an instruction for interruption processing is received and it is determined that the first flag information is written, the first flag information is written in the volatile memory corresponding to the redundant cell of the first address, And a step of erasing replacement prohibition information indicating that replacement of a redundant cell at an address is prohibited. A method for automatically replacing defective cells in a nonvolatile semiconductor memory device. Determining whether the second flag information has been written after the step of storing the second address in a second register when receiving an interrupt processing instruction;
When receiving an interrupt processing instruction, it is determined that the first flag information is written in the step of determining whether the first flag information is written, and the second flag information is written. When it is determined in the step of determining whether or not the second flag information has been written, the second flag information is written in the volatile memory corresponding to the redundant cell at the second address and the second flag information is written. 4. The method for automatically replacing defective cells in a nonvolatile semiconductor memory device according to claim 3, further comprising the step of erasing replacement prohibition information indicating that redundancy of an address redundant cell is prohibited. Determining whether the first flag information and the second flag information are both written when receiving a return processing instruction;
Volatility indicating that replacement of a redundant cell at the first address is prohibited when both the first flag information and the second flag information are written when receiving a return processing instruction 5. The method for automatically replacing defective cells in the nonvolatile semiconductor memory device according to claim 3, further comprising: writing memory replacement prohibition information.

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