JP2010033626A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for determining presence of a laser attack with high accuracy in an internal power supply circuit. <P>SOLUTION: A semiconductor device includes a nonvolatile memory, and the nonvolatile memory includes the internal power supply circuit. The internal power supply circuit includes a voltage generating circuit and a voltage-dividing circuit (100) which divides the output voltage. Further, the internal power supply circuit includes a first comparator (105) that compares an output voltage from a first tap of the voltage-dividing circuit with a reference voltage, a second comparator (104) which compares an output voltage from a second tap of the voltage-dividing circuit with the reference voltage, and a determination circuit (106) for determining presence of a laser attack based on the output of the second comparator. The determination circuit determines timing for starting determination of presence of the laser attack based on a voltage detection signal, thereby determining presence of the laser attack with high accuracy. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique for improving the security level of a semiconductor device and further to a laser attack of a nonvolatile memory included in the semiconductor device.

  Patent Document 1 discloses a method for protecting confidential data from unauthorized access such as optical flash, that is, a voltage drop sensor is arranged in a plurality of glue logic circuits on a smart card chip, and even one of them detects a voltage drop. Then, a technique for setting an error state is described (see FIGS. 1 and 2).

  In Patent Document 2, a voltage obtained by dividing the voltage boosted by the charge pump circuit 1 and the reference voltage Vref are compared by a comparator 13, and as a result, if a voltage necessary for writing or erasing is not obtained, A technique for prohibiting the operation of the CPU 4 is described. In this case, the timing for issuing the prohibit signal for prohibiting the operation is the timing at which the voltage Vpp should be fully boosted to a desired voltage (for example, 20 V) (see FIGS. 1 and 2). The present invention can also be applied to a case where the IC card is illegally used and is crafted so as to prohibit the supply of a voltage necessary for writing or erasing to the semiconductor memory device (paragraph 0043).

JP 2003-233790 A JP 2000-20411 A

  Attacks that induce malfunctions and extract security information in a memory containing security information have been actively performed. As a recent trend, an attack using a laser beam (referred to as “laser attack”) and causing a malfunction of a part of a circuit has been taken up.

  It is known that when a semiconductor device is irradiated with laser light, a leakage current is generated between the diffusion layer and the substrate. For example, as shown in FIG. 16, when laser light is irradiated to an inverter in which a p-channel MOS transistor (P-MOS) and an n-channel MOS transistor (N-MOS) are connected in series, P A leak current flows between the well (pwell) and the N well (nwell) adjacent thereto. Since the inverter is formed everywhere in the semiconductor device, the generation of leakage current between the P well and the N well causes a large current change in the entire chip. This causes the level fluctuation of the negative voltage VPP. Note that level fluctuations due to laser attack can occur not only with negative voltages but also with positive voltages. As a result of the voltage level fluctuations occurring in this way, it has been confirmed by the present inventor that a malfunction occurs when data is read from the memory immediately after that.

  In order to accurately determine the presence or absence of a laser attack, it is necessary to distinguish between a potential fluctuation caused by a normal leak current and an abnormal potential fluctuation caused by a laser attack. Also, it is difficult to accurately determine the presence or absence of a laser attack in a state where the power supply voltage is unstable, such as immediately after the power is turned on.

  An object of the present invention is to provide a technique for accurately determining the presence or absence of a laser attack in an internal power supply circuit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A representative one of the inventions disclosed in the present application will be briefly described as follows.

  That is, the semiconductor device includes a nonvolatile memory, and the nonvolatile memory includes an internal power supply circuit. The internal power supply circuit includes a voltage generating circuit, a voltage dividing circuit that divides the output voltage of the voltage generating circuit, a first comparator that compares an output voltage from a first tap in the voltage dividing circuit with a reference voltage, A second comparator that compares the output voltage from the second tap with the reference voltage, and a determination circuit that can determine the presence or absence of a laser attack based on the output signal of the second comparator. The determination circuit determines a determination start timing for the presence / absence of the laser attack based on the voltage detection signal. This eliminates the determination in a state where the power supply voltage is unstable, and achieves an improvement in the accuracy of the presence or absence of a laser attack.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to provide a technique for accurately determining the presence or absence of a laser attack in the internal power supply circuit.

1. Representative Embodiment First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor device (500) according to a representative embodiment of the present invention includes a nonvolatile memory (503). The nonvolatile memory includes an internal power supply circuit (701) that can generate a voltage supplied to the internal circuit of the nonvolatile memory. The internal power supply circuit includes a voltage generation circuit (107, 207) capable of controlling the output voltage level based on the transmitted voltage detection signal, and a plurality of resistors connected in series to form a plurality of taps. A voltage dividing circuit (100, 200) capable of dividing an output voltage of the voltage generating circuit and outputting the divided voltage from the plurality of taps. The internal power supply circuit includes a first comparator (105, 205) that forms the voltage detection signal by comparing an output voltage from the first tap in the voltage dividing circuit with a reference voltage, and the first comparator. It includes a second comparator (104, 204) that compares the output voltage from the second tap located closer to the output side of the voltage generating circuit than the tap and the reference voltage. Further, the internal power supply circuit includes a determination circuit (106, 206) capable of determining the presence or absence of a laser attack based on the output signal of the second comparator. The determination circuit determines a determination start timing for the presence / absence of the laser attack based on the voltage detection signal.

  According to the above configuration, when the output voltage of the tap in the voltage dividing circuit exceeds the reference voltage, the comparison result (C) in the first comparator is inverted, thereby starting the determination operation in the determination circuit. Since the determination timing of the presence / absence of laser attack can be determined in this way, the determination operation in the determination circuit can be started after the positive voltage level is stabilized, thereby determining the accuracy of determination of the presence / absence of laser attack. Can be improved.

  The voltage generation circuit includes charge pumps (107, 207).

  [2] In the above [1], the determination circuit fetches a mask signal and determines whether or not a laser attack is present during the period when the mask signal is asserted regardless of the voltage detection signal from the first comparator. It can be configured not to.

  [3] In the above [2], a sequencer (601) for asserting the mask signal during an erase operation period or a write operation period of the nonvolatile memory can be provided. Thereby, it is possible to prevent an erroneous determination in the determination circuit during the erase operation period or the write operation period of the nonvolatile memory.

  [4] In addition, the internal power supply circuit has a voltage generation circuit (207) capable of controlling the output voltage level based on the transmitted voltage detection signal and a plurality of resistors connected in series to form a tap, In addition to the voltage dividing circuit (200) capable of dividing the output voltage of the voltage generating circuit and outputting it from the tap, the following circuit can be provided. A comparator (205) that forms the voltage detection signal by comparing an output voltage from the tap in the voltage dividing circuit with a reference voltage, and an output from the tap in the voltage dividing circuit using the voltage detection signal as a trigger. A timer (301) that measures a period when the voltage is less than the reference voltage and a determination circuit (206) that can determine the presence or absence of a laser attack based on the measurement result of the timer are provided. The determination circuit determines a determination start timing for the presence / absence of the laser attack based on the voltage detection signal.

  [5] In the above [4], the determination circuit takes in the mask signal and does not determine whether or not there is a laser attack regardless of the voltage detection signal from the comparator during the period when the mask signal is asserted. Can be configured.

  [6] In the above [5], a sequencer (601) for asserting the mask signal during an erase operation period or a write operation period of the nonvolatile memory can be provided.

  [7] Further, in the internal power supply circuit, a voltage generation circuit (107) capable of controlling an output voltage level based on a transmitted voltage detection signal and a plurality of transistors separated from each other by a separation region are connected in series. Thus, a plurality of taps are formed, and the following circuit can be provided separately from the voltage dividing circuit (100) capable of dividing the output voltage of the voltage generating circuit and outputting the divided voltage. That is, the first comparator (105) that forms the voltage detection signal by comparing the output voltage from the first tap in the voltage dividing circuit with the reference voltage, and the output of the voltage generation circuit than the first tap. A second comparator (104) for comparing an output voltage from a second tap located near the side and the reference voltage, and a determination circuit capable of determining the presence or absence of a laser attack based on the output signal of the second comparator (106). The determination circuit determines a determination start timing for the presence / absence of the laser attack based on the voltage detection signal.

  [8] In the above [7], the determination circuit fetches a mask signal and determines whether or not a laser attack is present during the period when the mask signal is asserted regardless of the voltage detection signal from the first comparator. It can be configured not to.

  [9] In the above [8], a sequencer (601) for asserting the mask signal during an erase operation period or a write operation period of the nonvolatile memory can be provided.

  [10] In the above [7], the voltage generated by the voltage generation circuit is supplied to the isolation region.

2. Next, the embodiment will be described in more detail.

  FIG. 5 shows a microcomputer as an example of a semiconductor device according to the present invention. The microcomputer 500 shown in FIG. 5 is not particularly limited, but is mounted on an IC card or the like, and is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. The microcomputer 500 shown in FIG. 5 is not particularly limited, but includes a random access memory (RAM) 501, a read only memory (ROM) 502, an electrically erasable and programmable read only memory (EEP) 503, CPU (central processing unit) 504. The CPU 504 performs arithmetic processing according to a predetermined program. The nonvolatile memory 503 stores programs executed by the CPU 504 and various data. The ROM 502 stores a program that is executed by the CPU 504. The RAM 501 is used as a work area when arithmetic processing is performed by the CPU 504. The RAM 501, ROM 502, nonvolatile memory 503, and CPU 504 are coupled to each other via an address bus A-BUS and a data bus D-BUS so that signals can be exchanged. A RAM control signal for controlling the operation of the RAM 501 is supplied from the CPU 504 to the RAM 501, a ROM control signal for controlling the operation of the ROM 502 is supplied from the CPU 504 to the ROM 502, and the nonvolatile memory 503 is supplied from the CPU 504. In contrast, an EEP control signal for controlling the operation of the nonvolatile memory 503 is supplied. Further, an error signal ERR is supplied from the nonvolatile memory 503 to the CPU 504. The error signal ERR is asserted to a high level when a laser attack is performed on the nonvolatile memory 503 and detected in the nonvolatile memory 503. When the error signal ERR is asserted to a high level, the CPU 504 transitions to a state in which no command is accepted for security protection. This state is restored by a system power-on reset.

  FIG. 6 shows a configuration example of the nonvolatile memory 503.

  As shown in FIG. 6, the nonvolatile memory 503 includes a sequencer 601, an internal power supply circuit 602, a memory cell array 603, a row system circuit 604, a column system circuit 605, and an interface logic 606 with the CPU. The memory cell array 603 includes a plurality of nonvolatile memory cells arranged in an array. Although not particularly limited, the nonvolatile memory cell is an “insulating film charge trapping nonvolatile memory cell” that accumulates charges in the insulating film. A row address is decoded by the row circuit 604. According to the decoding result of the row address, a word line is selected in the memory cell array 603. The column address is decoded by the column circuit. The column line address is selected according to the decoding result. The internal power supply circuit 602 generates various voltages used in the internal circuit of the nonvolatile memory 503. The voltage generated by the internal power supply circuit 602 is supplied to the memory cell array 603, the row circuit 604, and the column circuit 605. The sequencer 601 sequentially controls write (write), erase (erase), and read (read) operations in the nonvolatile memory 503.

  FIG. 7 shows a configuration example of the internal power supply circuit 602.

  Although not particularly limited, the internal power supply circuit 602 includes a positive voltage generation circuit 701, a positive voltage generation circuit 702, a positive voltage generation circuit 703, and a negative voltage generation circuit 704, as shown in FIG. The positive voltage generation circuit 701 generates a positive voltage VDD3X when a control signal and a reference voltage are input. The positive voltage generation circuit 702 generates a positive voltage VEE by receiving a control signal and a reference voltage. The positive voltage generation circuit 703 generates a positive voltage VD45 when a control signal and a reference voltage are input. The negative voltage generation circuit 704 generates a predetermined negative voltage VPP when a control signal or a reference voltage is input. The levels of the various voltages VDD3X, VEE, VD45, and VPP are controlled as shown in FIG. 8, for example, in each of the read, erase, and write operations. That is, in the read operation, VPP = -2V, VDD3X = 4V, VEE = VDD, VD45 = VDD, and in the erase operation, VPP = -4V, VDD3X = VDD, VEE = 6V, VD45 = VDD, and the write operation. VPP = −6V, VDD3X = VDD, VEE = 6V, and VD45 = 4.5V. Although the positive voltage generation circuits 701 to 703 have different output voltage levels, basically the same configuration can be applied. Therefore, the positive voltage generation circuit 701 and the negative voltage generation circuit 704 will be described in detail, and detailed description of the positive voltage generation circuits 702 and 703 will be omitted.

  FIG. 1 shows a configuration example of the positive voltage generation circuit 701.

  The positive voltage generation circuit 701 includes a voltage dividing circuit 100, comparators 104 and 105, a determination circuit 106, and a charge pump 107. The voltage dividing circuit 100 includes a plurality of resistors 101, 102, and 103 connected in series. A series connection location of the resistors 101 and 102 is a tap 108, and a series connection location of the resistors 102 and 103 is a tap 109.

  The charge pump 107 generates a positive voltage VDD3X by a switching operation. The positive voltage VDD3X is supplied to one end of the voltage dividing circuit 100. The other end of the voltage dividing circuit 100 is set to the ground (GND) level. Thereby, a divided voltage output corresponding to the resistance ratio is obtained from the taps 108 and 109. Tap 108 of voltage divider circuit 100 is coupled to the inverting input terminal (−) of comparator 104, and tap 109 of voltage divider circuit 100 is coupled to the inverting input terminal (−) of comparator 105. A predetermined reference voltage VREF1 is supplied to the non-inverting input terminal (+) of the comparators 104 and 105. The comparator 105 compares the output voltage of the tap 109 of the voltage dividing circuit 100 with the reference voltage VREF1. This comparison result (C) is transmitted to the charge pump 107 and the determination circuit 106 in the subsequent stage. The comparator 104 compares the output voltage of the tap 108 of the voltage dividing circuit 100 with the reference voltage VREF1. The comparison result (D) is transmitted to the determination circuit 106 at the subsequent stage. In the charge pump 107, the positive voltage VDD3X is stabilized by controlling the speed of the switching operation according to the comparison result (C) in the comparator 105. The determination circuit 106 determines the presence / absence of a laser attack based on the comparison result (D) in the comparator 104. The determination circuit 106 determines the determination start timing for the presence or absence of the laser attack based on the comparison result (C) in the comparator 105. Further, the determination circuit 106 takes in the mask signal MASK and does not determine whether or not there is a laser attack during the period when the mask signal MASK is asserted. The mask signal MASK is asserted by the sequencer 601 during the erase operation period or write operation period of the nonvolatile memory 503.

  FIG. 10 shows the operation timing of the main part in the positive voltage generation circuit 701.

  A power supply voltage VCC is supplied from the outside of the microcomputer 500, and positive voltages VDD and VDD3X are formed in the internal power supply circuit 602. Although not particularly limited, when the power supply voltage VCC is 5V or 3V, the positive voltage VDD is 1.5V and the positive voltage VDD3X is 4V. The switching operation of the charge pump 107 is started by supplying the power supply voltage VCC. Immediately after the start of the switching operation of the charge pump 107, since the output voltage of the tap 109 in the voltage dividing circuit 100 is lower than the reference voltage VREF1, the comparison result (C) in the comparator 105 is set to the low level. Thereby, the switching operation speed of the charge pump 107 is increased, and the level of the positive voltage VDD3X is increased. As the level of the positive voltage VDD3X increases, the output voltage level of the tap 109 in the voltage dividing circuit 100 also increases. When the output voltage of the tap 109 in the voltage dividing circuit 100 exceeds the reference voltage VREF1, the comparison result (C) in the comparator 105 is inverted from the previous low level to the high level. Thereby, the determination operation in the determination circuit 106 is started. The positive voltage VDD3X is stabilized at 4V by feedback control based on the comparison result (C) in the comparator 105. Although the level fluctuation (ripple) of the positive voltage VDD3X may occur due to load fluctuation or the like, if the level fluctuation is within an allowable range, the determination result (D) in the comparator 104 is maintained at a high level. However, when the level of the positive voltage VDD3X is greatly reduced due to the laser attack, the determination result (D) in the comparator 104 is changed from the previous high level to the low level, so that the positive voltage VDD3X level is positive. A level drop of the voltage VDD3X is detected. When the decrease in level of the positive voltage VDD3X is detected, the determination circuit 106 asserts the error signal ERR to a high level.

  FIG. 2 shows a configuration example of the negative voltage generation circuit 704.

  The negative voltage generation circuit 704 includes a voltage dividing circuit 200, comparators 204 and 205, a determination circuit 206, and a charge pump 207. The voltage dividing circuit 200 includes a plurality of resistors 201, 202, and 203 connected in series. A series connection location of the resistors 201 and 202 is a tap 208, and a series connection location of the resistors 202 and 203 is a tap 209.

  The charge pump 207 generates a negative voltage VPP by a switching operation. This negative voltage VPP is supplied to one end of the voltage dividing circuit 200. A positive voltage VDD is supplied to the other end of the voltage dividing circuit 200. As a result, a divided voltage output corresponding to the resistance ratio is obtained from the taps 208 and 209. Tap 208 of voltage divider circuit 200 is coupled to a non-inverting input terminal (+) of comparator 204, and tap 209 of voltage divider circuit 200 is coupled to a non-inverting input terminal (+) of comparator 205. A predetermined reference voltage VREF2 is supplied to the inverting input terminals (−) of the comparators 204 and 205. The comparator 205 compares the output voltage of the tap 209 of the voltage dividing circuit 200 with the reference voltage VREF2. This comparison result (C) is transmitted to the charge pump 207 and the determination circuit 206 in the subsequent stage. The comparator 204 compares the output voltage of the tap 208 of the voltage dividing circuit 200 with the reference voltage VREF2. The comparison result (D) is transmitted to the determination circuit 206 at the subsequent stage. In the charge pump 207, the positive voltage VDD3X is stabilized by controlling the speed of the switching operation according to the comparison result (C) in the comparator 205. The determination circuit 206 determines the presence or absence of a laser attack based on the comparison result (D) in the comparator 204. The determination circuit 206 determines the determination start timing for the presence or absence of the laser attack based on the comparison result (C) in the comparator 205. Further, the determination circuit 206 takes in the mask signal MASK and does not determine whether or not there is a laser attack during the period when the mask signal MASK is asserted.

  FIG. 11 shows the operation timing of the main part in the negative voltage generation circuit 704.

  By supplying the power supply voltage VCC from the outside of the microcomputer 500, the negative voltage generation circuit 704 forms the negative voltage VPP. Although not particularly limited, the negative voltage VPP is set to -2V. The switching operation of the charge pump 207 is started by supplying the power supply voltage VCC. Immediately after the start of the switching operation of the charge pump 207, since the output voltage of the tap 209 in the voltage dividing circuit 200 is higher than the reference voltage VREF2, the comparison result (C) in the comparator 205 is set to the low level. Thereby, the switching operation speed of the charge pump 207 is increased, and the level of the negative voltage VPP is lowered. As the level of the negative voltage VPP decreases, the output voltage level of the tap 209 in the voltage dividing circuit 200 also decreases. When the output voltage of the tap 209 in the voltage dividing circuit 200 falls below the reference voltage VREF2, the comparison result (C) in the comparator 205 is inverted from the previous low level to the high level. Thereby, the determination operation in the determination circuit 206 is started. The negative voltage VPP is stabilized at −2 V by feedback control based on the comparison result (C) in the comparator 205. Although the level variation (ripple) of the negative voltage VPP may occur due to load variation or the like, if the level variation is within an allowable range, the determination result (D) in the comparator 204 is maintained at a high level. However, when the level of the negative voltage VPP is significantly increased due to the laser attack, the determination result (D) in the comparator 204 is changed from the previous high level to the low level. An increase in the level of voltage VPP is detected. When the increase in level of the negative voltage VPP is detected, the determination circuit 206 asserts the error signal ERR to a high level.

  FIG. 15 shows an operation example of the CPU 504.

  When the error signal ERR is asserted to a high level by the positive voltage generation circuit 701 or the negative voltage generation circuit 704 in the normal operation state of the CPU 504 (1502), the CPU 504 Immediately, the operation of each internal module is stopped or initialized (1503), and a transition is made to a state in which no external input is accepted (1504). This state is maintained until the power is shut off, and the normal state is restored by performing a power-on reset process.

  FIG. 12 shows operation timing related to mask processing in the determination circuit 206.

  During a period in which the mask signal MASK is asserted to a high level by the sequencer 601, the presence / absence of a laser attack is not determined regardless of the comparison result (C) in the comparator 205. During the erase operation period and write operation period for the memory cell array 603, the sequencer 601 asserts the mask signal MASK to a high level. In the erase operation period and write operation period for the memory cell array 603, for example, as shown in FIG. 12, the level of the negative voltage VPP varies greatly in the range of 0V to −6V, and this variation is caused by the laser attack. There is a risk of erroneous determination. Therefore, during the erase operation period and write operation period for the memory cell array 603, the sequencer 601 asserts the mask signal MASK to a high level so that the presence / absence of laser attack is not determined. Determination of the presence or absence of a laser attack is resumed after the mask signal MASK is negated by the sequencer 601.

  The mask processing in the determination circuit 106 in the positive voltage generation circuit 701 is also performed in the same manner as the mask processing in the determination circuit 206 in the negative voltage generation circuit 704, thereby eliminating erroneous determination in the determination circuit 106. Can do.

  According to the above example, the following effects can be obtained.

  (1) According to the configuration shown in FIG. 1, immediately after the start of the switching operation of the charge pump 107, the output voltage of the tap 109 in the voltage dividing circuit 100 is lower than the reference voltage VREF1, so the comparison result in the comparator 105 (C) is at a low level. Thereby, the switching operation speed of the charge pump 107 is increased, and the level of the positive voltage VDD3X is increased. As the level of the positive voltage VDD3X increases, the output voltage level of the tap 109 in the voltage dividing circuit 100 also increases. When the output voltage of the tap 109 in the voltage dividing circuit 100 exceeds the reference voltage VREF1, the comparison result (C) in the comparator 105 is inverted from the previous low level to the high level. Thereby, the determination operation in the determination circuit 106 is started. Further, according to the configuration shown in FIG. 2, when the output voltage of the tap 209 in the voltage dividing circuit 200 is lower than the reference voltage VREF2, the comparison result (C) in the comparator 205 is changed from the previous low level to the high level. Inverted. Thereby, the determination operation in the determination circuit 206 is started. As described above, the determination operation of the determination circuits 106 and 206 is started after the levels of the positive voltage VDD3X and the negative voltage VPP are stabilized, so that the determination accuracy of the presence or absence of the laser attack can be improved. .

  (2) During the erase operation period and write operation period to the memory cell array 603, the mask signal MASK is asserted to a high level by the sequencer 601 so that the presence / absence of the laser attack is not determined. An erroneous determination in the circuit 206 can be eliminated. Further, the mask process in the determination circuit 106 in the positive voltage generation circuit 701 is also performed in the same manner as the mask process in the determination circuit 206 in the negative voltage generation circuit 704, thereby eliminating erroneous determination in the determination circuit 106. Can do. Thereby, the determination accuracy of the presence or absence of laser attack can be further increased.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, the negative voltage generation circuit 704 can be provided with a timer 301 in place of the comparator 204 (see FIG. 2), as shown in FIG. The timer 301 measures a period during which the output voltage from the tap 209 in the voltage dividing circuit 200 is less than the reference voltage VREF2, using the comparison result (C) in the comparator 205 as a trigger. The measurement result of the timer 301 is transmitted to the determination circuit 301 at the subsequent stage. The determination circuit 206 determines the presence / absence of a laser attack based on the measurement result of the timer 301. FIG. 13 shows the operation timing in this case. When the low level period (see 131) of the comparison result (C) in the comparator 205 is measured by the timer 301 and the low level period exceeds a predetermined time, the determination circuit 206 determines that a laser attack has occurred. The error signal ERR is asserted to a high level. 3 shows the configuration of the negative voltage generation circuit 704. In the positive voltage generation circuit 701, a timer is provided in place of the comparator 104 (see FIG. 1) to determine the presence or absence of a laser attack. Can do.

  In the above example, the voltage dividing circuits 100 and 200 are configured by connecting a plurality of resistors in series. For example, as shown in FIG. 4, the voltage dividing circuit 100 includes n-channel MOS transistors 401, 402, A configuration in which 403 and 404 are connected in series can be applied. FIG. 9 shows the layout of the n-channel MOS transistors 401 to 404 constituting the voltage dividing circuit 100 in FIG.

  As shown in FIG. 4, the n-channel MOS transistors 401 to 404 are separated from each other by an n-channel isolation region (Niso). A positive voltage VDD3X is supplied to the isolation region (Niso). The n-channel MOS transistor 404 is biased by the reference voltage VREF. According to such a configuration, when the level of the positive voltage VDD3X supplied to the isolation region (Niso) is lowered by the laser attack, coupling noise is generated and is superimposed on the well potential (Vpwell). Thus, the output voltage (tap voltage) of the dividing circuit 100 is further reduced. That is, as shown in FIG. 14, the output voltage C0 of the dividing circuit 100 is obtained by superimposing the coupling noise component on the voltage division (DC level) by the resistance ratio of the n-channel MOS transistors 401, 402, 403, and 404. As a result, the voltage fluctuation caused by the laser attack is detected with higher sensitivity than when the voltage dividing circuits 100 and 200 are configured by a plurality of resistors (FIGS. 1, 2, and 3). can do.

  Further, in the above example, the logic of the mask signal MASK is controlled by the sequencer 601, but separately, the logic of the mask signal MASK may be controlled by the CPU 504. In this case, an OR logic between the mask signal MASK from the sequencer 601 and the mask signal MASK from the CPU 504 may be obtained and supplied to the determination circuits 106 and 206. When the determination result by the determination circuits 106 and 206 becomes unnecessary depending on the use environment of the microcomputer 500, the determination function in the determination circuits 106 and 206 can be stopped by the mask signal MASK from the CPU 504.

  In the above description, the case where the invention made mainly by the present inventor is applied to a microcomputer which is a field of use as the background has been described. However, the present invention is not limited to this and is applied to various semiconductor devices. be able to.

1 is a circuit diagram of a configuration example of a positive voltage generating circuit in a nonvolatile memory included in a microcomputer as an example of a semiconductor device according to the present invention. FIG. 3 is a circuit diagram illustrating a configuration example of a negative voltage generation circuit in a nonvolatile memory included in the microcomputer. FIG. 6 is a circuit diagram illustrating another configuration example of the negative voltage generation circuit. FIG. 6 is a circuit diagram illustrating another configuration example of the positive voltage generation circuit. It is a block diagram of an example of the overall configuration of the microcomputer. It is a block diagram of a configuration example of a nonvolatile memory included in the microcomputer. It is a block diagram of a configuration example of an internal power supply circuit in the nonvolatile memory. It is explanatory drawing of the various voltages generated with the said internal power supply circuit. FIG. 5 is a layout explanatory diagram of a main part in the voltage dividing circuit shown in FIG. 4. FIG. 2 is an operation timing chart of the positive voltage generation circuit shown in FIG. 1. FIG. 3 is an operation timing chart of the negative voltage generation circuit shown in FIG. 2. FIG. 3 is an operation timing chart regarding mask processing in a determination circuit included in the negative voltage generation circuit shown in FIG. 2. FIG. 4 is an operation timing chart of the negative voltage generation circuit shown in FIG. 3. FIG. 5 is an operation explanatory diagram of the positive voltage generation circuit shown in FIG. 4. It is a flowchart which shows operation | movement of CPU in the said microcomputer. It is explanatory drawing of the negative voltage VPP level fall by a laser attack.

Explanation of symbols

100, 200 Voltage divider circuit 101-103, 201-203 Resistor 104, 204 Comparator 105, 205 Comparator 106, 206 Judgment circuit 107, 207 Charge pump 500 Microcomputer 501 RAM
502 ROM
503 Non-volatile memory 504 CPU
601 Sequencer 602 Internal power supply circuit 603 Memory cell array 604 Row system circuit 605 Column system circuit 606 Interface logic with CPU 701, 702, 703 Positive voltage generation circuit 704 Negative voltage generation circuit

Claims (10)

A semiconductor device including a nonvolatile memory,
The nonvolatile memory includes an internal power supply circuit capable of generating a voltage supplied to the internal circuit of the nonvolatile memory,
The internal power supply circuit includes a voltage generation circuit capable of controlling an output voltage level based on a transmitted voltage detection signal;
A plurality of taps are formed by connecting a plurality of resistors in series, and a voltage dividing circuit capable of dividing the output voltage of the voltage generation circuit and outputting from the plurality of taps;
A first comparator that forms the voltage detection signal by comparing an output voltage from the first tap in the voltage dividing circuit with a reference voltage;
A second comparator that compares the output voltage from the second tap located closer to the output side of the voltage generation circuit than the first tap with the reference voltage;
A determination circuit capable of determining the presence or absence of a laser attack based on the output signal of the second comparator,
The semiconductor device according to claim 1, wherein the determination circuit determines a determination start timing for the presence or absence of the laser attack based on the voltage detection signal.   The semiconductor device according to claim 1, wherein the determination circuit takes in a mask signal and does not determine the presence or absence of a laser attack regardless of the voltage detection signal from the first comparator during a period in which the mask signal is asserted.   3. The semiconductor device according to claim 2, further comprising a sequencer that asserts the mask signal during an erase operation period or a write operation period of the nonvolatile memory. A semiconductor device including a nonvolatile memory,
The nonvolatile memory includes an internal power supply circuit capable of generating a voltage supplied to the internal circuit of the nonvolatile memory,
The internal power supply circuit includes a voltage generation circuit capable of controlling an output voltage level based on a transmitted voltage detection signal;
A tap is formed by connecting a plurality of resistors in series, and a voltage dividing circuit capable of dividing the output voltage of the voltage generating circuit and outputting from the tap,
A comparator that forms the voltage detection signal by comparing the output voltage from the tap in the voltage dividing circuit with a reference voltage;
Using the voltage detection signal as a trigger, a timer that measures a period during which the output voltage from the tap in the voltage dividing circuit is less than the reference voltage,
A determination circuit capable of determining the presence or absence of a laser attack based on the measurement result of the timer, and
The semiconductor device according to claim 1, wherein the determination circuit determines a determination start timing for the presence or absence of the laser attack based on the voltage detection signal.   5. The semiconductor device according to claim 4, wherein the determination circuit takes in a mask signal and does not determine the presence or absence of a laser attack regardless of a voltage detection signal from the comparator during a period in which the mask signal is asserted.   6. The semiconductor device according to claim 5, further comprising a sequencer that asserts the mask signal during an erase operation period or a write operation period of the nonvolatile memory. A semiconductor device including a nonvolatile memory,
The nonvolatile memory includes an internal power supply circuit capable of generating a voltage supplied to the internal circuit of the nonvolatile memory,
The internal power supply circuit includes a voltage generation circuit capable of controlling an output voltage level based on a transmitted voltage detection signal;
A plurality of taps are formed by serially connecting a plurality of transistors separated from each other by a separation region, and a voltage dividing circuit capable of dividing the output voltage of the voltage generation circuit and outputting from the plurality of taps;
A first comparator that forms the voltage detection signal by comparing an output voltage from the first tap in the voltage dividing circuit with a reference voltage;
A second comparator that compares the output voltage from the second tap located closer to the output side of the voltage generation circuit than the first tap with the reference voltage;
A determination circuit capable of determining the presence or absence of a laser attack based on the output signal of the second comparator,
The semiconductor device according to claim 1, wherein the determination circuit determines a determination start timing for the presence or absence of the laser attack based on the voltage detection signal.   8. The semiconductor device according to claim 7, wherein the determination circuit takes in a mask signal and does not determine whether or not a laser attack is present during a period in which the mask signal is asserted, regardless of a voltage detection signal from the first comparator.   9. The semiconductor device according to claim 8, further comprising a sequencer that asserts the mask signal during an erase operation period or a write operation period of the nonvolatile memory.   The semiconductor device according to claim 7, wherein a voltage generated by the voltage generation circuit is supplied to the isolation region.

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