JP2008250737A - Electromagnetic wave irradiation detecting circuit, semiconductor device and ic card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of achieving high security without deteriorating convenience. <P>SOLUTION: The electromagnetic wave irradiation detecting circuit is provided with two serial circuits SC1 and SC2 having an end to which a power-supply voltage V<SB>cc</SB>is applied and the other end to which a ground voltage is applied. The serial circuits are composed of resistors and flash memory transistors. A first target voltage V<SB>OUT1</SB>is input to an inversion input terminal 72im of a comparator 71, and a first target voltage V<SB>OUT2</SB>is input to an inversion input terminal 72ip, and a detection signal ERR is output based on magnitude relationship between them. A resistance value of the resistors R1 and R2 and a threshold voltage of the flash memory transistors 71a and 71b are adjusted under a prescribed condition so that a voltage level of the detection signal ERR in the state not irradiated with the electromagnetic wave and a voltage level of the detection signal ERR in the state irradiated with the electromagnetic wave are varied. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electromagnetic wave irradiation detection circuit that detects electromagnetic wave irradiation from the outside, a semiconductor device including the electromagnetic wave irradiation detection circuit, and an IC card.

  In recent years, there are increasing opportunities to use cash cards, credit cards, prepaid cards, etc. in everyday life. In contrast to these cards, magnetic cards were previously used to store information. However, from the viewpoint of handling personal information more carefully, in recent years, IC cards that have become easier to take security measures in place of magnetic cards. Has come to be used. The IC card normally uses a nonvolatile semiconductor memory device that retains memory even when the power is turned off to store information. As the nonvolatile semiconductor memory device, an EEPROM (Electronically Erasable and Programmable Read Only) is used. Memory) or an IC card using a flash memory has been conventionally provided.

  FIG. 8 is a block diagram showing a schematic configuration of a typical conventional IC card 90. The internal block of the IC card LSI includes an arithmetic and data storage unit 40, a non-contact interface 10, a contact interface 60, a power-on reset circuit 80, and an antenna 15.

  The non-contact interface 10 includes a rectifier circuit 11, a modulation circuit 12, a demodulation circuit 13, a clock separation circuit 14, a regulator 16, a regulator 17, and a protocol control circuit 18. The contact interface 60 includes a UART (Universal Asynchronous Receiver Transmitter) 61. The calculation and data storage unit 40 has almost the same configuration as that of a normal microcomputer, and includes a CPU 41, a ROM 42, a RAM 43, and a flash macro 20. The ROM 42 stores programs, and the RAM 43 is used as a working memory during calculation. The flash macro 20 is used for storing a program or holding data.

  The flash macro 20 includes an electromagnetic wave irradiation detection circuit 70 that detects electromagnetic wave irradiation from the outside. The configuration of the circuit 70 will be described later.

  The basic operation of the IC module built in the non-contact type IC card 90 having the above configuration will be described below with reference to FIG.

  First, a control signal for the non-contact IC card 90 is converted into an electromagnetic wave from an external reader / writer device (not shown). When the non-contact IC card receives the control signal converted into the electromagnetic wave, the antenna 15 embedded in the non-contact IC card 90 causes electromagnetic induction. A signal generated by the electromagnetic induction is converted into supply power, a clock signal, and a control signal for operating the calculation and data storage unit 40.

Further, the signal generated by the electromagnetic induction is converted to a positive voltage through a rectifier circuit 11, is further (generating V _PP) regulator 16, smoothing through a regulator 17 (generating the V _CC), operation And supplied to the data storage unit 40 as a power supply voltage. In addition, the power supply voltage ( _VCC and _VPP ) of a general IC module is 5V or 3V.

  The signal generated by the electromagnetic induction is converted into an internal clock by the clock separation circuit 14. The frequency of the internal clock is approximately 1 MHz to 15 MHz.

  Further, the signal generated by the electromagnetic induction is input to the protocol control circuit 18 through the demodulation circuit 13. The protocol control circuit 18 controls a communication protocol of a non-contact IC card (for example, Type A, Type B, Type C in the case of a proximity non-contact IC card) and transmits / receives data to / from the CPU 41. Based on the data, the CPU 41 controls the ROM 42, the RAM 43, and the flash macro 20 to perform processing such as computation. The result calculated by the CPU 41 is modulated by the modulation circuit 12 via the protocol control circuit 18, converted into an AC signal having a predetermined band, and then output as an electromagnetic wave from the antenna 15. The external reader / writer device receives this electromagnetic wave, converts it to a signal through a demodulation circuit in the reader / writer device, and completes the exchange of information with the IC card.

The power-on reset circuit 80 is a circuit that mainly outputs a reset signal in a non-contact operation. When the IC card 90 is close to the reader / writer device within a predetermined range, the voltage generated by electromagnetic induction of electromagnetic waves emitted from the reader / writer device increases. When the power supply voltage _VCC generated based on this voltage reaches a desired voltage (for example, 2.3 V), the reset state is released.

  On the other hand, the external reset signal RST is a reset signal during the contact operation. It is controlled by a contact type reader / writer device. When the voltage value falls below a predetermined level, the external reset signal RST is activated (low active).

  Note that the output signal of the power-on reset circuit 80 and the external reset signal RST (negative signal thereof) are both OR-connected by a reset signal generation circuit 9 that is internally configured with an OR circuit. The output signal of the reset signal generation circuit 9 is given to the arithmetic and data storage unit 40 as the reset signal RST1. The calculation and data storage unit 40 executes a reset process when a reset signal RST1 in an active state is given. The output signal ERR from the electromagnetic wave irradiation detection circuit 70 input to the reset signal generation circuit 9 will be described later.

  As described above, a non-volatile semiconductor memory device is mounted on a recent IC card, and various information is recorded in the memory device. Since such information includes personal information such as personal identification numbers and other information that is highly necessary to maintain confidentiality, the information in the IC card is externally used for unauthorized purposes such as falsification or leakage of such information. There is a need to take measures to prevent access to the storage device.

  As a conventional technique for preventing illegal analysis of circuit operation by irradiating an IC card with electromagnetic waves or the like and preventing leakage, falsification, and duplication of internal data, there is one disclosed in Patent Document 1 below. . A semiconductor device described in Patent Document 1 includes a detection circuit including a nonvolatile memory for detecting an electromagnetic wave irradiated to an integrated circuit formed on a semiconductor substrate (hereinafter referred to as an “electromagnetic wave irradiation detection circuit”). When the value read from the non-volatile memory does not match a predetermined value, the subsequent operation is stopped. Hereinafter, the basic operation of the electromagnetic wave irradiation detection circuit described in Patent Document 1 will be described with reference to the drawings. This electromagnetic wave irradiation detection circuit corresponds to the electromagnetic wave irradiation detection circuit 70 shown in FIG.

  FIG. 9 is a circuit block diagram showing a schematic configuration of a conventional electromagnetic wave irradiation detection circuit 70. The electromagnetic wave detection circuit 70 shown in FIG. 9 includes a resistor R1, a flash memory transistor 71, and a comparison circuit 74.

The resistor R1 and the flash memory transistor 71 are arranged in series to form a series circuit. More specifically, the power supply voltage _VCC is applied to one end of the resistor R1, the drain of the flash memory transistor 71 is connected to the other end of the resistor R1, and the source of the flash memory transistor 71 is grounded. The power supply voltage _VCC is also applied to the gate of the flash memory transistor 71.

The comparison circuit 74 includes a comparator 72 and a negation circuit 73. The comparator 72 includes an inverting input terminal 72im, a non-inverting input terminal 72ip, and an output terminal 72o. The inverting input terminal 72im predetermined reference voltage _{V REF} is input. Further, a voltage (hereinafter referred to as “target voltage”) _VOUT indicated by a connection node between the resistor R1 and the flash memory transistor 71 is applied to the non-inverting input terminal 72ip. Then, the non-inverting and the target voltage _{V OUT} applied to the input terminal 72Ip, compares the reference voltage _{V REF} that is input to the inverting input terminal 72Im, outputs the binary voltage signal based on the magnitude relationship from the output terminal 72o To do. Here, when V _OUT > V _REF, a high level voltage (eg, 3V) is output from the output terminal 72o, and conversely, when V _OUT <V _REF, a low level voltage (eg, ground voltage) is output from the output terminal 72o. Is output. The negative circuit 73 receives the voltage output from the output terminal 72o of the comparator 72, inverts the result of the input voltage level, and outputs the result as a detection signal ERR. That is, the electromagnetic wave irradiation detection circuit 70 outputs a low level voltage (for example, ground voltage) as the detection signal ERR when V _OUT > V _REF , and the high level voltage as the detection signal ERR when V _OUT <V _REF. (For example, 3V) is output.

A change in the target voltage _VOUT due to the electromagnetic wave irradiation to the electromagnetic wave irradiation detection circuit 70 having the configuration shown in FIG. 9 will be described below.

In describing the change in the target voltage _VOUT due to the irradiation of electromagnetic waves, first, the operation principle of the flash memory transistor will be described. FIG. 10 is a conceptual structural diagram of the flash memory transistor 71. As shown in FIG. 10, the flash memory transistor 71 includes electrodes (terminals) of a control gate 51, a floating gate 52, a source 53, and a drain 54.

  Since the threshold voltage of the flash memory transistor 71 changes depending on the amount of electrons in the floating gate 52, binary or multi-level information can be stored by defining a write state and an erase state based on the threshold voltage. It becomes possible. That is, a state where there is a large amount of charges (hereinafter referred to as electrons) accumulated in the floating gate 52 is a write state, and a state where no electrons are accumulated (or a state where there are few accumulated electrons) is an erased state. Thus, information is written by injection of electrons (hot electrons) into the floating gate 52, and conversely, information is erased by extracting the electrons accumulated in the floating gate 52. Become.

  For example, when information is written to the flash memory transistor 71, the control gate 51 has a high voltage (for example, 12V), the drain 54 has a high voltage (for example, 7V), and the source 53 has a low voltage (for example, 0V). Is applied by injecting hot electrons generated in the vicinity of the drain junction into the floating gate 52.

  On the other hand, when erasing information written in the flash memory transistor 71, the control gate 51 has a low voltage (for example, 0V), the drain 54 has a low voltage (for example, 0V), and the source 53 has a high voltage (for example, 0V). For example, 12V) is applied, a high electric field is generated between the floating gate 52 and the source 53, and electrons in the floating gate 52 are extracted to the source side using a tunnel phenomenon.

  When reading information from the flash memory transistor 71, a high voltage (eg, 5V) is applied to the control gate 51, a low voltage (eg, 1V) is applied to the drain 54, and a low voltage (eg, 0V) is applied to the source 53. The voltage is applied and the magnitude of the drain current flowing through the drain 54 is amplified by an internal sense amplifier, and data “1” and “0” are determined (in the case of binary data). When the voltage is applied, when electrons are accumulated in the floating gate 52 (information is written), the threshold voltage is high, so that the on-resistance of the flash memory transistor 71 is large, which causes the drain. The current becomes smaller. On the contrary, when no electrons are accumulated in the floating gate 52 or when the amount of accumulated electrons is small (information is erased), the threshold voltage is low, so that the on-resistance of the flash memory transistor 71 is small. The drain current increases. Accordingly, the storage state of the flash memory transistor 71 can be determined by detecting the magnitude of the drain current.

  A non-volatile semiconductor memory device (flash macro 20) provided in an IC card is a memory cell array configured by using the above-described flash memory transistor 71 as one memory cell and arranging a plurality of such memory cells in the row direction and the column direction. It is realized by. FIG. 11 is a schematic configuration diagram of a memory cell array configured by arranging the flash memory transistors 71 shown in FIG. 10 in a matrix.

  In FIG. 11, transistors having the same configuration as the flash memory transistor 71 described above are arranged in a matrix of m rows and n columns. The memory cell array 20a shown in FIG. 11 includes a plurality of word lines WL1, WL2,..., WLm extending in the row direction, a plurality of bit lines BL1, BL2,. Prepare. The control gates of the flash memory transistors in the same row are connected to the same word line, the drains of the flash memory transistors in the same column are connected to the same bit line, and the sources of all the transistors are a common source. Connected to line SL.

  For the flash memory having the memory cell array configured as described above, the voltage corresponding to the processing is applied via the word line, the bit line, and the source line connected to the memory cell to be written, erased, or read. By applying this, each process of writing, erasing, or reading information on the selected memory cell is executed.

A flash memory that stores information based on the above-described principle is configured to distinguish between a written state and an erased state based on the number of electrons accumulated in the floating gate 52. Since the structure is in an insulating state (floating state) with the conductive material, electrons once injected into the floating gate 52 remain stably in the floating gate 52 unless a new voltage is applied,
Further, unless a new voltage is applied, electrons are not injected into the floating gate 52 from an external conductive material, and thus information can be stably held.

  However, when an electromagnetic wave is irradiated from the outside to such a flash memory, the energy contained in the irradiated electromagnetic wave is given to the floating gate 52, so that the electrons accumulated in the floating gate 52 are in a high energy state. Thus, a situation of escape from the floating gate 52 may occur. When such a situation occurs, there is a concern that correctly written information is illegally erased, rewritten, or read.

  The electromagnetic wave irradiation detection circuit 70 shown in FIG. 9 detects a change in the threshold voltage by utilizing the change in the threshold voltage of the flash memory cell transistor when the electromagnetic wave is irradiated in order to deal with such a concern. By doing so, it is possible to detect the irradiation of electromagnetic waves.

In the circuit configuration shown in FIG. 9, the target voltage V _OUT is larger than the reference voltage V _REF (V _OUT >> under a state where no electromagnetic wave is irradiated (hereinafter referred to as “non-irradiation state”). It is assumed that the threshold voltage of the resistor R1 and the flash memory transistor 71 is set in advance so as to indicate V _REF ). In this case, as described above, the detection signal ERR output from the electromagnetic wave irradiation detection circuit 70 indicates a low level voltage.

Here, it is assumed that the electrons accumulated in the floating gate 52 escape from the floating gate 52 by being irradiated with electromagnetic waves. At this time, the threshold voltage of the flash memory transistor 71 is lowered, thereby reducing the on-resistance of the flash memory transistor 71 (hereinafter, appropriately referred to as “R _ON ”). Target voltage _{V OUT} shown in FIG. 9, since the value calculated by dividing the power supply voltage _{V CC} by the resistance ratio of the resistor R1 and the on-resistance _{R ON,} the on-resistance _{R ON} decreases, the resistance R1 The potential difference between both ends increases. As a result, the target voltage V _OUT defined by the voltage at the connection node between the resistor R1 and the drain of the flash memory transistor 71 can be calculated as a value in which the voltage corresponding to the potential difference across the resistor R1 has decreased from the power supply voltage _VCC. The value of V _OUT decreases as the on-resistance _RON decreases.

Here, when the target voltage V _OUT is lowered to a level lower than the reference voltage V _REF due to the irradiation with the electromagnetic wave, a low level voltage is output from the output terminal of the comparator 72, and thus the signal is inverted. Therefore, the detection signal ERR having a high level voltage is output from the electromagnetic wave irradiation detection circuit 70. That is, by detecting that the detection signal ERR output from the electromagnetic wave irradiation detection circuit 70 is a high level voltage, it can be recognized that the electromagnetic wave has been irradiated.

  As shown in FIG. 8, an ERR that is an output signal of the electromagnetic wave detection circuit 70 is an inverted signal of the external reset signal RST during the contact operation, and a power-on reset circuit 80 that is a reset signal during the non-contact operation. And the output signal of the reset signal generation circuit 9 composed of an OR circuit, and the output signal of the reset signal generation circuit 9 is given to the arithmetic and data storage unit 40 as the reset signal RST1. . Therefore, when electromagnetic wave irradiation is detected by the electromagnetic wave irradiation detection circuit 70, an ERR signal having a high level voltage is given to the calculation and data storage unit 40 as the reset signal RST1 via the reset signal generation circuit 9, thereby calculating and The data storage unit 40 is reset. That is, when the irradiation of electromagnetic waves is detected, the calculation and data storage unit 40 is forcibly reset, so that unauthorized rewriting, erasure, or reading of the internal recorded information is prevented by the irradiation of electromagnetic waves. be able to.

JP 2005-149438 A

However, in the above-described conventional configuration, the electromagnetic wave irradiation detection circuit 70 may not realize a desired operation when the power supply voltage _VCC fluctuates.

That is, in the configuration in FIG. 9, for example, when the power supply voltage _VCC is set higher than the specification value for an illegal purpose, the gate voltage of the flash memory transistor 71 increases accordingly. Then, the current flowing through the flash memory transistor 71 (including the series circuit) increases, and as a result, the voltage drop at both ends of the resistor R1 increases, so that the value of the target voltage _VOUT decreases. As a result, the target voltage V _OUT tends to be smaller than the reference voltage V _REF (V _OUT <V _REF ), and as a result, the detection signal ERR output from the electromagnetic wave irradiation detection circuit 70 is likely to output a high level. .

On the contrary, when the power supply voltage _VCC is set lower than the use value, the gate voltage of the flash memory transistor 71 is lowered accordingly, so that the current flowing through the flash memory transistor 71 (including the series circuit) decreases. The value of the target voltage V _OUT increases. As a result, the target voltage V _OUT tends to be larger than the reference voltage V _REF (V _OUT > V _REF ), and as a result, the detection signal ERR output from the electromagnetic wave irradiation detection circuit 70 is likely to output a low level. .

When the IC card 90 performs a non-contact operation, the IC card 90 is fed with power generated by electromagnetic induction by holding the IC card over the magnetic field generated by the non-contact type reader / writer as described above. This is a configuration for performing clock supply, data communication, and the like. Therefore, depending on how the IC card 90 is held up, the distance between the IC card 90 and the reader / titer may change. When the distance between the IC card 90 and the reader / writer is increased, the magnetic field strength decreases, and the current supply capability decreases accordingly. Therefore, when the large current consumption operation (eg a read operation of the flash memory), even at the time of operation start has power supply voltage V _CC reaches the desired voltage, the regulator 17 causes a drop in the power supply voltage V _CC, As a result, the electromagnetic radiation detection circuit 70 may malfunction as described above.

  In addition, when such a malfunction occurs, the IC card 90 is in a reset state, so that it is necessary to perform a recovery process such as reading again after the voltage is restored, and a duplicate operation is required. This causes a problem that the convenience of the IC card is lowered.

  In view of the above problems, an object of the present invention is to provide an electromagnetic wave irradiation detection circuit that does not cause a malfunction even when a power supply voltage changes. It is another object of the present invention to provide a semiconductor device and an IC card that are provided with such an electromagnetic wave irradiation detection circuit and can achieve high security without deteriorating convenience.

  In order to achieve the above object, an electromagnetic wave irradiation detection circuit according to the present invention includes a first series circuit in which a first resistor and a first nonvolatile memory transistor are arranged in series, a second resistor and a second nonvolatile memory transistor. An intermediate point of the first resistor of the first series circuit and the first nonvolatile memory transistor is connected to one input terminal of the second series circuit arranged in series and the pair of differential input terminals, An intermediate point of the second resistor of the second series circuit and the second nonvolatile memory transistor is connected to the other input terminal, and a binary detection signal corresponding to the voltage difference input to the two input terminals is output. A comparison circuit, and a potential at an intermediate point between the first resistor and the first nonvolatile memory transistor, and a potential at an intermediate point between the second resistor and the second nonvolatile memory transistor in the second series circuit. But The on-resistance of the first and second nonvolatile memory transistors changes when the energy of a predetermined amount or more is given by irradiation with electromagnetic waves, and the electromagnetic waves are generated. The first characteristic is that the detection signal changes between a non-irradiated state and an irradiated state in which electromagnetic waves are irradiated, in which a voltage difference inputted to both the input terminals changes.

  According to the first characteristic configuration of the electromagnetic wave irradiation detection circuit according to the present invention, a predetermined node in the first and second series circuits (a connection node between the resistor and the nonvolatile memory transistor, hereinafter simply referred to as “middle point”). Both voltage signals based on this potential are input to both input terminals of the comparison circuit, and a detection signal is output based on the voltage difference between the input voltages. Each series circuit has a resistor and a non-volatile memory transistor, and when the on-resistance of the non-volatile memory transistor changes due to irradiation with electromagnetic waves, the current flowing through the series circuit changes. In this configuration, the potential at the point changes. Therefore, by setting the resistance value of both resistors and the threshold voltage of both nonvolatile memory transistors to a predetermined value in a non-irradiated state in advance, the intermediate point between the two series circuits when the electromagnetic wave is irradiated The potential difference decreases. Therefore, since the voltage level of the detection signal changes by detecting such a change in potential difference, it can be recognized that the electromagnetic wave has been irradiated by confirming this.

  According to this feature configuration, since the potential at both intermediate points is determined according to the power supply voltage, even if the power supply voltage changes, the voltage of both voltage signals input to the comparison circuit The difference does not change to such an extent that the voltage level of the detection signal is changed. For this reason, even when the power supply voltage is changed for an illegal purpose or when the power supply voltage changes depending on the usage state, the electromagnetic wave irradiation can be correctly detected without being affected by these effects.

  According to the electromagnetic wave irradiation detection circuit of the present invention, in addition to the first characteristic configuration, the comparison circuit includes a comparator having an inverting input terminal, a non-inverting input terminal, and an output terminal. The first resistor of the first series circuit is connected to an intermediate point of the first nonvolatile memory transistor, and the non-inverting input terminal is connected to the second resistor of the second series circuit and the second nonvolatile memory. It is connected to an intermediate point of a transistor, and the output terminal outputs a binary voltage signal determined according to a magnitude relationship between two voltages input to the inverting input terminal and the non-inverting input terminal, When the voltage level of the detection signal is determined based on the voltage level of the voltage signal output from the output terminal, and energy of a predetermined amount or more is given by being irradiated with electromagnetic waves, the first and 2 The on-resistance of the non-volatile memory transistor is changed, and the voltage input to the inverting input terminal and the non-inverting input terminal is changed between a non-irradiated state where no electromagnetic wave is irradiated and an irradiated state where the electromagnetic wave is irradiated. A second feature is that the detection signal output from the output terminal changes as the magnitude relationship changes.

  According to the second characteristic configuration of the electromagnetic wave irradiation detection circuit according to the present invention, when electromagnetic waves are irradiated, the magnitude relationship between the two voltages input to the inverting input terminal and the non-inverting input terminal changes. Changes the detection signal. Therefore, it can be recognized that the electromagnetic wave has been irradiated by confirming the change in the voltage level of the detection signal.

  According to this feature configuration, since the potential at both intermediate points is determined according to the power supply voltage, the magnitude of both voltage signals input to the comparison circuit is large even when the power supply voltage changes. The relationship does not reverse with the magnitude relationship under non-irradiation conditions. For this reason, even when the power supply voltage is changed for an illegal purpose or when the power supply voltage changes depending on the usage state, the electromagnetic wave irradiation can be correctly detected without being affected by these effects.

  Here, the comparison circuit further includes a negative circuit, and a negative circuit is connected to the output terminal of the comparator, thereby generating the detection signal by inverting the voltage level of the signal output from the output terminal of the comparator. It is good also as composition to do.

  In addition to the second characteristic configuration, the electromagnetic wave irradiation detection circuit according to the present invention has a resistance value of the first resistor smaller than a resistance value of the second resistor. A third feature is that a threshold voltage of the nonvolatile memory cell is smaller than a threshold voltage of the second nonvolatile memory cell.

  According to the third characteristic configuration of the electromagnetic wave irradiation detection circuit according to the present invention, the voltage level input to the non-inverting input terminal is higher than the voltage level input to the inverting input terminal under the non-irradiation state. . Under such a configuration, when electromagnetic waves are irradiated, both the threshold voltages of both nonvolatile memory transistors are lowered, so that both currents flowing through both series circuits are increased. As a result, when energy of a predetermined amount or more is given by irradiation of electromagnetic waves, the potential difference between both ends of the second resistor having a large resistance value exceeds the potential difference between both ends of the first resistor having a small resistance value, and is input to both input terminals. The magnitude relationship between the voltage levels is reversed, and the voltage level of the detection signal also changes accordingly. Therefore, it is possible to recognize that the electromagnetic wave has been irradiated by confirming the change in the voltage level of the output detection signal.

  In addition to the second or third feature configuration, the electromagnetic wave irradiation detection circuit according to the present invention further includes an electromagnetic wave shielding means in a predetermined area, and a part of the electromagnetic wave irradiated by the electromagnetic wave shielding means is reflected. Thus, the fourth feature is that the amount of energy given to the first nonvolatile memory transistor is smaller than the amount of energy given to the second nonvolatile memory transistor. And

  According to the fourth characteristic configuration of the electromagnetic wave irradiation detection circuit according to the present invention, even when electromagnetic waves are irradiated to both nonvolatile memory transistors, the amount of energy given to both nonvolatile transistors by the irradiation There will be a difference. As a result, a difference can be provided in the change in threshold voltage between the two nonvolatile memory transistors. Therefore, the non-irradiation state of the non-volatile memory transistor of the series circuit on the side where the potential at the intermediate point is set low is set higher than the other non-volatile memory transistors. When the electromagnetic wave is irradiated, the magnitude relationship between the two input voltages input to both input terminals of the comparison circuit is reversed, so that the voltage level of the detection signal is changed, thereby detecting the electromagnetic wave irradiation.

  The electromagnetic wave shielding means may be provided only for the nonvolatile memory transistor on the side where the electromagnetic wave shielding capability is desired to be set high. For example, by providing a difference in the shielding area and the shielding member, The electromagnetic wave shielding means may be provided.

  In the case of this characteristic configuration, the degree of change in the threshold voltage of both nonvolatile memory transistors differs depending on the irradiation of electromagnetic waves, so that even when the resistance values of the first and second resistors are the same, , The magnitude relationship between the two input voltages input to the comparison circuit can be changed.

  According to the electromagnetic wave irradiation detection circuit of the present invention, in addition to the fourth characteristic configuration, the electromagnetic wave shielding means is provided in an upper layer of the formation area of the first nonvolatile memory cell, and the second nonvolatile memory is provided. The fifth feature is that it is not provided in the upper layer of the formation region of the memory cell.

  In addition to the fourth or fifth characteristic configuration, the electromagnetic wave irradiation detection circuit according to the present invention has a sixth characteristic that the electromagnetic wave shielding means is formed of a metal wiring layer.

  Further, in the electromagnetic wave irradiation detection circuit according to the present invention, the first series circuit and the second series circuit are connected in parallel in addition to any one of the first to sixth feature configurations, A first reference voltage is applied to one terminal, a second reference voltage is applied to the other terminal, and the first reference voltage is a power supply voltage or a voltage determined according to the power supply voltage. A seventh feature is that the first reference voltage is applied to both control gates of the first nonvolatile memory transistor and the second nonvolatile memory transistor.

  According to the seventh characteristic configuration of the electromagnetic wave irradiation detection circuit according to the present invention, both ends of both series circuits exhibit the same potential, so that when the power supply voltage changes, both series circuits correspond to the change. That is, the potential at the intermediate point of FIG. That is, since the magnitude relation of the potential at the intermediate point does not change due to the change in the power supply voltage, the electromagnetic wave irradiation can be correctly detected without causing a malfunction.

  The second reference voltage can be a ground voltage, for example.

  Further, in the electromagnetic wave irradiation detection circuit according to the present invention, the first series circuit and the second series circuit are connected in parallel in addition to any one of the first to sixth feature configurations, A first reference voltage is applied to one terminal, a second reference voltage is applied to the other terminal, and the first reference voltage is a power supply voltage or a voltage determined according to the power supply voltage. An output voltage from a voltage generation circuit for performing read, write, or erase processing on the first or second nonvolatile memory transistor with respect to both control gates of the first nonvolatile memory transistor and the second nonvolatile memory transistor The eighth characteristic is that is applied.

  According to the eighth characteristic configuration of the electromagnetic wave irradiation detection circuit according to the present invention, the amount of electrons stored in the floating gates of both the nonvolatile memory transistors can be increased, so that the threshold voltage can be increased. Thereby, since the influence with respect to the threshold voltage when an electromagnetic wave is irradiated and the electric current which flows through both DC circuits can be enlarged, the detection accuracy of an electromagnetic wave irradiation can be improved.

  The electromagnetic wave irradiation detection circuit according to the present invention applies a bias voltage between the source and drain terminals of the first and second nonvolatile memory transistors in addition to any one of the first to eighth characteristic configurations. It is a ninth feature that a bias generation circuit is provided.

  According to the ninth characteristic configuration of the electromagnetic wave irradiation detection circuit according to the present invention, it is configured that a predetermined bias voltage is applied between the drain and the source of both nonvolatile memory transistors under the non-irradiation state. Therefore, by setting the bias voltage to a low voltage in advance, it is possible to prevent a soft program (weak writing) from occurring under a non-irradiation state. As a result, fluctuations in the amount of electrons accumulated in the floating gate of each nonvolatile memory transistor under non-irradiation conditions can be prevented, and electromagnetic wave irradiation detection accuracy can be further improved.

  According to the electromagnetic wave irradiation detection circuit of the present invention, in addition to any one of the first to ninth characteristic configurations, the first and second nonvolatile memory transistors are configured by flash memory transistors. Ten features.

  According to the electromagnetic wave irradiation detection circuit of the present invention, in addition to any one of the first to tenth characteristic configurations, the first and second nonvolatile memory transistors may include a metal wiring layer at a gate and a drain. The area of the metal wiring layer connected to the gate terminal and the drain terminal of the first nonvolatile memory transistor and the gate terminal and the drain terminal of the second nonvolatile memory transistor. The eleventh feature is that the area of the metal wiring layer is different.

  When manufacturing the electromagnetic wave irradiation detection circuit according to the present invention having the eleventh feature configuration, the metal wiring layer is connected to the gate electrode and the drain diffusion layer, and when the metal wiring layer is deposited, Charges are accumulated in the metal wiring layer. For this reason, when writing processing is performed on both nonvolatile memory transistors included in the manufactured electromagnetic wave irradiation detection circuit according to the present invention, the charge accumulated in the metal wiring layer is also taken into the floating gate. The threshold voltage can be changed as compared with a configuration having no wiring layer.

  As the amount of wiring (wiring length, wiring area) of the metal wiring layer connected to the gate electrode and the drain diffusion layer increases, the amount of electrons taken into the metal wiring layer increases. By making a difference between the first and second nonvolatile memory transistors, it is possible to cause a difference in the threshold voltage between the two nonvolatile memory transistors in advance. That is, according to this characteristic configuration, since the threshold voltages of both nonvolatile memory transistors have already been adjusted at the time of manufacture, there is no need to adjust the threshold voltage again. For this reason, when the electromagnetic wave irradiation detection circuit according to the present invention is mounted in a semiconductor device, the semiconductor device does not need to be provided with an adjusting means for adjusting the threshold voltage of both nonvolatile memory transistors, and the scale of the device is large. It can contribute to realization of reduction.

  In order to achieve the above object, a semiconductor device according to the present invention includes an electromagnetic wave irradiation detection circuit having any one of the first to eleventh characteristic configurations, and an activity / activity of the detection signal output from the comparison circuit. A reset signal generation circuit for generating a reset signal based on an inactive state, and a reset operation is performed based on the reset signal output from the reset signal generation circuit.

  According to the first characteristic configuration of the semiconductor device according to the present invention, the configuration includes the electromagnetic wave irradiation detection circuit that can detect the electromagnetic wave irradiation without being affected by the fluctuation of the power source voltage. There is no possibility that the electromagnetic wave irradiation detection circuit malfunctions due to fluctuations and the reset process is executed. Accordingly, since a return process after the reset process is not required due to fluctuations in the power supply voltage, a highly secure semiconductor device can be realized without deteriorating convenience.

  In order to achieve the above object, a semiconductor device according to the present invention includes an electromagnetic wave irradiation detection circuit having any one of the first to eleventh characteristic configurations, and an activity / activity of the detection signal output from the comparison circuit. A reset signal generation circuit that generates a reset signal based on an inactive state; and an invalidation circuit that can invalidate a detection result of the electromagnetic wave irradiation detection circuit, and is output from the reset signal generation circuit. A reset operation is performed based on the reset signal, the invalidation instruction signal indicating an instruction as to whether or not the invalidation circuit executes invalidation processing of the detection result of the electromagnetic wave irradiation detection circuit; When the invalidation instruction signal indicating that the invalidation processing is not performed is input, the detection signal is input to the reset signal generation circuit. When the invalidation instruction signal for executing the invalidation process is input, a voltage signal indicating an inactive state is supplied to the reset signal regardless of activation / inactivation of the detection signal. The second feature is to input to the generation circuit.

  According to the second characteristic configuration of the semiconductor device according to the present invention, the detection result of the electromagnetic wave irradiation detection circuit according to the present invention can be invalidated. For this reason, the threshold voltage of the nonvolatile memory transistor included in the electromagnetic wave irradiation detection circuit does not satisfy the predetermined condition, and the detection signal indicating that the electromagnetic wave irradiation is detected even in the non-irradiation state is output. The threshold voltage of both nonvolatile memory transistors can be adjusted so as to perform the function of electromagnetic wave irradiation detection after executing the invalidation process to invalidate the detection result of the electromagnetic wave irradiation detection circuit.

  According to a third aspect of the present invention, in addition to the second feature configuration, the invalidation circuit is configured such that the invalidation instruction signal can be received from the outside by a test pad. It is characterized by.

  According to the third characteristic configuration of the semiconductor device of the present invention, the detection result of the electromagnetic wave irradiation detection circuit can be invalidated by a simple process when adjusting the threshold voltage of the nonvolatile memory transistor.

  In addition to the second characteristic configuration, the semiconductor device according to the present invention includes an operation reset circuit that outputs a high level operation reset instruction signal when a certain operation condition is satisfied, and a binary voltage level. An invalidation instruction signal generation circuit that generates the invalidation instruction signal and outputs the invalidation instruction signal to the invalidation circuit, wherein the reset signal generation circuit includes the output signal of the invalidation circuit, the operation reset instruction signal, Is input, and the reset signal is generated based on whether any one of the signals is in an active state, and the invalidation instruction signal generation circuit has a predetermined invalidation instruction nonvolatile memory. Temporary binary storage information corresponding to the level of the input voltage level is input together with a high / low binary invalidation sub-instruction signal corresponding to the storage state of the transistor and the operation reset instruction signal. A storable configuration, the fourth being to output the invalidation instruction signal voltage level associated with the temporary storage information different from information stored.

  According to the fourth characteristic configuration of the semiconductor device according to the present invention, it is possible to determine whether or not to execute the invalidation process according to the storage state of the invalidation instruction nonvolatile memory transistor. For this reason, before the assembly into a package or the like, the invalidation instruction nonvolatile memory transistor is set in a storage state indicating a state in which the invalidation process is executed, and after the threshold voltage is adjusted, the invalidation instruction is performed. The storage state of the non-volatile memory transistor can be changed again to change to a storage state indicating that the invalidation process is not executed. The change in the storage state of the nonvolatile memory transistor and the reading of the storage state can be executed in the writing, erasing, and reading processes of a normal nonvolatile semiconductor memory device, and can be programmed in advance. is there. Therefore, according to this characteristic configuration, it is possible to automatically switch between invalidation and validation of the detection result from the electromagnetic wave irradiation detection circuit.

  In order to achieve the above object, the IC card according to the present invention communicates in a non-contact manner with the semiconductor device having any one of the first to fourth characteristic configurations and the non-contact type external device. Is exchanged, and information is exchanged by contact with the contact-type external device and power is supplied from the non-contact-type external device by electromagnetic coupling. One or both of contact-type communication interfaces to which power is supplied are provided.

  According to the above characteristic configuration of the IC card according to the present invention, the reset process is not forcibly executed due to the fluctuation of the power supply voltage, so that the return process after the reset process caused by the malfunction is not required. As a result, an IC card with high security can be realized without reducing convenience.

  According to the configuration of the present invention, it is possible to realize an electromagnetic wave irradiation detection circuit that does not cause a malfunction even when the power supply voltage changes. In addition, by providing the electromagnetic wave irradiation detection circuit according to the present invention, a semiconductor device capable of realizing high security without reducing convenience can be realized.

  In the following, referring to the drawings, each embodiment of an electromagnetic wave irradiation detection circuit according to the present invention (hereinafter referred to as “the present circuit” as appropriate) and a semiconductor device according to the present invention (hereinafter referred to as “the present apparatus” as appropriate) To explain.

  In the following embodiments, the same components as those in the prior art described above with reference to FIGS. 8 to 11 are denoted by the same reference numerals, and detailed description thereof is omitted.

<< Configuration of the Circuit of the Present Invention >>
First, each embodiment of the circuit of the present invention will be described below.

[First Embodiment]
A first embodiment of the circuit of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described with reference to FIGS.

  FIG. 1 is a circuit block diagram showing a schematic configuration of a circuit of the present invention in this embodiment. The circuit 1 of the present invention is different from the conventional electromagnetic wave irradiation detection circuit 70 shown in FIG. 9 in that it has two series circuits composed of a resistor and a flash memory transistor.

  That is, the circuit 1 of the present invention includes a series circuit SC1 configured by arranging the resistor R1 and the flash memory transistor 71a in series, and a series circuit configured by arranging the resistor R2 and the flash memory transistor 71b in series. This is a configuration having two series circuits of SC2. In the following description, the resistor R1, the flash memory transistor 71a, and the series circuit SC1 are referred to as “first resistor R1,” “first flash memory transistor 71a,” and “first series circuit SC1,” respectively. The transistor 71b and the series circuit SC2 are respectively referred to as “second resistor R2”, “second flash memory transistor 71b”, and “second series circuit SC2”. Further, in order to avoid complications due to an increase in the number of symbols, the description will be made assuming that the symbols (R1, R2) attached to the resistors indicate the resistance values of the resistors as they are.

  The first resistor R1 and the second resistor R2 have the same structure and differ only in the resistance value (R1 ≠ R2), and the first flash memory transistor 71a and the second flash memory transistor 71b have the same structure and threshold values. Only the voltage is different.

Each of the first series circuit SC1 and the second series circuit SC2 has a ground voltage applied to one end and a power supply voltage _VCC applied to the other end, and the both constitute a parallel connection. Taking the first series resistor SC1 as an example, the power supply voltage _VCC is applied to one end of the first resistor R1, the drain terminal of the first flash memory transistor 71a is connected to the other end of the first resistor R1, and the first flash The source terminal of the memory transistor 71a is grounded. Similarly to the configuration of FIG. 9, the power supply voltage _VCC is applied to the gate electrode of the first flash memory transistor 71a. The same applies to the second series circuit SC2.

The circuit 1 of the present invention differs from the conventional electromagnetic wave irradiation detection circuit 70 shown in FIG. 9 in the voltage input to the input terminal of the comparator 72. That is, as shown in FIG. 1, the comparator 72 included in the circuit 1 of the present invention has a voltage (hereinafter referred to as “first object”) indicated by a connection node between the first resistor R1 and the first flash memory transistor 71a in the first series circuit SC1. V _OUT1 is input to the inverting input terminal 72im, and a voltage indicated by a connection node between the second resistor R2 and the second flash memory transistor 71b in the second series circuit SC2 (hereinafter referred to as “second target voltage”). (Described) V _OUT2 is input to the non-inverting input terminal 72ip. That is, the reference voltage _VREF is not input to one input terminal of the comparator 72.

Under the above connection relation, the level of the detection signal ERR is determined by the magnitude relation between the first target voltage V _OUT1 and the second target voltage V _OUT2 . That is, the circuit 1 of the present invention outputs a low level voltage (for example, ground voltage) as the detection signal ERR when V _OUT1 <V _{OUT2, and} a high level voltage (as the detection signal ERR when V _OUT1 > V _OUT2 ). For example, 3V) is output.

Whether one of the first target voltage V _OUT1 and the second target voltage V _OUT2 has a large voltage value depends on the resistance values of the resistors R1 and R2 and the threshold voltage of the flash memory transistors 71a and 71b. Here, it is assumed that both resistors R1 and R2 have a relationship of R1 <R2, and the threshold voltages of the flash memory transistors 71a and 71b are set so that V _OUT1 <V _OUT2 in a non-irradiation state. Shall. That is, when the threshold voltage of the first flash memory transistor 71a is V _th1 and the threshold voltage of the second flash memory transistor 71b is V _th2 , at least V _th1 <V _th2 is established under the non-irradiation state. And At this time, the circuit 1 of the present invention outputs a low level voltage under the non-irradiation state and outputs a signal indicating that the electromagnetic wave irradiation is not detected.

  The case where electromagnetic waves are irradiated to the circuit 1 of the present invention under such a configuration will be examined. As described above, when the flash memory transistor is irradiated with ultraviolet rays, the threshold voltage decreases. However, the threshold voltage does not decrease below a certain value (for example, 2 V, hereinafter referred to as “minimum threshold voltage” as appropriate). That is, when an electromagnetic wave is irradiated to both flash memory transistors 71a and 71b, any threshold voltage decreases with the irradiation of the electromagnetic wave, but the threshold voltage decreases when a predetermined amount or more is irradiated. I can't see it. Here, as described above, since both flash memory transistors 71a and 71b have the same structure, the minimum threshold voltages of both flash memory transistors have substantially the same value.

  Therefore, when the threshold voltage of both flash memory transistors decreases with the irradiation of the electromagnetic wave, the threshold voltage of the first flash memory transistor 71a, which has been set low in advance under the non-irradiation state, becomes the first threshold voltage. The value becomes near the minimum threshold voltage before the threshold voltage of the two flash memory transistor 71b. As the threshold voltage approaches the minimum threshold voltage, the threshold voltage decreases at a slower rate. Therefore, the threshold voltage of the first flash memory transistor 71a gradually decreases than the second flash memory transistor 71b. Become. As a result, the difference between the threshold voltages of both flash memory transistors is gradually reduced.

  As described above, when the threshold voltage of the flash memory transistor is lowered, the on-resistance is reduced, so that the drain current, that is, the current flowing through each series circuit increases. Then, as the threshold voltage of the first flash memory transistor 71a approaches the minimum threshold voltage, the rising speed of the current flowing through the first series circuit SC1 (hereinafter referred to as “first current I1”) causes the second series circuit SC2 to increase. It becomes slower than the rising speed of the flowing current (hereinafter referred to as “second current I2”).

Here, each of the target voltages V _OUT1 and V _OUT2 is a value obtained by reducing a voltage corresponding to the potential difference between both ends of the resistor R1 or R2 from the common power supply voltage _VCC. The target voltage will decrease. As described above, since R1 <R2 and the rising speed of the second current I2 is faster than the rising speed of the first current I1, when a predetermined time elapses, the potential difference between both ends of the resistor R2 becomes the potential difference between both ends of the resistor R1. It will exceed. That is, at this time, the magnitude relationship between the first target voltage V _OUT1 and the second target voltage V _OUT2 is reversed (V _OUT1 > V _OUT2 ), and a high level voltage (for example, 3 V) is output as the detection signal ERR. Thereby, the circuit 1 of the present invention outputs a signal indicating that the electromagnetic wave irradiation has been detected.

  Therefore, according to the above configuration, the circuit 1 of the present invention changes the level of the detection signal ERR from the low voltage to the high voltage when the electromagnetic wave is irradiated. Can be recognized.

Here, the operation of the circuit 1 of the present invention when the power supply voltage _VCC fluctuates under the non-irradiation state will be considered.

Also in the configuration of the circuit 1 of the present invention, since the power supply voltage _VCC is input to one end of the resistor constituting the series circuit as in the conventional configuration, if the power supply voltage _VCC fluctuates, the current flowing through the series circuit is also changed to this. It changes with it. However, in the configuration of the circuit 1 of the present invention, the first target voltage V _OUT1 and the second target voltage V _OUT2 are input to the comparator 72. Both target voltages are determined based on the first current I1 and the second current I2. Although the currents (I1 and I2) flowing through both series circuits change as the power supply voltage _VCC changes, the higher the threshold voltage, the smaller the current flowing through the series circuit. As described above, under the non-irradiation state, the threshold voltages of both flash memory transistors are set so that V _th1 <V _th2, and therefore the second flash memory transistor 71b whose threshold voltage is still set high is set. The second current I2 flowing through the second series circuit SC2 provided has a smaller value than the first current I1 flowing through the first series circuit SC1 provided with the first flash memory transistor 71a.

Since R2> R1 as described above, even if the power supply voltage _VCC varies, the potential difference between both ends of the resistor R2 is still maintained larger than the potential difference between both ends of the resistor R1. As a result, since the first target voltage V _OUT1 still has a smaller value than the second target voltage V _OUT2 , the circuit 1 of the present invention outputs a low level voltage as the detection signal ERR.

Therefore, according to the configuration of the circuit 1 of the present invention, even when the power supply voltage _VCC fluctuates, it is not affected by the fluctuation of the power supply voltage unlike the conventional configuration. For this reason, even when the power supply voltage _VCC is changed for an illegal purpose or when the power supply voltage _VCC changes depending on the use state, it is possible to correctly detect the electromagnetic wave irradiation without being affected by them. .

In the present embodiment, the comparison circuit 74 includes a comparator 72 and a negation circuit 73, the first target voltage V _OUT1 is at the inverting input terminal of the comparator 72, and the second target voltage V _OUT2 is at the non-inverting input terminal. However, if there is a means for comparing the magnitude relationship between the two target voltages V _OUT1 and V _OUT2 and generating a voltage having a different level when this relationship is reversed, the comparison circuit 74 The configuration is not necessarily limited to the configuration shown in FIG. Another example different from the configuration of FIG. 1 is shown in FIG.

The comparison circuit 74a shown in FIG. 2 includes comparators 72a, 72b, and 72c. In the comparator 72a, the first target voltage V _OUT1 is input to the inverting input terminal, and the second target voltage V _OUT2 is input to the non-inverting input terminal. Unlike the comparator 72a, the comparator 72b receives the first target voltage V _OUT1 at the non-inverting input terminal and the second target voltage V _OUT2 at the inverting input terminal. In the comparator 72c, the output voltage V _oa of the comparator 72a is input to the inverting input terminal, and the output voltage V _ob of the comparator 72b is input to the non-inverting input terminal. At least the high level voltage output from the comparator 72a is higher than the low level voltage output from the comparator 72b, and the low level voltage output from the comparator 72a is lower than the high level voltage output from the comparator 72b. . Of course, the comparators 72a and 72b may be composed of the same circuit.

In the case of the circuit configuration as described above, since V _OUT1 <V _OUT2 under the non-irradiation state, the comparator 72a outputs a high level voltage as the output voltage V _oa and the comparator 72b outputs a low level as the output voltage V _ob. Output voltage. At this time, since the low level voltage is output from the comparator 72c, the detection signal ERR indicates the low level voltage.

On the other hand, when electromagnetic wave irradiation is detected and the magnitude relationship between the two target voltages is reversed and V _OUT1 > V _OUT2 , the comparator 72a outputs a low level voltage as the output voltage V _oa , and the comparator 72b is high as the output voltage V _obs. Output level voltage. At this time, since the high level voltage is output from the comparator 72c, the detection signal ERR indicates the high level voltage. Therefore, by confirming the voltage level of the detection signal ERR, it is possible to recognize that the electromagnetic wave has been irradiated, as in FIG.

In the case of this embodiment described above, a high-level detection signal ERR is output when the magnitude relationship between the first target voltage V _OUT1 and the second target voltage V _OUT2 is inverted by irradiation with electromagnetic waves. Therefore, in other words, when the irradiation amount of electromagnetic waves is within a range that does not reverse the magnitude relationship between the two target voltages, the configuration of the circuit 1 of the present invention cannot detect the irradiation of electromagnetic waves.

However, as described above, the current flowing through both series circuits SC1 and SC2 changes due to irradiation with electromagnetic waves, and the rate of change differs between the two series circuits. Both target voltages V _OUT1 and V _OUT2 are voltage values determined by currents flowing through both series circuits SC1 and SC2, respectively. However, when electromagnetic waves are irradiated, the voltage difference between both target voltages changes. Become.

In particular, in the case of the configuration of FIG. 1, when the electromagnetic wave is irradiated, the rising speed of the current I2 flowing through the series circuit SC2 is faster than the rising speed of the current I1 flowing through the series circuit SC1, so As a result, the second target voltage V _OUT2 decreases faster than the first target voltage V _OUT1 . That is, the second target voltage _{V OUT2} which showed a higher voltage value than the first target voltage _{V OUT1} is, to lower faster than the first target voltage _{V OUT1,} the voltage difference between the target voltage is gradually narrowed.

  Therefore, when the voltage difference between the two target voltages is within a predetermined range, an electromagnetic wave within a range in which the magnitude relationship between the two target voltages is not reversed is configured by outputting a high level detection signal ERR. Even in the case of the irradiation amount, the electromagnetic wave irradiation can be detected. As an example, the offset voltage of the comparator can be used.

  Assume that the comparator 72 shown in FIG. 1 has a predetermined offset α. At this time, when the voltage obtained by adding the offset α to the input voltage of the inverting input terminal 72im is lower than the input voltage of the non-inverting input terminal 72ip, a high-level output voltage is output from the output terminal 72io. It is assumed that when the voltage obtained by adding the offset α to the input voltage of the inverting input terminal 72im is higher than the input voltage of the non-inverting input terminal 72ip, a low level output voltage is output from the output terminal 72io.

In such a case, even if the magnitude relationship between the two target voltages V _OUT1 and V _OUT2 is not reversed, a low level output voltage is output from the output terminal 72io when the voltage difference between the two voltages becomes equal to or less than the offset α. The voltage level of the detection signal ERR changes to a high level. Thereby, irradiation of electromagnetic waves can be detected.

  However, when performing voltage detection using the offset voltage α under the configuration of FIG. 1, a negation circuit 73 connected to the subsequent stage of the comparator 72 near the threshold value at which the voltage level output from the output terminal 72io changes. There is also a possibility that the detection signal ERR output from is not stabilized. On the other hand, when the comparison circuit 74 is configured by only the differential amplification type comparator as shown in FIG. 2, a stable output is shown even in the vicinity of the threshold at which the voltage level of the detection signal ERR changes. .

  In the above description, each of the memory transistors 71a and 71b is constituted by a flash memory transistor, but may be constituted by another nonvolatile memory transistor such as an EEPROM. The same applies to the following embodiments.

  Further, in the above-described embodiment, it has been described that the circuit 1 of the present invention has a function of detecting the irradiation of “electromagnetic waves”. However, the term “electromagnetic waves” here includes general ultraviolet rays, X-rays, gamma rays, and the like. This suggests an effective energy emission. In other words, the circuit 1 of the present invention may be configured to be capable of detecting at least one of energy irradiations among electromagnetic waves such as ultraviolet rays, X-rays, and gamma rays. The same applies to the following embodiments.

[Second Embodiment]
A second embodiment of the circuit of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described with reference to FIG. In addition, about the component same as 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  FIG. 3 is a circuit block diagram showing a schematic configuration of the circuit of the present invention in this embodiment. 1a in the present embodiment is different from the circuit 1 of the present invention in the first embodiment in that it further includes a bias generation circuit 30 and MOS transistors 31a and 31b (here, N-channel type).

  The MOS transistor 31a forms a first series circuit SC1 together with the first resistor R1 and the first flash memory transistor 71a, and is interposed between the first resistor R1 and the drain of the first flash memory transistor 71a. More specifically, the MOS transistor 31 has a drain connected to one end of the first resistor R1, a source connected to the drain of the first flash memory transistor 71a, and a gate connected to the bias generation circuit 30. Similarly, the MOS transistor 31b, like the MOS transistor 31a, constitutes a second series circuit SC2 together with the second resistor R2 and the second flash memory transistor 71b, and the drain is connected to one end of the second resistor R2, The source is connected to the drain of the second flash memory transistor 71b, and the gate is connected to the bias generation circuit 30.

  The bias generation circuit 30 is applied to the gate terminals of both MOS transistors 31a and 31b so that a bias voltage of about 1 V at maximum is applied between the drain and source of both flash memory transistors 71a and 71b in a non-irradiated state. A predetermined voltage is applied.

  With this configuration, under the non-irradiation state, a low bias voltage set in advance is applied between the drain and source of both flash memory transistors 71a and 71b. Under this, it is possible to prevent a soft program (weak writing) for the flash memory transistors 71a and 71b. As a result, it is possible to prevent the amount of electrons accumulated in the floating gates of the flash memory transistors 71a and 71b from fluctuating in a non-irradiated state, thereby further improving electromagnetic wave irradiation detection accuracy. Can do.

Further, since the same voltage is applied from the bias generation circuit 30 to the gates of the MOS transistors 31a and 31b, the electromagnetic wave irradiation detection accuracy is not lowered by the application of the voltage. Similarly, it is possible to correctly detect electromagnetic wave irradiation without being affected by fluctuations in the power supply voltage _VCC .

[Third Embodiment]
A third embodiment of the circuit of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described below. In addition, about the component same as 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  In the present embodiment, the first resistor R1 and the second resistor R2 have the same resistance value (R1 = R2), except that a metal wiring layer is provided in the upper layer portion of the first flash memory transistor 71a. This is the same as the configuration (FIG. 1). Hereinafter, description will be given with reference to FIG. In addition, in order to distinguish from the circuit 1 of the present invention according to the first embodiment, the circuit of the present invention in this embodiment is referred to as “the circuit 1b of the present invention” (not shown).

Since R1 = R2, the first current I1 and the second current I2 depend only on the threshold voltage of each flash memory transistor. As described above in the first embodiment, under the non-irradiation state, V _th1 <V _th2 is set so that I1> I2 is satisfied under this state. Therefore, since the potential difference between both ends of the first resistor R1 is larger than the potential difference between both ends of the second resistor R2, V _OUT1 <V _OUT2 is established, and the low level voltage detection signal ERR is output.

Even when the power supply voltage _VCC varies, the same power supply voltage is applied to the gates of both flash memory transistors. Therefore, as described above in the first embodiment, the threshold values of both flash memory transistors are used. The magnitude relationship between the voltages is not reversed, and the voltage level of the detection signal ERR is not affected.

  Considering the case where electromagnetic waves are irradiated to the circuit 1b of the present invention under such a configuration. At this time, since the metal wiring layer is formed on the first flash memory transistor 71a, a part of the electromagnetic wave irradiated by the metal wiring layer is shielded. As a result, the first flash memory transistor 71a The amount of electromagnetic wave energy applied to is reduced as compared with the case where the metal wiring layer is not present. On the other hand, since the metal wiring layer is not formed in the upper layer portion of the second flash memory transistor 71b, the amount of energy larger than that of the first flash memory transistor 71a is greater than that of the first flash memory transistor 71a due to the electromagnetic wave irradiation. Given.

As a result, the threshold voltage of the second flash memory transistor 71b is greatly reduced than the threshold voltage of the first flash memory transistor 71a. As a result, the rising speed of the second current I2 becomes faster than the rising speed of the first current I1, and when a predetermined time elapses, the potential difference between both ends of the resistor R2 exceeds the potential difference between both ends of the resistor R1. At this time, the magnitude relationship between the first target voltage V _OUT1 and the second target voltage V _OUT2 is reversed (V _OUT1 > V _OUT2 ), and a high level voltage (for example, 3 V) is output as the detection signal ERR. Thereby, the circuit 1 of the present invention outputs a signal indicating that the electromagnetic wave irradiation has been detected.

In this embodiment, the resistance values are the same (R1 = R2), and only the threshold voltages of both flash memory transistors are different. However, V _OUT1 <V _OUT2 is established under the non-irradiation state. If the resistance value is set to be different, the threshold voltage of both flash memory transistors may be set to the same voltage value, and both resistance values and both flash values may be set as in the first embodiment. Both threshold voltages of the memory transistors may be set to different values.

  In the present embodiment, the metal wiring layer is provided in the upper layer portion of the first flash memory transistor 71a. However, any structure having a function of shielding electromagnetic waves may be used, and the structure is limited to the metal wiring layer. It is not something. In addition, since the first flash memory transistor 71a may be configured to shield more electromagnetic waves than the second flash memory transistor 71b, so long as such a condition is satisfied, for example, An electromagnetic shielding means such as a metal wiring layer may also be provided in the upper layer portion of the second flash memory transistor 71b.

  Further, in the present embodiment, similarly to the second embodiment, the bias generation circuit 30 and the MOS transistors 31a and 31b may be provided. The same applies to the following fourth and fifth embodiments.

[Fourth Embodiment]
A fourth embodiment of the circuit of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described with reference to FIG. In addition, about the component same as 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  FIG. 4 is a circuit block diagram showing a schematic configuration of the circuit of the present invention in this embodiment. 1c in the present embodiment is different from the circuit 1 of the present invention in the first embodiment in that a voltage generation circuit 21 is further provided.

  The voltage generation circuit 21 is a circuit that generates a voltage for executing each process of reading, writing, or erasing with respect to a nonvolatile semiconductor memory device such as a flash memory provided outside the circuit 1c of the present invention.

The present invention circuit 1c, the flash memory transistors 71a and 71b are, with respect to the gate terminal, rather than the power supply voltage V _CC, a configuration in which the output voltage from the voltage generating circuit 21 is applied.

The output voltage from the voltage generation circuit 21 is set to be larger than the power supply voltage _VCC . For example, when the power supply voltage _VCC is about 3V, the voltage generation circuit 21 generates a voltage of about 5V. Is output. With such a configuration, the amount of electrons accumulated in the floating gates of both flash memory transistors 71a and 71b can be increased as compared with the first embodiment in which the power supply voltage _VCC is applied to the control gate. Therefore, the threshold voltage can be increased. Thereby, since the influence with respect to the threshold voltage and electric current (I1 and I2) when electromagnetic waves are irradiated can be enlarged, the detection accuracy of electromagnetic wave irradiation can be improved.

[Fifth Embodiment]
A fifth embodiment of the circuit of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described below. In addition, about the component same as 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted. In addition, in order to distinguish from the circuit 1 of the present invention according to the first embodiment, the circuit of the present invention in the present embodiment is referred to as “present circuit 1d” (not shown).

  This embodiment is different from the first to fourth embodiments in that the metal wiring layer is connected to the gate and drain of the flash memory transistors 71a and 71b when manufacturing the circuit of the present invention. Common to each embodiment.

That is, in the above embodiments, the threshold voltages of both the flash memory transistors 71a and 71b are adjusted under a predetermined condition together with the resistors R1 and R2 so that V _OUT1 <V _OUT2 in the non-irradiation state. There was a need.

  As in the circuit 1d of the present invention, the metal wiring layer is connected in advance to the gate electrode and the drain diffusion layer at the time of manufacturing. For example, when the metal wiring layer is deposited by a sputtering process, Charge is accumulated. As a result, when a high voltage is applied to the gate and drain after the manufacture of the circuit of the present invention is completed, the charge accumulated in the metal wiring layer is taken into the floating gate and writing is performed. For this reason, the threshold voltage of the flash memory transistor can be increased as compared with the configuration without the metal wiring layer.

  As the wiring amount (wiring length, wiring area) of the metal wiring layer connected to the gate electrode or the drain diffusion layer increases, the amount of electrons taken into the metal wiring layer increases. The amount of electrons taken in will also increase. Therefore, by manufacturing the flash memory transistor by varying the wiring amount of the metal wiring layer connected to the gate electrode or the drain diffusion layer, the threshold voltage of the completed flash memory transistor can be varied. Therefore, by using the two flash memory transistors having different manufacturing conditions as the flash memory transistors 71a and 71b, it is not necessary to adjust the threshold voltage of each flash memory transistor when detecting electromagnetic wave irradiation.

<< Configuration of the Device of the Present Invention >>
Next, each embodiment of the apparatus of the present invention will be described below. Note that the same components as those of the conventional IC card 90 shown in FIG.

[First Embodiment]
A first embodiment of the device of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described with reference to FIG.

  FIG. 5 is a circuit block diagram showing a schematic configuration of the device of the present invention in the present embodiment. Compared with the conventional IC card 90 shown in FIG. 8, the device 2 of the present invention is configured to include the circuit 1 (or 1a, 1b, 1c, 1d) of the present invention instead of the conventional electromagnetic wave irradiation detection circuit 70. The others are the same as the configuration of FIG.

  That is, in addition to the output signal of the power-on reset circuit 80 and the external reset signal RST (negative signal), the detection signal ERR output from the circuit 1 of the present invention is given to the reset signal generation circuit 9. The reset signal generation circuit 9 is configured by an OR circuit, and is configured to supply a binary voltage signal based on the OR operation of these three signals to the calculation and data storage unit 40 as the reset signal RST1. When the high level (active state) reset signal RST1 is given to the arithmetic and data storage unit 40, the reset process is executed, and the device 2 of the present invention shifts to the reset state.

In this configuration, when the circuit 1 of the present invention detects the irradiation of electromagnetic waves and outputs a detection signal ERR having a high level voltage, the reset signal generation circuit 9 to which the detection signal ERR has been supplied resets the high level voltage. The signal RST1 is given to the calculation and data storage unit 40, whereby the inventive device 2 is in a reset state. As described above, the inventive circuit 1 is a configuration that can be detected electromagnetic radiation without being affected by fluctuations in the power supply voltage V _CC, is not to be malfunctioning by fluctuations in the power supply voltage V _CC. Therefore, unlike the conventional configuration, the electromagnetic wave irradiation detection circuit 70 malfunctions, so that the high level voltage detection signal ERR is output, and the reset process is not executed due to such malfunction.

  As a result, when the device 2 of the present invention is mounted as an IC card, a return process after a reset process caused by a malfunction like the conventional IC card 90 is not required, so that the convenience is not reduced. An IC card with high security can be realized.

  The present invention device 2 is not limited to an IC card mounted in a card shape, but is a semiconductor device using an RFID (Radio Frequency IDentification) technology such as an IC chip or IC tag. If so, the name and shape are not bound. The same applies to each of the following embodiments.

[Second Embodiment]
A second embodiment of the device of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described with reference to FIG. In addition, about the component same as 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  FIG. 6 is a circuit block diagram showing a schematic configuration of the device of the present invention in the present embodiment. The inventive device 2a is different from the inventive device 2 in the first embodiment in that it further includes an invalidation circuit 4.

  The invalidation circuit 4 has a function of invalidating the detection result indicated by the detection signal ERR output from the circuit 1 of the present invention based on the input of the invalidation instruction signal ERRDIS. As shown in FIG. 6, in the present embodiment, the detection signal ERR is not input directly to the reset signal generation circuit 9 but is input to the invalidation circuit 4. The invalidation circuit 4 receives inputs of the invalidation instruction signal ERRDIS and the detection signal ERR, performs a logical operation using the signals, and gives the calculation result to the reset signal generation circuit 9. The signal output from the invalidation circuit 4 is hereinafter referred to as “detection modification signal ERR1”.

  The invalidation circuit 4 outputs a detection modification signal ERR1 having a low level voltage regardless of whether the level of the detection signal ERR is high or not when the invalidation instruction signal ERRDIS having a high level voltage (for example, a power supply voltage) is input. When the invalidation instruction signal ERRDIS of the low level voltage (for example, ground voltage) is input, the detection modification signal ERR1 having a level corresponding to the level of the detection signal ERR is output.

  In other words, while the high-level voltage invalidation instruction signal ERRDIS is input, even if the detection signal ERR indicates a high-level voltage, the detection result of the circuit 1 of the present invention is invalidated, as if this The invention circuit 1 gives a signal to the reset signal generation circuit 9 that the electromagnetic wave irradiation is not detected.

  On the other hand, while the low level voltage invalidation instruction signal ERRDIS is being input, the level of the voltage level of the detection signal ERR output from the circuit 1 of the present invention is directly input to the reset signal generation circuit 9 as in the first embodiment. As a result, the detection result of the circuit 1 of the present invention is sent to the reset signal generation circuit 9. That is, when the detection signal ERR is a high level voltage, the high level voltage detection modification signal ERR1 is supplied to the reset signal generation circuit 9, and when the detection signal ERR is a low level voltage, the low level voltage detection modification is performed. The signal ERR1 is supplied to the reset signal generation circuit 9.

The inventive circuit 1 (or 1a, 1b, 1c, 1d) provided in the inventive device 2a includes the first flash memory transistor 71a and the second flash memory transistor 71b as described above. Since the circuit 1 of the present invention is manufactured through a normal semiconductor process such as a sputtering method or an etching method, the second flash memory transistor 71b included in the circuit 1 of the present invention after the manufacture depends on conditions at the time of manufacture. threshold voltage _{V th2} is, it is considered to be lower than the threshold voltage _{V th1} of the first flash memory transistor 71a.

  When such a situation occurs, in the configuration of the circuit 1 of the present invention shown in FIG. 1, a detection signal ERR having a high level voltage is output although the irradiation of electromagnetic waves is not detected. As a result, with the configuration of the inventive device 2 of the first embodiment shown in FIG. 5, the reset process is executed even though the irradiation of the electromagnetic wave is not detected.

According to the configuration of the inventive device 2a according to the present embodiment, even if V _th2 <V _th1 , the high level invalidation instruction signal ERRDIS is given to the invalidation circuit 4 Thus, the output signal ERR output from the circuit 1 of the present invention can be invalidated (hereinafter, this state is referred to as “invalidated state” as appropriate). Then, under this invalidation state, the threshold voltage of both flash memory transistors 71a and 71b is adjusted so that V _th1 <V _th2 is established, and then the invalidation instruction signal ERRDIS is set to a low level, whereby It is possible to shift to a state in which the reset process can be executed based on the electromagnetic wave irradiation detection result of 1.

  As a method of adjusting the threshold voltage of each flash memory transistor 71a, 71b, hot electrons are injected into or extracted from the floating gate.

  For example, when it is desired to increase the threshold voltage, a write operation to the flash memory transistor to be increased, that is, a high voltage (for example, 12V) is applied to the control gate, a high voltage (for example, 7V) is applied from the bit line to the drain, and the source is applied. A low voltage (for example, 0 V) is applied, and hot electrons generated near the drain junction are injected into the floating gate. On the other hand, when it is desired to lower the threshold voltage, erase processing is performed on the flash memory transistor to be lowered to sufficiently reduce the threshold voltage, and then writing is performed as described above so that the desired threshold voltage is obtained. The operation is executed to increase the voltage to a certain extent. When executing the erasing process, a low voltage (for example, 0 V) is applied to the control gate, a low voltage (for example, 0 V) is applied from the bit line to the drain, and a high voltage (for example, 12 V) is applied to the source. A high electric field is generated between them, and electrons in the floating gate are extracted to the source side using a tunnel phenomenon.

  The fine adjustment of the threshold voltage can be performed using a soft program (weak writing). For example, a high voltage (for example, 12V) is applied to the control gate during normal write / write operation, but a lower voltage (for example, about 6V) may be applied during soft programming. In addition, it is also possible to realize a soft program by applying a voltage that is lower than the normal write voltage to the drain voltage.

  If the flash memory transistor does not have a metal wiring layer in the upper layer portion, it is possible to adjust the threshold voltage by irradiating the flash memory transistor with ultraviolet rays in an invalid state. .

  As an input method of the invalidation instruction signal ERRDIS, for example, a method of inputting a signal from the outside using a dedicated test pad is possible. That is, only when it is desired to invalidate the detection signal ERR from the circuit 1 of the present invention, a high-level voltage signal (invalidation instruction signal ERRDIS) is input to the invalidation circuit 4 via the test pad and invalidated. When canceling (validating) the signal, the signal input from the test pad is not performed, so that the detection signal ERR from the circuit 1 of the present invention can be switched between valid / invalid.

At this time, the test pad is not bonded to the external terminal at the time of assembly with respect to a package such as a module, so that it can be invalidated only at the time of manufacture. In addition, after adjusting the threshold voltages of both flash memory transistors 71a and 71b so that V _th1 <V _th2 is satisfied under the invalidation state, the test pad and the invalidation instruction signal ERRDIS are separated by a fuse to manufacture It can be invalidated only at the time. If the test pad is not bonded to an external terminal during assembly, the invalidation instruction signal ERRDIS is set to a low level (ground voltage) even when the invalidation instruction signal ERRDIS is separated from the test pad by a fuse. It is necessary to set. The fuse may be either a laser fuse or an electrical fuse.

Further, as described above, in the inventive circuit 1d according to the fifth embodiment, since the threshold voltage of each flash memory transistor can be adjusted in advance at the time of manufacture, the inventive device 2a is not limited to the inventive circuit 1d. It is useful when the present invention circuit 1, 1a, 1b, 1c is provided. However, even if the circuit 1d according to the present invention is provided, the threshold voltage can be adjusted as an invalidation state in the event that V _th2 <V _th1 by any chance. It is useful to configure the device 2a. This also applies to the following third embodiment.

  In the device 2a of the present invention shown in FIG. 6, the invalidation circuit 4 performs a logical product operation of the negative circuit 33 that receives the input of the invalidation instruction signal ERRDIS, and the output signal of the negative circuit 33 and the detection signal ERR. The logical sum circuit 34 outputs the calculation result as the detection modification signal ERR1. However, this circuit configuration is merely an example, and any circuit configuration capable of realizing the above-described logical contents may be used. It is not limited to.

[Third Embodiment]
A third embodiment of the device of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described with reference to FIG. In addition, about the component same as 1st or 2nd embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  FIG. 7 is a circuit block diagram showing a schematic configuration of the device of the present invention in the present embodiment. Compared with the inventive device 2a in the second embodiment, the inventive device 2b includes an invalidation circuit 4a instead of the invalidation circuit 4, and further includes an invalidation instruction signal generation circuit 5 and an operation reset circuit 6. Is different.

  Unlike the invalidation circuit 4 according to the second embodiment, the invalidation circuit 4a has a high or low level of the detection signal ERR when the invalidation instruction signal ERRDIS having a low level voltage (for example, a power supply voltage) is input. Regardless of the case, when the low level voltage detection modification signal ERR1 is output and the high level voltage (for example, ground voltage) invalidation instruction signal ERRDIS is input, the level of the detection signal ERR is high or low. The detection modification signal ERR1 is output. In FIG. 7, the invalidation circuit 4a is composed of only the AND circuit 34. However, the circuit configuration is not limited to this as long as the circuit configuration can realize the logical contents.

  The operation reset circuit 6 accepts input of a reset signal during contact operation and non-contact operation, and when any of them is in a reset state, a high-level voltage signal (hereinafter referred to as “operation reset instruction signal RSD”). Is supplied to the invalidation instruction signal generation circuit 5, and if none of them is in the reset state, the low level operation reset instruction signal RSD is provided to the invalidation instruction signal generation circuit 5.

  The invalidation instruction signal generation circuit 5 receives an operation reset instruction signal RSD from the operation reset circuit 6 and a high / low binary level voltage signal (hereinafter referred to as an “invalidation subinstruction signal”) provided via the control bus. In addition to the configuration that is input, the configuration is such that the voltage level of the invalidation sub-instruction signal can be temporarily stored. For example, it is configured by a register circuit. Further, the invalidation instruction signal generation circuit 5 is configured to perform reset processing on stored information (hereinafter referred to as “temporary storage information”) when a high-level operation reset instruction signal RSD is input. Suppose that Further, the invalidation instruction signal generation circuit 5 generates an invalidation instruction signal ERRDIS having a voltage level associated with the temporarily stored information that is currently stored, and outputs it to the invalidation circuit 4a.

  For example, when a high-level invalidation sub-instruction signal is input to the invalidation instruction signal generation circuit 5, the fact that it is in a high level state (hereinafter referred to as “information H”) is stored as temporary storage information, On the other hand, when a low level invalidation sub instruction signal is input, the fact that it is in a low level state (hereinafter referred to as “information L”) is stored as temporary storage information. At this time, when the invalidation instruction signal generation circuit 5 stores the information H as the temporary storage information, the invalidation instruction signal ERRDIS having a voltage level corresponding to the stored information H, that is, a high level is displayed. On the contrary, when information L is stored as temporary storage information, a voltage level corresponding to the stored information L, that is, a low level invalidation instruction signal ERRDIS is generated. When a high-level operation reset instruction signal RSD is input to the invalidation instruction signal generation circuit 5, the temporarily stored information is forcibly reset, information L is stored, and a low-level invalidation signal is stored. The instruction signal ERRDIS is generated and the state becomes invalid.

  Here, it is assumed that the invalidation sub instruction signal is a voltage signal corresponding to an inverted value of a read voltage (current) value of a predetermined invalidation instruction flash memory transistor NT (see FIG. 7) in the flash macro 20. . Specifically, when the invalidation instruction flash memory transistor is in a write state, the read voltage is low, and therefore, a high-level invalidation sub-instruction signal that is an inverted value thereof is an invalidation instruction signal generation circuit. Is given for 5. On the other hand, when the invalidation instruction flash memory transistor is in the erased state, the read voltage is at a high level. Therefore, a low-level invalidation sub instruction signal, which is an inverted value thereof, is sent to the invalidation instruction signal generation circuit 5. Given to.

  First, after the manufacture of the device 2b of the present invention is completed, before the assembly into a package or the like, for example, during an inspection process in a wafer state, an electromagnetic wave such as ultraviolet rays is irradiated onto the invalidation instruction flash memory transistor NT to be in an erased state. Is a high level. As a result, the invalidation sub instruction signal becomes a low level voltage, and therefore the invalidation instruction signal generation circuit 5 stores information L as temporary storage information.

At this time, the invalidation instruction signal generation circuit 5 outputs a low-level invalidation instruction signal ERRDIS to the invalidation circuit 4a, whereby the circuit 1 of the present invention enters the invalidation state. Therefore, as described above in the second embodiment, the threshold voltages of both flash memory transistors 71a and 71b can be adjusted so that V _th1 <V _th2 is satisfied under such an invalidation state.

  After adjusting the threshold voltages of both flash memory transistors, a write operation is performed on the invalidation instruction flash memory transistor NT. As a result, the read voltage of the flash memory transistor NT becomes a low level, and thus a high level invalidation sub instruction signal which is an inverted value thereof is given to the invalidation instruction signal generation circuit 5. As a result, the invalidation instruction signal generation circuit 5 stores the information H as temporary storage information, the invalidation state is canceled, and the reset process can be executed based on the electromagnetic wave irradiation detection result of the circuit 1 of the present invention. it can.

  Here, it is assumed that either the contact operation or the non-contact operation is in the reset state. In this case, as described above, the operation reset circuit 6 outputs the high level operation reset instruction signal RSD to the invalidation instruction signal generation circuit 5. The invalidation instruction signal generation circuit 5 to which the high-level operation reset instruction signal RSD has been input is reset, stores the information L as temporary storage information, and is invalidated at a low level with respect to the invalidation circuit 4a. The instruction signal ERRDIS is output and the state becomes invalid. During this period, since either the negative signal of the external reset signal RST given to the reset signal generation circuit 9 or the power-on reset circuit 80 is a high level voltage signal, the detection output from the invalidation circuit 4 Regardless of the level of the modification signal ERR1, a high-level reset signal RST1 is given to the calculation and data storage unit 40, and the inventive device 2b indicates a reset state.

  Next, when the reset state of the operation that has been in the reset state (contact operation or non-contact operation) is released, the operation reset circuit 6 sends the low-level operation reset instruction signal RSD to the invalidation instruction signal generation circuit 5. Output. At this time, the invalidation instruction signal generation circuit 5 still stores the information L as the temporary storage information, so the invalidation instruction signal ERRDIS is output to the invalidation circuit 4a and the invalidation state is output. Is continuing.

  When the reset is released, the CPU 41 executes the program stored in the ROM 42 and stores the inversion value of the read voltage value of the invalidation instruction flash memory transistor NT in the invalidation instruction signal generation circuit 5. At this time, since the read voltage of the invalidation instruction flash memory transistor NT is at the low level as described above, the invalidation instruction signal generation circuit 5 stores the information H as temporary storage information, the invalidation state is released, and again Based on the electromagnetic wave irradiation detection result of the circuit 1 of the present invention, it is possible to shift to a state where the reset process can be executed.

  The invalidation instruction flash memory transistor NT is desirably arranged in the vicinity of a data storage area, specifically, data to be physically protected. Even if the invalidation instruction flash memory transistor NT is irradiated with ultraviolet rays in order to form an invalidation state intentionally, the flash memory transistor group related to the data storage area that exists in the vicinity Electromagnetic waves are also applied to the (memory cell group). As a result, the flash memory transistor group is in an erased state, and target data to be protected is also erased, so that high security can be realized.

  Further, in the present embodiment described above, the invalidation sub instruction signal is a voltage signal corresponding to the inverted value of the read voltage (current) value of the predetermined invalidation instruction flash memory transistor NT in the flash macro 20. Can be a voltage signal corresponding to the read voltage value.

  In this case, after the manufacturing of the device 2b of the present invention is completed, before the assembly into the package or the like, the invalidation instruction flash memory transistor NT is set in the write state and the read voltage is set to a low level. As a result, the invalidation sub instruction signal becomes a low level voltage, and therefore the invalidation instruction signal generation circuit 5 stores information L as temporary storage information. Thereby, since the circuit 1 of the present invention is in an invalidated state, the threshold voltage can be adjusted.

  Then, after the threshold voltage is adjusted, an erasing operation is performed on the invalidation instruction flash memory transistor NT. As a result, the read voltage of the flash memory transistor NT becomes a high level, and thus a high level invalidation sub instruction signal is given to the invalidation instruction signal generation circuit 5. As a result, the invalidation instruction signal generation circuit 5 stores the information H as temporary storage information, the invalidation state is canceled, and the reset process can be executed based on the electromagnetic wave irradiation detection result of the circuit 1 of the present invention. it can.

  When either the non-contact operation or the contact operation is in a reset state, the invalidation instruction signal generation circuit 5 performs a reset process and stores information L as temporary storage information. When the reset state is released, the CPU 41 executes the program stored in the ROM 42 and stores the read voltage value of the invalidation instruction flash memory transistor NT in the invalidation instruction signal generation circuit 5. As described above, since the read voltage of the flash memory transistor NT is at a high level, a high-level invalidation sub-instruction signal is given to the invalidation instruction signal generation circuit 5, and the invalidation instruction signal generation circuit 5 temporarily stores it. Information H is stored as information, and the invalidation state is released. Thereby, it can transfer to the state which can perform reset processing again based on the electromagnetic wave irradiation detection result of this invention circuit 1. FIG.

  In this case, the invalidation instruction flash memory transistor NT does not change even when the electromagnetic wave is irradiated (in the erased state). Therefore, the invalidation instruction flash memory transistor NT is not necessarily stored in the data storage area. It is not necessary to arrange in the vicinity.

  In the second and third embodiments related to the device of the present invention described above, the device 2a or 2b of the present invention includes the invalidation instruction flash memory transistor NT. However, other nonvolatile memory transistors such as an EEPROM may be used. It may be configured.

The block diagram which shows schematic structure of 1st Embodiment of the electromagnetic wave irradiation detection circuit which concerns on this invention The circuit block diagram which shows another example of the comparison circuit with which the electromagnetic wave irradiation detection circuit which concerns on this invention is equipped The block diagram which shows schematic structure of 2nd Embodiment of the electromagnetic wave irradiation detection circuit which concerns on this invention The block diagram which shows schematic structure of 4th Embodiment of the electromagnetic wave irradiation detection circuit which concerns on this invention. The block diagram which shows schematic structure of 1st Embodiment of the semiconductor device which concerns on this invention. The block diagram which shows schematic structure of 2nd Embodiment of the semiconductor device which concerns on this invention. The block diagram which shows schematic structure of 3rd Embodiment of the semiconductor device which concerns on this invention. A block diagram showing a schematic configuration of a conventional IC card A circuit block diagram showing a schematic configuration of a conventional electromagnetic wave irradiation detection circuit Conceptual structure diagram of flash memory transistor Schematic configuration diagram of a memory cell array configured by arranging flash memory transistors in a matrix.

Explanation of symbols

1, 1a, 1b, 1c, 1d: electromagnetic wave irradiation detection circuit 2, 2a: semiconductor device according to the present invention 4: invalidation circuit 9: reset signal generation circuit 10: non-contact interface 11: rectifier circuit 12: Modulation circuit 13: Demodulation circuit 14: Clock separation circuit 15: Antenna 16: Regulator 17: Regulator 18: Protocol control circuit 20: Flash macro 20a: Memory cell array 30: Bias generation circuit 31a, 31b: MOS transistor 33: Negation circuit 34: OR circuit 40: operation and data storage unit 41: CPU
42: ROM
43: RAM
51: Control gate 52: Floating gate 53: Source 54: Drain 60: Contact interface 61: UART
70: Conventional electromagnetic wave irradiation detection circuit 71: Flash memory transistor 71a: First flash memory transistor 71b: Second flash memory transistor 72, 72a, 72b, 72c: Comparator 72im: Inverted input terminal 72ip: Non-inverted input terminal 72o: Output Terminal 73: Negative circuit 74, 74a: Comparison circuit 80: Power-on reset circuit 90: Conventional IC card BL1, BL2,..., BLn: Bit line NT: Invalidation instruction flash memory transistor R1: (first) resistor R2 : Second resistor SC1: first series circuit SC2: second series circuit SL: source line V _CC : power supply voltage V _OUT : target voltage V _OUT1 : first target voltage V _OUT2 : second target voltage WL1, WL2,. WLm: Word line

Claims (16)

A first series circuit in which a first resistor and a first nonvolatile memory transistor are arranged in series;
A second series circuit in which a second resistor and a second nonvolatile memory transistor are arranged in series;
The intermediate point of the first resistor of the first series circuit and the first nonvolatile memory transistor is connected to one input terminal of the pair of differential input terminals, and the second input terminal of the second series circuit is connected to the other input terminal. A midpoint between the second resistor and the second nonvolatile memory transistor is connected, and a comparison circuit that outputs a binary detection signal corresponding to a voltage difference input to the two input terminals, and
The potential at the intermediate point between the first resistor and the first nonvolatile memory transistor and the potential at the intermediate point between the second resistor and the second nonvolatile memory transistor in the second series circuit are both determined according to the power supply voltage. Configuration
When energy of a predetermined amount or more is given by irradiation with electromagnetic waves, the on-resistances of the first and second nonvolatile memory transistors change, and the electromagnetic waves are irradiated in a non-irradiated state where no electromagnetic waves are irradiated. An electromagnetic wave irradiation detection circuit, wherein a difference in voltage input to the two input terminals changes between irradiation states, and the detection signal changes. The comparison circuit includes a comparator having an inverting input terminal, a non-inverting input terminal, and an output terminal;
The inverting input terminal is connected to the first resistor of the first series circuit and an intermediate point of the first nonvolatile memory transistor;
The non-inverting input terminal is connected to the second resistor of the second series circuit and an intermediate point of the second nonvolatile memory transistor;
The output terminal is configured to output a binary voltage signal determined according to a magnitude relationship between two voltages input to the inverting input terminal and the non-inverting input terminal,
A voltage level of the detection signal is determined based on a voltage level of the voltage signal output from the output terminal;
When energy of a predetermined amount or more is given by irradiation with electromagnetic waves, the on-resistances of the first and second nonvolatile memory transistors change, and the electromagnetic waves are irradiated in a non-irradiated state where no electromagnetic waves are irradiated. 2. The detection signal output from the output terminal is changed by changing a magnitude relationship between voltages input to the inverting input terminal and the non-inverting input terminal between irradiation states. The electromagnetic wave irradiation detection circuit according to 1. A resistance value of the first resistor is smaller than a resistance value of the second resistor;
3. The electromagnetic wave irradiation detection circuit according to claim 2, wherein a threshold voltage of the first nonvolatile memory transistor is smaller than a threshold voltage of the second nonvolatile memory transistor in the non-irradiation state. An electromagnetic wave shielding means is provided in a predetermined area,
The amount of energy given to the first nonvolatile memory cell is greater than the amount of energy given to the second nonvolatile memory cell by reflecting a part of the electromagnetic wave irradiated by the electromagnetic wave shielding means. 4. The electromagnetic wave irradiation detection circuit according to claim 2, wherein the electromagnetic wave irradiation detection circuit is configured to be reduced.   5. The electromagnetic wave shielding means is provided in an upper layer of the formation region of the first nonvolatile memory cell, and is not provided in an upper layer of the formation region of the second nonvolatile memory cell. The electromagnetic wave irradiation detection circuit of description.   6. The electromagnetic wave irradiation detection circuit according to claim 4, wherein the electromagnetic wave shielding means is formed of a metal wiring layer. The first series circuit and the second series circuit are connected in parallel, a first reference voltage is applied to one of the terminals, and a second reference voltage is applied to the other terminal,
The first reference voltage is a power supply voltage or a voltage determined according to the power supply voltage;
7. The structure according to claim 1, wherein the first reference voltage is applied to both control gates of the first nonvolatile memory transistor and the second nonvolatile memory transistor. 2. An electromagnetic wave irradiation detection circuit according to item 1. The first series circuit and the second series circuit are connected in parallel, a first reference voltage is applied to one of the terminals, and a second reference voltage is applied to the other terminal,
The first reference voltage is a power supply voltage or a voltage determined according to the power supply voltage;
A voltage generation circuit for performing read, write, or erase processing on the first or second nonvolatile memory transistor with respect to both control gates of the first nonvolatile memory transistor and the second nonvolatile memory transistor. The electromagnetic wave irradiation detection circuit according to claim 7, wherein an output voltage is applied.   The electromagnetic wave according to any one of claims 1 to 8, further comprising a bias generation circuit for applying a bias voltage between the source and drain terminals of the first and second nonvolatile memory transistors. Irradiation detection circuit.   The electromagnetic wave irradiation detection circuit according to claim 1, wherein the first and second nonvolatile memory transistors are configured by flash memory transistors. The first and second nonvolatile memory transistors form a connection with a metal wiring layer at a gate terminal and a drain terminal;
An area of a metal wiring layer connected to a gate terminal and a drain terminal of the first nonvolatile memory transistor; an area of a metal wiring layer connected to a gate terminal and a drain terminal of the second nonvolatile memory transistor; The electromagnetic wave irradiation detection circuit according to claim 1, wherein the electromagnetic wave irradiation detection circuits are different from each other. The electromagnetic wave irradiation detection circuit according to any one of claims 1 to 11,
A reset signal generation circuit that generates a reset signal based on an active / inactive state of the detection signal output from the comparison circuit;
A semiconductor device, wherein a reset operation is performed based on the reset signal output from the reset signal generation circuit. The electromagnetic wave irradiation detection circuit according to any one of claims 1 to 11,
A reset signal generation circuit that generates a reset signal based on an activation / inactivation state of the detection signal output from the comparison circuit;
An invalidation circuit capable of invalidating the detection result of the electromagnetic wave irradiation detection circuit, and a configuration in which a reset operation is performed based on the reset signal output from the reset signal generation circuit,
The invalidation circuit comprises:
An invalidation instruction signal indicating an instruction as to whether or not to execute the invalidation processing of the detection result of the electromagnetic wave irradiation detection circuit and the detection signal are input,
When the invalidation instruction signal indicating that the invalidation processing is not performed is input, the detection signal is input to the reset signal generation circuit,
When the invalidation instruction signal for executing the invalidation processing is input, a voltage signal indicating an inactive state is input to the reset signal generation circuit regardless of activation / inactivation of the detection signal. A semiconductor device comprising:   The semiconductor device according to claim 13, wherein the invalidation circuit is configured to accept input of the invalidation instruction signal from an external device using a test pad. An operation reset circuit that outputs a high-level operation reset instruction signal when a certain operating condition is satisfied;
An invalidation instruction signal generation circuit that generates the invalidation instruction signal having a binary voltage level and outputs the invalidation instruction signal to the invalidation circuit;
The reset signal generation circuit includes:
The output signal of the invalidation circuit and the operation reset instruction signal are input, and the reset signal is generated based on whether any one of the signals is active,
The invalidation instruction signal generation circuit,
A high / low binary invalidation sub-instruction signal corresponding to the storage state of a predetermined invalidation instruction nonvolatile memory transistor and the operation reset instruction signal are input, and 2 corresponding to the level of the input voltage level. A configuration capable of storing temporary storage information of values,
The semiconductor device according to claim 13, wherein the invalidation instruction signal having a voltage level associated with information different from the stored temporary storage information is output.   The semiconductor device according to any one of claims 12 to 16 and the non-contact type external device communicate with each other in a non-contact manner so that information is exchanged and electromagnetically coupled from the non-contact type external device. Either a contactless communication interface to which power is supplied or a contact communication interface to which information is exchanged by contact with a contact type external device and power is supplied from the contact type external device or An IC card characterized by comprising both.

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