KR100301931B1 - A semiconductor memory device with redundant selection circuit - Google Patents

Abstract

The semiconductor memory device according to the present invention includes a main memory cell array, a redundant memory cell array, a row decoder, a column decoder, a Y-gate circuit, a main sense amplifier and a write driving circuit, a redundant sense amplifier and a write driving circuit, a redundant selection circuit, a multiplexer. And data input / output buffers. The redundant selection circuit includes a memory cell array, a write control circuit, a first decoder, a Y-gate circuit, a sense amplifier and a write drive circuit, and a second decoder. The redundant selection circuit selects a plurality of bits of redundant selection for input / output data input / output to / from redundant memory cells in a redundant memory cell array according to a column address applied from the outside during a test operation, a write operation, and a read operation. Output signals. As described above, during the test operation, the redundant select circuit selects input / output data input / output to / from redundant memory cells, thereby providing the main memory cells as well as the redundant memory cells without the addition of a separate test circuit. The defects are tested to increase the reliability of the semiconductor memory device and the yield of the semiconductor manufacturing process.

Description

A SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANT SELECTION CIRCUIT}

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundant memory.

In recent years, semiconductor memory devices are increasingly integrated and large in capacity, and chip sizes are gradually increased in proportion to the high functionality of such semiconductor memory devices. In general, as the chip size increases and the minimum line width decreases for high integration of the semiconductor memory device, the yield of the chip decreases vice versa.

According to this tendency, in high-density memory devices where the yield of chips is important, the yield of chips has been improved by a technique using an error correction code and various defect repair techniques using a redundant memory as shown in FIG. 1. The error correction code, which is one of such defect remedy techniques, is a technique using a hamming code used in digital communication, which is read from a memory cell through a combination of parity data and data read from the memory cell. It is a technology that replaces data in which an error occurs among data with accurate data. Such an error correction code has an advantage of correcting not only a defect of a memory cell but also an error in a process of reading data.

However, the failure remedy technique using the error correction code not only increases the area of the chip, but also when the error occurs in the data of a plurality of bits of the read data, there is a disadvantage that it is impossible to correct the error-produced data.

Referring to FIG. 1, a semiconductor memory device using a defect repair technique using redundant memory cells includes a main memory cell array 11, a redundant memory cell array 13, a row decoder 21, a column decoder 23, and a Y. Gate circuit 25, main sense amplifier and write driver circuit 31, redundant sense amplifier and write driver circuit 33, address storage circuit 41, input / output coding circuit 43, multiplexer 50 and Data input / output buffer 60 is provided.

Although not shown, the main memory cell array 11 includes a plurality of main memory cells, a plurality of main word lines MWLs, and a plurality of main bit lines. MBLs, and stores a plurality of bits of data in the main memory cells. Although not shown, the redundant memory cell array 13 includes the main word lines MWLs, a plurality of redundant memory cells, and a plurality of redundant bit lines RBLs. The defective memory cells in the main memory cell array 11 are repaired to store data to be stored in the defective memory cells.

The row decoder 21 decodes a plurality of row addresses RA from the outside. The column decoder 23 decodes a plurality of column addresses CA from the outside. The Y-gate circuit 25 outputs data DOUT <0:15>, RDOUT <from memory cells of the main and redundant memory cell arrays 11 and 13 selected by the decoded row addresses RA. 16>) outputs the output data DOUT <0:15> / RDOUT <16> corresponding to the column address CA among the output data DOUT <0:15> and RDOUT <16>. Optionally Y-gating.

The main sense amplifier and word line driver circuit 31 transfers write data WD <0:15>, RWD <16> to the corresponding main bit line MBL during a write operation, and during the read operation, The output data DOUT <0:15> and RDOUT <16> transmitted through the Y-gate circuit 25 are sensed. The address storage circuit 41 stores column addresses CA representing the addresses of the defective main memory cells, and input column addresses CA represent the addresses of the defective main memory cells. In response, repair enable signals RE <0: 7> indicating a selection of a redundant memory cell are output.

The input / output coding circuit 43 may include a plurality of redundant selection signals that code repair activation signals RE <0: 7> from the address storage circuit 41. ; R <0:15>). The multiplexer 50 receives input data from the data input / output buffer 60 during the write operation under the control of the redundant select signals R <0:15>, DIN <0:15>. Is transmitted to the sense amplifier and write driving circuits 31 and 33 and during the read operation, sensing data (SD <0:15>, RSD from the sense amplifier and write driving circuits 31 and 33). <16> is optionally delivered to the data input / output buffer 60. The data input / output buffer 60 stores input data DIN <0:15> input from the outside during a write operation, and senses data SD <0: from the multiplexer 50 during a read operation. 15>, RSD <16>).

A technique for repairing bad memory cells using a general redundant memory cell, such as FIG. 1, is mainly used in dynamic random access memory (DRAM), static random access memory (SRAM), programmable read only memory (PROM), and the like. For example, a failure remedy technique in a semiconductor memory device having a word unit (16 bits) as one page is a case where one bit of data in a word unit for a specific address of the main memory cell array 11 is defective. In this case, the data is replaced with data stored in the redundant memory cells in the redundant memory cell array 13. In contrast, data to be written to the main memory cells in the defective main memory cell array 11 is written to the redundant memory cells in the redundant memory cell array 13.

In the address storage circuit 41 of the semiconductor memory device in which the general failure repair technique illustrated in FIG. 1 is used, a row of main memory cells failed according to a test result of the main memory cell array 11 after the semiconductor manufacturing process is completed. The address CA is stored in the address storage circuit 41 through a fuse cutting method. By the way, such a fuse cutting method is a laser fuse cutting method for cutting a fuse in a semiconductor memo device at a wafer stage before packaging and an electric fuse cutting method for cutting a fuse after packaging. ) Method.

Among the fuse cutting methods, the laser fuse cutting method not only results in an increase in test time, but also a large increase in cost in a semiconductor manufacturing process. The electric fuse cutting method includes a method of cutting a fuse by supplying an overcurrent to a packaged semiconductor memory device, and a method of cutting a fuse using a flash memory cell as a fuse. Here, the fuse cutting method using the flash memory cell is a method in which the fuse is determined according to whether the flash memory cell is programmed and erased using the flash memory cell as a fuse. In addition to fail defects, there is an advantage in that redundant memory cells can be tested for defects.

However, the redundant technology using the flash memory cell also requires a separate test circuit for reading data of the redundant memory cell as well as a circuit used for fusing the main memory cell to detect whether the redundant memory cell is defective. Thus, a problem arises in that the area of the semiconductor memory device is increased.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of testing whether a redundant memory cell array is defective without adding a test circuit.

1 is a block diagram showing a general semiconductor memory device;

2 is a block diagram showing a semiconductor memory device according to a preferred embodiment of the present invention;

3 is a block diagram illustrating a memory cell array and a peripheral circuit of the semiconductor memory device of FIG. 2;

4 is a block diagram illustrating a redundant selection circuit of FIG. 2.

* Explanation of symbols on the main parts of the drawings

110: main memory cell array 130: redundant memory cell array

210: row decoder 230: column decoder

250: Y-gate circuit 310, 330: sense amplifier and write drive circuit

400: redundant selection circuit 500: multiplexer

600: data input / output buffer

(Configuration)

According to one aspect of the present invention for achieving the above object, the semiconductor memory device according to the present invention includes a first and second arrays, a bit line selection circuit, a sense amplifier circuit, a redundant selection circuit and a multiplexer. . The first array includes a plurality of first bit lines and a plurality of main memory cells connected to the first bit lines. The second array includes a plurality of second bit lines and a plurality of redundant memory cells connected to the second bit lines. The bit line selection circuit selects at least one second bit line of at least one of the first bit lines and second bit lines in response to a column address. The sense amplifier circuit senses data from the first and second arrays through the selected bit line in response to a sense signal. The redundant selection circuitry accepts the column address and generates a redundant selection signal informing whether the selected first bit line is a defective column. The multiplexer outputs sensed data through the selected second bit line in response to the redundant select signal. The redundant selection circuit stores column address information for designating each of the second bit lines to determine whether each of the second bit lines is a defective column during a test operation mode, and the redundant selection circuit During the normal mode operation, column address information indicating a fault column among the first bit lines is stored.

The redundant selection circuit also includes a first decoder, a memory cell array, a bit line selection circuit, a sense amplifier circuit, and a second decoder. The first decoder outputs first and second addresses from which the column address is decoded. The memory cell array has a plurality of memory cells and stores the column address information. The bit line selection circuit selectively outputs data corresponding to the column address information from the memory cell array in response to the second address. The sense amplifier circuit senses the data from the memory cell array through the bit line select circuit in response to the sense signal. The second decoder outputs the redundant select signals decoded the data from the sense amplifier circuit.

The first and second arrays include NOR type flash memory cells, and the memory cell array of the redundant selection circuit includes NOR type flash memory cells. Here, the redundant selection circuit may include a write driving circuit for driving the column address information to the memory cell array during the test operation mode, and a write control circuit for transferring the column redundant data to the write driving circuit in response to the test signal. It includes more.

According to another feature of the invention, the semiconductor memory device according to the invention comprises first and second arrays, bit line selection circuits, sense amplifier circuits, redundant selection circuits and multiplexers. The first array includes a plurality of first bit lines and a plurality of main memory cells connected to the first bit lines. The second array includes a plurality of second bit lines and a plurality of redundant memory cells connected to the second bit lines. The bit line selection circuit selects at least one second bit line of at least one of the first bit lines and second bit lines in response to a column address. The sense amplifier circuit senses data from the first and second arrays through the selected bit line in response to a sense signal. The redundant selection circuitry accepts the column address and generates a redundant selection signal informing whether the selected first bit line is a defective column. The multiplexer outputs sensed data through the selected second bit line in response to the redundant select signal. The redundant selection circuit includes a first decoder, a memory cell array, a bit line selection circuit, a sense amplifier circuit, a first decoder and a write driver circuit. The first decoder outputs first and second addresses from which the column address is decoded. The memory cell array has a plurality of memory cells and stores the column address information. The bit line selection circuit selectively outputs data corresponding to the column address information from the memory cell array in response to the second address. The sense amplifier circuit senses the data from the memory cell array through the bit line select circuit in response to the sense signal. The second decoder outputs the redundant select signals decoded the data from the sense amplifier circuit. The write driver circuit drives the column address information to the memory cell array during the test operation mode.

According to another feature of the invention, the semiconductor memory device according to the invention comprises first and second arrays, bit line selection circuits, sense amplifier circuits, redundant selection circuits and multiplexers. The first array includes a plurality of first bit lines and a plurality of main memory cells connected to the first bit lines. The second array includes a plurality of second bit lines and a plurality of redundant memory cells connected to the second bit lines. The bit line selection circuit selects first and second bit lines corresponding to the column address among the first and second bit lines in response to a column address. The sense amplifier circuit senses data from the first and second arrays through the selected bit lines. The redundant select circuitry accepts the column address and generates a redundant select signal indicating whether one bit line of the selected first bit lines is a defective column. The multiplexer outputs sensed data through a second bit line instead of a defective bit line among the selected first bit lines in response to the redundant select signal. Here, the redundant selection circuit stores column address information for designating each of the second bit lines to determine whether each of the second bit lines is defective open during a test operation mode, and during normal mode operation. And storing column address information indicating a defective column among the first bit lines.

According to another feature of the invention, the semiconductor memory device according to the invention comprises first and second arrays, bit line selection circuits, sense amplifier circuits, redundant selection circuits and multiplexers. The first array includes a plurality of first bit lines and a plurality of main memory cells connected to the first bit lines. The second array includes a plurality of second bit lines and a plurality of redundant memory cells connected to the second bit lines. The bit line selection circuit selects first and second bit lines corresponding to the column address among the first and second bit lines in response to a column address. The sense amplifier circuit senses data from the first and second arrays through the selected bit lines. The redundant select circuitry accepts the column address and generates a redundant select signal indicating whether at least two of the selected first bit lines are faulty columns. The multiplexer causes the sensed data to be output through the selected second bit lines instead of the defective bit lines of the selected first bit lines in response to the redundant select signal. The redundant selection circuit stores column address information for designating each of the second bit lines to determine whether each of the second bit lines is defective open during a test operation mode, and during a normal mode operation, And stores column address information indicating a defective column among the first bit lines.

(Action)

With such a device, during the test operation, not only the main memory cells but also the redundant memory cells are tested for defects, thereby improving the reliability of the semiconductor memory device and the yield of the semiconductor manufacturing process.

(Example)

Hereinafter, reference will be described in detail with reference to FIGS. 2 to 4 according to a preferred embodiment of the present invention.

Referring to FIG. 2, the semiconductor memory device according to the present invention may include a main memory cell array 110, a redundant memory cell array 130, a row decoder 210, a column decoder 230, a Y-gate circuit 250, A main sense amplifier and write driver circuit 310, redundant sense amplifier and write driver circuit 330, redundant select circuit 400, multiplexer 500, and data input / output buffer 600. The redundant selection circuit 400 includes a memory cell array 410, a write control circuit 420, a first decoder 430, a Y-gate circuit 440, a sense amplifier and write driver circuit 450, and a second. And a decoder 460, wherein defects of the memory cells in the main memory cell array 110 and the redundant memory cell array 130 are tested during a test operation, and during a write operation and a read operation, Paths of output data DOUT <0:15>, RDOUT <16> from the redundant memory cell array 130 and input data DIN <0:15> from the data input / output buffer 600 Outputs a plurality of redundant select signals R <0:15> for controlling. As described above, during the test operation, the redundant selection circuit 400 input / output data (DIN <0:15> / DOUT <0:15>, RDOUT <16>) input / output to / from redundant memory cells. ), Without the addition of a separate test circuit, the defects of the main memory cells as well as the redundant memory cells are tested, thereby increasing the reliability of the semiconductor memory device and the yield of the semiconductor manufacturing process.

2 and 3, a semiconductor memory device according to the present invention may include a main memory cell array 110, a redundant memory cell array 130, a row decoder 210, a column decoder 230, and Y-gate circuits. 250, a main sense amplifier and write driver circuit 310, a redundant sense amplifier and write driver circuit 330, a redundant select circuit 400, a multiplexer 500, and a data input / output buffer 600. The main memory cell array 110 includes a plurality of main memory cells and a plurality of main word lines MWLs and MWLs extending in a row direction along the main memory cells. And a plurality of main bit lines (MBLs) extending along the main memory cells in a column direction to intersect.

The redundant memory cell array 130 may include a plurality of redundant bit lines extending in a column direction along the memory cells to intersect a plurality of redundant memory cells and the main word lines MWLs and the main word lines MWLs. And redundant bit lines (RBLs). The memory cells of the main and redundant memory cell arrays 110 and 130 may be divided into bit segments in a bit line unit as shown in FIG. 3. The row decoder 210 decodes a plurality of row addresses RA from the outside. The column decoder 230 decodes a plurality of column addresses CA from the outside.

As illustrated in FIG. 3, the Y-gate circuit 250 includes a Y-gate circuit 251 connected to corresponding main bit lines MBLs and a Y-gate circuit 253 connected to corresponding redundant bit lines RBLs. Bit lines corresponding to the column address CA for write data WD <0:15> and RWD <16> from the sense amplifier and the write driving circuits 310 and 330 during the write operation. Bit lines MBLs and RBLs from the main memory cell array 110 and the redundant memory cell array 130 under the control of the column addresses CA during selective transfer to (MBLs, RBLs) and during a read operation. The output data DOUT <0:15> and RDOUT <16>, which are transmitted through the signal, are selectively transferred to the sense amplifier and the write driving circuits 310 and 330.

The sense amplifier and write driver circuits 310 and 330 include a plurality of sense amplifiers and write drivers SA and WD connected to the corresponding Y-gate circuits 251/253, as shown in FIG. During operation, the input data DIN <0:15> is provided to the main memory cell array 110 and the redundant memory cell array 130 as read data WD <0:15>, RWD <16> and read. During operation, sensing the output data DOUT <0:15> and RDOUT <16> from the main memory cell array 110 and the redundant memory cell array 130 in response to a sensing signal SEN. The data SD <0:15> and RSD <16> are output to the multiplexer 500. The sensing signal SEN is output after a predetermined delay time after an address is input from an address transition detector ATD for detecting a transition of addresses input from the outside.

Although not shown, the multiplexer 500 transfers sensing data SD <0:15> and RSD <16> from the sense amplifier and the write driving circuits 310 and 330 to the data input / output buffer 600. A first multiplexer to transfer and a second multiplexer to pass input data DIN <0:15> from the data input / output buffer 600 to the sense amplifier and write drive circuits 310 and 330. .

Referring to FIG. 4, the redundant selection circuit 400 includes a memory cell array 410, a write control circuit 420, a decoder 430, a Y-gate circuit 440, a sense amplifier, and a write driving circuit 450. And a redundant decoder 460, wherein the redundant select signal R <0:15 selects the output data RDOUT <16> from the redundant memory cell array 130 during a test operation, a write operation, and a read operation. Output>) The memory cell array 410 includes a plurality of floating gate type memory cells, a plurality of word lines WLs, and bit lines BLs.

The write control circuit 420 receives a word line voltage VWL and redundant data RD <0: 4> from the outside during a write operation during a test operation, and applies the test signal TEST to a plurality of bits. In response, the word line voltage VWL is supplied to the decoder 430 and the redundant data RD <0: 4> are supplied to the sense amplifier and the write driving circuit 450. The decoder 430 is provided with the column address. Outputs a decoding row address DRA and a decoding column address DCA decoded CA. The Y-gate circuit 440 is controlled from the memory cell array 410 under the control of the decoding column address DCA. Optionally, output the column redundant output data (CR_DOUT <0: 4>) or the column redundant write data (CR_WD <0: 4>) to be stored in the memory cell array 410. Gating, where the open redundancy The most significant bit data (CR_DOUT <4>) of the output data (CR_DOUT <0: 4>) represents the selection of redundant data, and the remaining lower bit data (CR_DOUT <0: 4>) represents the redundant data (RWD / RSD <16>). ) Indicates the path to be input / output.

The sense amplifier and write driver circuit 450 provides the column redundant write data CR_WD <0: 4> to the memory cell array 410 through the Y-gate circuit 440 during a write operation during a test operation. During the test operation and the read operation, column redundant sensing data (CR_SD <0: 4>) that senses open redundant output data CR_DOUT <0: 4> under control of the sensing signal SEN. Outputs The redundant decoder 460 outputs the redundant selection signal R <0:15> that decodes the column redundant sensing data CR_SD <0: 4> from the sense amplifier and the write driving circuit 450. Here, the redundant select signal R <0:15> indicates an input / output path of the redundant data RWD / RSD <16>.

The multiplexer 500 senses and writes input data DIN <0:15> from the data input / output buffer 600 in response to the redundant select signals R <0:15> during a write operation. Selectively transfers the sensing data SD <0:15>, RSD <16> from the sense amplifier and write driving circuits 310, 330 during transfer operation selectively to the driving circuits 310, 330 and during a read operation. Optionally pass to input / output buffer 600. The data input / output buffer 600 may read / write data from the memory cell arrays 110 and 130 or may be stored in the memory cells of the memory cell arrays 110 and 130 during a write and read operation. / SD <0:15>).

Hereinafter, an operation of a semiconductor memory device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2 to 4.

2 to 3, a semiconductor memory device according to the present invention may include the redundant selection circuit 400. The redundant select circuit 400 outputs a plurality of bits of redundant select signals R <0:15> for selecting the redundant memory cell array 130 during test, write, and read operations. As described above, during the test operation, by selecting the input / output path of the redundant data DIN / SD <0:15> input / output using the multiple bit redundant selection signals R <0:15>. The defects of the redundant memory cells are tested without addition of a separate test circuit and data stored in the redundant memory cells are written and read during the write and read operations, thereby improving the reliability of the semiconductor memory device and the yield of the manufacturing process.

2 to 4, the operations of the NOR flash memory device including the NOR type flash memory cells according to the present invention are largely divided into a test operation, a write operation, and a read operation. In the test operation, defects of main memory cells and redundant memory cells in the semiconductor memory device are tested.

<Test behavior>

During the test operation, first, whether the main memory cells in the main memory cell array 110 of FIG. 2 are defective is tested. The test of the main memory cells is performed in order to write a predetermined type of data (for example, data of all '1' or '0') into the main memory cells, and then read data stored in the main memory cells. . In this case, when data of different from the data stored in the normal memory cells (for example, data of '1' is output from the normal memory cell) is output from the defective main memory cells, data of '0' is output from the defective memory cell. Is output.) Is output.

After the test of the main memory cells in the main memory cell array 110 ends, when the test of the redundant memory cells in the redundant memory cell array 130 starts, the memory cell array of the redundant select circuit 400 ( In 410, column redundant information indicating the selection of the redundant bit line RBL is written. At this time, the write control circuit 420 of the redundant select circuit 400 of FIG. 3 receives the redundant data RD <0: 4> from the outside in response to the test signal TEST. 450, and a word line voltage (VWL) to the decoder 430. In this case, the redundant data RD <0: 4> may be input to any one of address pins or input / output pins. The decoder 430 outputs the decoding row and column addresses DRA and DCA which decode the column addresses CA from the outside.

In this case, the word line WL of the memory cell array 410 selected by the decoding row address DRA is activated at a program voltage (Vpgm; for example, about 19V to 20V). In addition, the write driver circuit of the sense amplifier and the write driver circuit 450 transmits the column redundant write data CR_WD <0: 4> corresponding to the redundant data RD <0: 4> to the Y-gate circuit 440. Through the corresponding bit line BL of the memory cell array 410. In this case, the Y-gate circuit 440 transfers the column redundant write data CR_WD <0: 4> to the bit line BL corresponding to the decoding column address DCCA in response to the decoding column address DCA. do.

In this way, memory cells connected to the word line WL and the bit lines BLs selected by the decoding row and column addresses DRA and DCA correspond to the addresses of all the redundant bit lines RBLs. Open redundant data is stored. When information corresponding to addresses of all redundant bit lines RBLs of the redundant memory cell array 130 is stored in the memory cell array 410, a test of the redundant memory cells in the redundant memory cell array 130 is performed. .

In order to test the redundant memory cells, first, data of a certain type is written in the redundant memory cells as in the main memory cells. In this case, the column address CA is provided to the decoder 430 of the redundant selection circuit 400. The decoder 430 outputs the decoding row and column addresses DRA and DCA which decode the column address CA. The column redundant data CR_DOUT <0: 4> of the memory cells connected to the word line WL and the bit lines BLs selected by the decoding row and column addresses DRA and DCA are stored in the Y-gate circuit ( The signal is transferred to the sense amplifier and the write driving circuit 450 through 440.

The sense amplifiers SA of the sense amplifiers and the write driving circuit 450 may perform the column redundant sensing data CR_SD <which senses the column redundant output data CR_DOUT <0: 4> transmitted through the Y-gate circuit 440. 0: 4>) to the redundant decoder 460. The redundant decoder 460 outputs a redundant selection signal R <0:15> decoded from the column redundant sensing data CR_SD <0: 4>.

In this case, row and column addresses RA and CA are also input to the row and column decoders 210 and 230 of FIG. 2. The data input / output buffer 600 stores input data (for example, DIN <0> is data to be stored in redundant memory cells) for testing of redundant memory cells. The multiplexer 500 senses the input data DIN <0> stored in the data input / output buffer 600 under the control of the redundant selection signals R <0:15>. To pass).

The write driver circuit WD of the sense amplifier and the write driver circuit 330 supplies the write data WD <0> corresponding to the input data DIN <0> to the Y-gate circuit 253. At this time, the Y-gate circuit 253 transfers the write data WD <0> to all the redundant bit lines RBLs in response to the column addresses CA decoded by the column decoder 230. Deliver sequentially. At this time, for example, if the Y-gate circuit 251/253 is divided into YA gates and YB gates, the column address CA supplied to the Y-gate circuit 253 is Y-gate. The lower bit address (for example, 2 bits) and the YB address (for example, 1 bit) of the YA address supplied to the circuit 251. Thus, when one main bit line MBL in the main memory cell array 110 is selected, one redundant bit line RBL in the redundant memory cell array 130 is selected.

As such, the write data RWD <0> transferred through the redundant bit lines RBLs are sequentially stored in redundant memory cells connected to the selected main word line MWL. When the write data RWD <0> is stored in all redundant memory cells in the redundant memory cell array 130, a read operation of data stored in the redundant memory cells is performed. When the read operation is started, the row decoder 210 decodes the row address RA to read the main word lines MWLs corresponding to the row address RA, for example, a read voltage Vread; About 5V to 6V) level. The column decoder 230 decodes the column address CA to turn on Y-gates corresponding to the column address CA of the Y-gate circuit 250.

Thereafter, the data RDOUT <16> stored in redundant memory cells connected to the main word line MWL corresponding to the row address RA may be stored in the redundant bit lines RBLs and Y− corresponding to the column address CA. It is output to the sense amplifier SA of the sense amplifier and the write driving circuit 330 through the gate circuit 250. The sense amplifier SA multiplexes the sensing data RSD <16> from the output data RDOUT <16> transmitted through the Y-gate circuit 250 in response to the sensing signal SEN. )

In this case, the column address CA and the sensing signal SEN are supplied to the sense amplifier and the write driving circuit 450 of the redundant selection circuit 400 simultaneously with the sense amplifier and the write driving circuit 330. The redundant selection signal R <0:15>, which decodes the column redundant data CR_SD <0: 4> corresponding to the redundant information stored in the memory cell array 410, is output from the redundant selection circuit 400. . The multiplexer 500 may receive the sensed data RSD <16> from the redundant sense amplifier and the write driver circuit 330 in response to the redundant select signal R <0:15>. To the outside through).

In this case, the defect test of the redundant memory cells is performed in the same manner as the defect test of the main memory cells, and all the redundant memory cells are sequentially tested. When the test operation of the redundant memory cells in the redundant memory cell array 130 ends, repairing the output defective memory cells of the main memory cell array 100 to the normal redundant memory cells of the redundant memory cell array 130 may be performed. Is performed. In this step, repair information of the redundant memory cell array 130 to be repaired is stored in the memory cell array 410 in the redundant selection circuit 400.

<Write operation>

When the repair of the defective main memory cell by the test operation ends, a write operation for storing data in the main memory cell array 110 and the redundant memory cell array 130 of the semiconductor memory device according to the present invention starts. In particular, the write operation of the semiconductor memory device according to the present invention is divided into a program operation and an erase operation.

The erase operation refers to an operation of erasing data stored in memory cells in the main and redundant memory cell arrays 110 and 130. An erase command is externally inputted into a command register (not shown). It starts by entering. When the erase command is input, the command register supplies an erase command to control logic (not shown) and the control logic generates an erase control signal informing the erase operation. In this case, row and column addresses RA and CA are input to the row and column address decoders 210 and 230. An erase voltage generate circuit (not shown) generates an erase voltage Vera (for example, about −10 V to about −20 V) by controlling the erase control signal.

The erase voltage Vera is applied to the bulk of the memory cells in the main and redundant memory cell arrays 110 and 130, so that the erase voltage Vera is applied to the main and redundant memory cell arrays 110 and 130 of the semiconductor memory device. Memory cells are erased in chip, block, or sector units through FN tunneling.

The program operation is an operation of writing data into memory cells of the main and redundant memory cell arrays 110 and 130. During the program operation, predetermined data is stored in the normal memory cells in the main memory cell array 110. In this case, data to be stored in the defective memory cells in the main memory cell array 110 is stored in the normal redundant memory cells in which no defect occurs among the memory cells of the redundant memory cell array 130.

A logic low level chip enable bar (CEB), a write enable bar (WEB) and a logic high level (output enable bar); When OEB) is input to the command register, the program operation of the semiconductor memory device according to the present invention is started.

When the program operation is started, a program command is input into the command register and a program address is input into the row and column decoders 210 and 230. The command register supplies a program command to the control logic, and the control logic generates a program control signal informing the program operation. The program voltage generate circuit (not shown) generates a program voltage Vpgm (for example, about 19V to 20V) by the control of the program control signal.

The program voltage Vpgm is supplied to the row decoder 210 so that the main word line MWL selected by the row decoder 210 is activated to the program voltage Vpgm level. The data input / output buffer 600 receives program data, that is, input data DIN <0:15>, and delivers the program data to the multiplexer 500.

In this case, the decoder 420 of the redundant selection circuit 400 outputs the decoded row and column addresses DRA and DCA decoded from the column address CA. If the column address CA has the address of one defective memory cell in the main memory cell array 110, a redundant bit line to which a redundant memory cell replacing a defective memory cell is connected from the memory cell array 410. The column redundant output data CR_DOUT <0: 4> indicating the address of the RBL is output. The sense amplifier and the write driving circuit 450 output the column redundant sensing data CR_SD <0: 4> in which the output data CR_DOUT <0: 4> is sensed in response to the sensing signal SEN. The redundant decoder 460 decodes the column redundant sensing data CR_SD <0: 4> and outputs the redundant selection signals R <0:15> indicating the selection of the redundant bit line RBL. .

The multiplexer 500 writes input data DIN <0:15> from the data input / output buffer 600 by the control of the redundant select signals R <0:15> and the sense amplifier. Supply to the driving circuits (310, 330). At this time, each of the write driving circuits in the sense amplifier and the write driving circuits 310 and 330 has the write data corresponding to the input data DIN <0:15>, for example, a WD <0> defective main memory. Assuming that data is to be written to a cell, WD <1:15>, WD <16>; where WD <16> is WD <0>. Are supplied to the Y-gate circuits 210, 230. .

The Y-gate circuit 251 transfers the write data WD <1:15> from the sense amplifier and the write driving circuit 310 to the main bit lines MBLs of the main memory cell array 110. The Y-gate circuit 253 transfers the write data WD <0> from the sense amplifier and the write driving circuit 330 to the redundant bit line MBL of the redundant memory cell array 130. As such, the write data WD <1:15> and WD <16> transferred through the main and redundant bit lines MBLs and RBL are selected main words in the main and redundant memory cell arrays 110 and 130. The memory cells connected to the line MWL are programmed through hot electron injection. Since the halon injection and F-N tunneling operation of the flash memory cell are obvious to those skilled in the art, a detailed description is omitted.

<Read operation>

The read operation is an operation of reading data stored in the main and redundant memory cell arrays 110 and 130. The read operation may include a logic low level chip enable bar (CEB), a logic high level write enable bar (WEB), and an output enable signal (IC). When the output enable bar (OEB) is input to the command register and the row and column addresses RA and CA are input to the row and column decoders 210 and 230, a read operation of the semiconductor memory device according to the present invention starts. do.

When the read operation is started, the row decoder 210 decodes the row addresses RA to activate one main word line MWL corresponding to the row addresses RA to the read voltage Vread level. . The column decoder 230 decodes the column addresses CA to turn on Y-gates corresponding to the column addresses CA among the Y-gates of the Y-gate circuits 251 and 253. . Output data DOUT <0:15> and RDOUT <16> from memory cells connected to the main word line MWL are connected to the sense amplifier and write driving circuits 310 and 330 through turned-on Y-gates. It is sensed by sense amplifiers SAs.

Each sense amplifier SA of the sense amplifier and the write driving circuits 310 and 330 senses the output data DOUT <0:15> and RDOUT <16> in response to the sensing signal SEN. The data SD <0:15> and RSD <16> are output to the multiplexer 500. In this case, the column address CA and the sensing signal SEN are supplied to the decoder 420 of the redundant selection circuit 400.

In this case, the decoder 420 of the redundant selection circuit 400 outputs the decoded row and column addresses DRA and DCA decoded from the column address CA. If the column address CA has the address of one defective memory cell in the main memory cell array 110, a redundant bit line to which a redundant memory cell replacing a defective memory cell is connected from the memory cell array 410. The column redundant output data CR_DOUT <0: 4> indicating the address of the RBL is output. The sense amplifier and the write driving circuit 450 output the column redundant sensing data CR_SD <0: 4> in which the output data CR_DOUT <0: 4> is sensed in response to the sensing signal SEN. The redundant decoder 460 decodes the column redundant sensing data CR_SD <0: 4> and outputs the redundant selection signals R <0:15> indicating the selection of the redundant bit line RBL. .

The multiplexer 500 is configured to sense data (eg, SD <0>) from the sense amplifier and the write driving circuits 310 and 330 by controlling the redundant select signals R <0:15>. Is an output data from the defective main memory cell, SD <1:15> and RSD <16> are supplied to the data input / output buffer 600.

Of course, as described above, even if two or more bits of the 16-bit data output from the main memory cell array 110 are output from the defective memory cells or the defective main bit lines, the data is the data from the redundant memory cells. Can be replaced. To this end, the number of bits of the 5-bit column redundant writing and sensing data CR_WD <0: 4> and CR_SD <0: 4> in the redundant selection circuit 400 must be increased.

For example, two bits of data (the least significant bit data DOUT <0>, the most significant bit data DOUT <15>) of the output data DOUT <0:15> from the main memory cell array 110 are transferred from the defective memory cell. Assuming output data, 8-bit column redundant data CR_WD <0: 7> and CR_SD <0: 7> should be output from the memory cell array 410. This indicates that the top-level data WD <7> and SD <7> of the open redundant data CR_WD <0: 7> and CR_SD <0: 7> indicate whether a repair is present and the data WD <4: 6>. , SD <4: 6> distinguishes the upper and lower bits, and data WD <0: 3> and SD <0: 3> have the address of the repaired redundant bit line.

As described above, the semiconductor memory device according to the present invention, during the test operation, the redundant memory of the redundant memory cell array 130 as well as the main memory cells of the main memory cell array 110 using the redundant selection circuit 400. Test the cells for defects. In addition, during the read operation, the sense amplifiers SAs of the sense amplifiers and the write driving circuits 310 and 330 and the sense amplifiers SAs of the redundancy selection circuit 400 and the sense amplifiers SAs of the write driving circuit 450 are connected. Since it is controlled by the same sensing signal SEN from the address transition detector ADT, no time delay occurs during the read operation.

In addition, when the memory cells in the main and redundant memory cell arrays 110 and 130 are NOR type flash memory cells, the memory cell array 410 in the redundant select circuit 400 may be implemented as NOR type flash memory cells. It is preferable to be. This is because the main and redundant memory cell arrays 110 and 130 and the memory cell array 410 in the redundant selection circuit 400 may be implemented in the same process without additional process.

As described above, the semiconductor memory device according to the present invention is tested not only for the main memory cells but also for the defects of the redundant memory cells, so that the reliability of the semiconductor memory device and the yield of the semiconductor manufacturing process are improved.

In the above, the semiconductor memory device according to the present invention has been shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications may be made without departing from the spirit of the present invention.

As described above, during the test operation, the defect memory cells are tested for defects, thereby improving the reliability of the semiconductor memory device and the yield of the semiconductor manufacturing process.

Claims (9)

A first array having a plurality of first bit lines and a plurality of main memory cells connected to the first bit lines; A second array having a plurality of second bit lines and a plurality of redundant memory cells coupled to the second bit lines; A bit line selection circuit for selecting at least one of the first bit line and at least one of the second bit lines of the first bit lines in response to a column address; Sense amplifier circuitry for sensing data from the first and second arrays through the selected bit line in response to a sensing signal; A redundant select circuit for accepting the column address and generating a redundant select signal informing whether the selected first bit line is a defective column; A multiplexer for outputting sensed data through the selected second bit line in response to the redundant select signal; The redundant selection circuit stores column address information for designating each of the second bit lines to determine whether each of the second bit lines is a defective column during a test mode of operation, and And the redundant selection circuit stores column address information indicating a fault column among the first bit lines during a normal mode operation. The method of claim 1, The redundant selection circuit, A first decoder for outputting first and second addresses decoded the column address; A memory cell array having a plurality of memory cells and storing the column address information; A bit line selection circuit for selectively outputting data corresponding to the column address information from the memory cell array in response to the second address; A sense amplifier circuit for sensing the data from the memory cell array through the bit line selection circuit in response to the sensing signal; And a second decoder outputting the redundant select signals decoded the data from the sense amplifier circuit. The method of claim 1, And the first and second arrays comprise NOR type flash memory cells. The method of claim 2, The memory cell array includes NOR type flash memory cells. The method of claim 2, And the redundant selection circuit further comprises a write driver circuit for driving the column address information to the memory cell array during the test mode of operation. The method of claim 5, The redundant selection circuit further includes a write control circuit for transferring the column redundant data to the write driving circuit in response to the test signal. A first array having a plurality of first bit lines and a plurality of main memory cells connected to the first bit lines; A second array having a plurality of second bit lines and a plurality of redundant memory cells coupled to the second bit lines; A bit line selection circuit for selecting at least one of the first bit line and at least one of the second bit lines of the first bit lines in response to a column address; Sense amplifier circuitry for sensing data from the first and second arrays through the selected bit line in response to a sensing signal; A redundant select circuit for accepting the column address and generating a redundant select signal informing whether the selected first bit line is a defective column; A multiplexer for outputting sensed data through the selected second bit line in response to the redundant select signal; The redundant selection circuit, A first decoder for outputting first and second addresses decoded the column address; A memory cell array having a plurality of memory cells and storing the column address information; A bit line selection circuit for selectively outputting data corresponding to the column address information from the memory cell array in response to the second address; A sense amplifier circuit for sensing the data from the memory cell array through the bit line selection circuit in response to the sensing signal; A second decoder for outputting the redundant select signals decoded the data from the sense amplifier circuit; And a write driver circuit for driving the column address information to the memory cell array during the test operation mode. A first array having a plurality of first bit lines and a plurality of main memory cells connected to the first bit lines; A second array having a plurality of second bit lines and a plurality of redundant memory cells coupled to the second bit lines; A bit line selection circuit for selecting first and second bit lines corresponding to the column address among the first and second bit lines in response to a column address; Sense amplifier circuitry for sensing data from the first and second arrays through the selected bit lines; A redundant select circuit for accepting the column address and generating a redundant select signal informing whether one of the selected first bit lines is a defective column; A multiplexer for outputting sensed data through a second bit line in place of a defective bit line among the selected first bit lines in response to the redundant select signal; The redundant selection circuit stores column address information for designating each of the second bit lines to determine whether each of the second bit lines is defective open during a test mode of operation, and And the redundant selection circuit stores column address information indicating a fault column among the first bit lines during a normal mode operation. A first array having a plurality of first bit lines and a plurality of main memory cells connected to the first bit lines; A second array having a plurality of second bit lines and a plurality of redundant memory cells coupled to the second bit lines; A bit line selection circuit for selecting first and second bit lines corresponding to the column address among the first and second bit lines in response to a column address; Sense amplifier circuitry for sensing data from the first and second arrays through the selected bit lines; A redundant select circuit for accepting said column address and generating a redundant select signal informing whether at least two bit lines of said selected first bit lines are defective columns; A multiplexer for outputting sensed data through selected second bit lines instead of defective bit lines of the selected first bit lines in response to the redundant select signal; The redundant selection circuit stores column address information for designating each of the second bit lines to determine whether each of the second bit lines is defective open during a test mode of operation, and And the redundant selection circuit stores column address information indicating a fault column among the first bit lines during a normal mode operation.