JPH0982899A - Semiconductor memory device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a redundancy relieving effect by setting a priority where a means of momorizing information for inhibiting redundancy cells replacement is higher than one of memorizing information for permitting redundancy cells replacement. SOLUTION: A memory part of a semiconductor memory device provides a memory cell array 1 having memory cells 4 arranging word lines 5 and a means which relieves word lines 5 by being replaced by redundancy cells in case of word lines being connected with defective bits. A priority where a means of memorizing information for inhibiting redundancy cells 2 replacement is higher than one of memorizing information for permitting redundancy cells 2 replacement is set This can improve a redundancy relieving effect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a redundancy circuit which can be relieved when a redundancy cell of a replaced address has a defect or a fuse is not properly blown, and a manufacturing method thereof. It is a thing.

[0002]

2. Description of the Related Art As semiconductor elements incorporated in a semiconductor substrate (chip) of a semiconductor device are miniaturized and the number of elements included in one chip becomes huge, the level of countermeasures against defect density is improved. In the development stage and the initial stage of mass production, low yield is a problem. In order to solve this problem, a redundancy circuit (hereinafter referred to as redundancy (re
A technique called "dundancy" or a redundancy circuit) has been proposed and put into practical use. Here, for example, a redundant circuit for relieving a defect created during a manufacturing process in a memory element will be described. When there are defective rows or columns in the memory cell array, some spare row lines or column lines are prepared, and when the address signal corresponding to the defective portion is input, the spare By configuring the circuit so that the row line or the column line is selected, it can be treated as a good product even if it includes a defect. This redundant circuit slightly increases the chip area but greatly improves the yield. In order to realize such a redundant circuit, it is very important to select one kind of programming means for allocating an address corresponding to a defective portion randomly generated in each chip to a spare portion.

Circuit configurations of a semiconductor memory device including a conventional redundancy circuit are shown in FIGS. 2, 7 and 8. Figure 7
Is a circuit configuration diagram of the entire semiconductor memory device, and FIG.
2 is a circuit configuration diagram showing the redundancy circuit unit of FIG. 2, and FIG. 2 is a circuit configuration diagram of the memory unit of FIG. FIG. 2 is also a circuit configuration diagram of the memory section of the semiconductor memory device of the present invention. The semiconductor memory device shown in these figures is an example of repairing a word line (row line) having a defective bit, and stores a defective address for an address signal (A0 to An) that determines a defective row address. The circuit 10 for detecting a match between the input address bit and the storage address bit is provided by the replacement row address number (m). Then, a signal (AE1 to AE) that is satisfied when the address matches the defective address.
m) to spare row lines (SWL1 to SWL)
WLm) 3 is provided, and the low lines (WL1 to WL
m ') 5 is accessed and the main row decoder 8 is established, the spare enable signal / (SE) ("/" is
The bar marked above SE is shown and the enable inversion signal is shown. The same applies hereinafter. ) Has been configured to be prohibited.

The memory portion of the semiconductor memory device is provided with a memory cell array 1 consisting of a plurality of memory cells (MC11 to MCkm ') 4 and a redundancy cell (SC11 to SCkm) 2 (FIG. 2). The gate of the redundancy cell 2 is connected to the m spare row lines 3 and one spare row line 3 is connected to k redundancy cells 2. On the other hand, the gates of the memory cells 4 of the memory cell array 1 have row lines (WL1 to WLm ') 5
, And k memory cells 4 are connected to one row line 5. One of the source / drain electrodes of the memory cell 4 and the redundancy cell 2 is connected to the GND line 6, and the other is connected to the k bit lines 7. The bit line 7 is connected to the column selector and the sense amplifier 9, and the data signals (D0 to Dn) from each sense amplifier are transmitted to the data bus.

The output of the circuit 10 that stores a defective address in response to an address signal that determines a defective row address and detects the match between each input address bit and the stored address bit is input to an AND circuit 11 and its output ( AE1
To AEm) are input to the spare row line 3 via each level shifter circuit 12. The outputs (AE1 to AEm) of the AND circuit 11 are input to the NOR circuit 13,
The output / (SE) is input to the row line 5 via the row decoder 8. The address signal (A0 to An) from the address bus is also supplied to the row decoder 8 together with its inverted signal.
Is input to the row line 5 via.

FIG. 9 shows a circuit configuration diagram of a circuit 10 for storing the conventional defective address shown in FIG. 7 and detecting a match between each input address and a storage address bit. First,
When using the redundancy circuit, it is necessary to enable the address detection circuit used. One of the bits (FE1 to FEm) for that purpose is connected to GND,
The other is a fuse element F connected to the power supply via a resistor R
It is composed of When the fuse element F is blown by a current or a laser, the connection point fg between the resistor R and the fuse element becomes "H" level, which is input to the buffer 25 and the spare enable signal (SE) of its output is "1". become. The defective address information is similarly stored in the ON / OFF state of the fuse element. For example, if the address signals A0 = 0, A1 = 1, ... Are defective addresses, F
When the fuse element of 01 bit is cut, SA0 = 1 when A0 = 0 is input, and when the fuse element of F11 bit is kept on, SA1 = 1 when A1 = 1 is input. As described above, the exclusive OR circuit (e
xOR) 24, and when a defective address is input, all of the outputs SA0 to SAn are set to 1.

A test flow of such a conventional redundancy circuit is shown in FIG. First, it is checked whether or not all bits are in the initial state (erase) (1), and if they are in the initial state (OK), writing check is performed (2). If you do not provide redundancy relief,
Here, an OK one is once removed from the tester for a reliability test, and a high temperature storage test is performed (3). Then, all bits are read again by the tester to check whether the written data has been erased, and the wafer test ends (4). When performing repair by redundancy, it is judged whether or not a non-initial state (NG) can be repaired with a specified row replacement number (5), and then a specified row replacement is performed for an NG one in writing. It is determined whether the repair is possible by the number (6), and for the repairable ones, the fuse element of the redundancy circuit is cut based on the replacement address information (7). Then, the cut fuse element is returned to the tester, and the erased and written check is performed on the replaced row (8).
After that, a read check of all bits is performed (9), and a high temperature storage test is performed by removing the bit from the tester (3). afterwards,
All bits are read again by the tester and checked (4).

[0008]

As described above, it is first checked whether the bit is erased, and if it is OK, the writing is checked. If redundancy is not used for repair, OK is removed from the tester once for reliability testing and a high temperature storage test is performed to check whether all the written data has been erased. Perform and check to complete the wafer test. In the case of repairing by redundancy, it is judged whether or not it is possible to repair an NG one by writing with a prescribed row replacement number, and if it is repairable, then the redundancy fuse is cut based on the replacement address information. To do. Next, a write / erase check is performed on the row in which the fuse cut one has been replaced, and a read check for all bits is performed.

Here, if the redundancy cell to be replaced has a defect or if the fuse is not blown properly and the address is set to the wrong address, the rescue becomes impossible. The present invention has been made in view of the above circumstances, and a redundancy cell of a defective address is replaced with a defective redundancy cell of a replaced address after the fuse is blown. The present invention provides a semiconductor memory device in which the redundancy repair efficiency is improved by not blowing the fuse bit group of another set and replacing it with another redundancy cell by fusing the fuse bit group, and a manufacturing method thereof.

[0010]

SUMMARY OF THE INVENTION A semiconductor memory device of the present invention comprises a memory cell array composed of a plurality of memory cells arranged in a plurality of word lines and a word line to which defective bits of the word lines are connected. The redundancy cell is replaced by a means for replacing the defective cell with a redundancy cell, and means for repairing the redundancy bit, and a nonvolatile storage means for storing address relief information, redundancy cell replacement permission information, and redundancy cell replacement prohibition information. A first feature is that the means for storing the prohibited information is set to have a higher priority than the means for storing the information allowing the replacement of the redundancy cell. A second feature of the semiconductor memory device according to claim 1 is that the non-volatile storage means includes a fuse element. A third feature of the semiconductor memory device according to claim 1 is that the non-volatile storage means comprises a non-volatile memory.

A method of manufacturing a semiconductor memory device according to the present invention is
First to check if all bits are initialized
And the second step of checking the writing if all the bits are initialized, and if the redundancy circuit does not perform the repair based on the second step, the writing is OK. A third step of performing a high temperature storage test, a fourth step of reading all bits with a tester to check whether written data has been erased after the third step, and the above-mentioned step based on the first step. When performing repair by the redundancy circuit, a fifth step of determining whether or not all bits have not been initialized can be repaired by a prescribed row line replacement number,
A sixth step of judging whether or not a part of all the bits cannot be written based on the second step, by the redundancy circuit, can be repaired by a prescribed row line replacement number, and the sixth step. A seventh step of cutting the fuse element of the redundancy circuit based on the replacement address and the replacement permission information based on the step;
For those that can be repaired by the redundancy circuit based on the above step, an eighth step of performing initialization (erasing) and writing check of the redundancy cell;
If the redundancy cell of the replaced address is defective after the fuse is blown, or if the fuse is not blown properly, the fuse bit is blown and the defective redundancy cell is not accessed. In this way, the method further comprises a ninth step of blowing out the fuse bit group of another set, and a tenth step of performing a read check of all the bits in the state where the row lines are replaced based on the relief address. The tenth
It is characterized in that the data is checked through the third and fourth steps as in the case where the redundancy circuit does not perform the repair after the step.

A fuse bit for storing a defective replacement address and a fuse bit for storing information for permitting replacement are provided together with a fuse bit for storing information for inhibiting replacement, and a fuse bit for storing information for inhibiting replacement is permitted. By setting the priority higher than the fuse bit that stores information, the fuse bit that prohibits replacement is blown if there is a defect in the redundancy cell of the replaced address after the fuse has blown or if the fuse is not blown correctly. The defective redundancy cell is prevented from being accessed, and the fuse bit group of another set is blown to be replaced with another redundancy cell.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. A circuit configuration of a semiconductor memory device including the redundancy circuit of the present invention is shown in FIGS.
FIG. 1 is a circuit configuration diagram of the entire semiconductor memory device, and FIG.
1 and FIG. 3 are circuit configuration diagrams showing the redundancy circuit unit of the semiconductor memory device of FIG. 1, and FIG. 4 is a redundancy circuit diagram of the redundancy circuit unit of FIG. . FIG. 2 is a circuit configuration diagram of a memory section of a conventional semiconductor memory device, and the memory section has the same configuration as the conventional one. The semiconductor memory device shown in these figures is an example of repairing a word line (row line) having a defective bit, and stores a defective address for an address signal (A0 to An) that determines a defective row address. The circuit 20 for detecting the match between the input address bit and the stored address bit is replaced with the row address number (m
Only). Spare row lines (SWL1 to SWLm) 3 are provided for the signals (AE1 to AEm) that are satisfied when they match the defective address, and the row lines (WL1 to WLm ') 5 are accessed and the main row is connected. It is configured such that the establishment of the decoder 8 can be prohibited by a spare enable signal / (SE) (“/” represents a bar above SE and represents an enable inversion signal. The same applies hereinafter). .

The memory section of the semiconductor memory device is provided with a memory cell array 1 consisting of a plurality of memory cells (MC11 to MCkm ') 4 and a redundancy cell (SC11 to SCkm) 2 (FIG. 2). The gate of the redundancy cell 2 is connected to the m spare row lines 3 and one spare row line 3 is connected to k redundancy cells 2. On the other hand, the gates of the memory cells 4 of the memory cell array 1 have row lines (WL1 to WLm ') 5
, And k memory cells 4 are connected to one row line 5. One of the source / drain electrodes of the memory cell 4 and the redundancy cell 2 is connected to the GND line 6, and the other is connected to the k bit lines 7. The bit line 7 is connected to the column selector and the sense amplifier 9, and the data signals (D0 to Dn) from each sense amplifier are transmitted to the data bus.

The output of the circuit 20 for storing the defective address in response to the address signal for determining the defective row address and detecting the match between each input address bit and the stored address bit is input to the AND circuit 11 and its output ( AE1
To AEm) are input to the spare row line 3 via each level shifter circuit 12. The outputs (AE1 to AEm) of the AND circuit 11 are also input to the NOR circuit 13, and the output / (SE) is input to the row line 5 via the row decoder 8. The address signals (A0 to An) from the address bus are also input to the row line 5 via the row decoder 8 together with its inverted signal. That is, the signals AE1 to AEm that are satisfied when they match the defective address.
To spare row lines (SWL1 to SWL
m) 3 is provided, the row line 5 is accessed, and establishment of the main row decoder is prohibited by the SE1 to SEm signals.

FIG. 4 is a detailed circuit configuration diagram of the circuit 20 for storing the defective address shown in FIG. 1 and detecting the match between each input address and the stored address bit. First,
When using the redundancy circuit, it is necessary to enable the address detection circuit used. One of the bits (FE1 to FEm) for that purpose is connected to GND,
The other is a fuse element F connected to the power supply via a resistor R
It is composed of The fuse element F is composed of an aluminum film, a polysilicon film, or the like. When the fuse element F is blown by a current or a laser, the connection point fg1 between the resistor R and the fuse element becomes "H" level, which is input to the buffer 25 and the spare enable signal (SE) of its output is "1". become. The defective address information is similarly stored in the ON / OFF state of the fuse element. For example, address signals A0 = 0, A1 = 1,
... is a defective address and the fuse element of the F01 bit is cut, SA0 is input when A0 = 0 is input.
= 1 and the F11 bit fuse element is left on, the exclusive OR of the input and the address input from each fuse element is set so that SA1 = 1 when A1 = 1 is input. When the defective address is input to the circuit (exOR) 24, SA0 of its output is input.
Make 1 for all SAn.

A circuit 20 for storing the defective address and detecting a match between each input address and the stored address bit.
Are provided with bits (FD1 to FDm) for disabling the address detection circuit, and output (SD
V1 to SDVm) are input to the AND circuit 11, respectively. One of these bits (FD1 to FDm) is GND
The fuse F connected to is connected to the power source through the resistor R, and when the fuse is blown by the current or the laser, the connection point fg2 between the resistor R and the fuse F becomes “H” level and is input to the inverter 26, and The output SDV becomes "0". When the fuse F of this bit is blown, "0" is input to the input SDV of the AND circuit 11 of the address detection circuit, and the detection of a match with the address bit of the set can be prohibited.

Next, the test flow of the redundancy circuit of the semiconductor memory device of the present invention will be described with reference to FIG. First, it is checked whether all the bits are in the initial state (erase) (1), and if they are in the initial state (O
K) Check writing (2). If the redundancy is not used for repair, the OK one is temporarily removed from the tester for the reliability test and a high temperature storage test is performed (3). Then, all bits are read again by the tester to check whether the written data has been erased, and the wafer test ends (4). When performing repair by redundancy, it is determined whether or not it is possible to repair a non-initial state (NG) with a specified row replacement number (5), and then a specified row replacement is performed for an NG one in writing. It is judged whether or not the repair is possible by the number (6), and for the repairable one, the fuse element of the redundancy circuit is cut (blown) based on the replacement address information (7). Then, an erase / write check is performed on the replaced row with respect to the cut fuse element (8).

Then, if the redundancy cell of the address replaced after the fuse is blown is defective or if the fuse is not blown correctly, the fuse bits (FD1 to FDm) that prohibit the replacement are blown to cause a defective redundancy cell. Is not accessed, and the fuse bit group of another set is melted and replaced with another redundancy cell (9). After that, a read check of all bits is performed (10), and a high temperature storage test is further performed (3). After that, all bits are read again by the tester and checked (4).

Next, a case where a nonvolatile memory is used in place of the fuse of the fuse element will be described with reference to FIG.
The figure is a circuit diagram showing a fuse element having a nonvolatile memory. Conventionally, the fuse of the fuse element is formed of aluminum, polysilicon, or the like.
A nonvolatile memory element such as M, EEPROM, or flash memory can be replaced with a fuse. This memory element is, for example, a two-layer gate transistor 27 having the same floating gate as a memory cell or a redundancy cell, and when writing to a cell corresponding to a fuse cut,
A high voltage (Vpp) is applied to the gate and drain of the cell, and a power supply voltage (Vcc) is applied when reading the cell.

[0021]

EFFECTS OF THE INVENTION If the redundancy cell of the address replaced after the fuse is blown is defective or if the fuse is not blown correctly, the fuse bit for prohibiting the replacement is blown to prevent access to the defective redundancy cell. Then, the fuse bit group of the other set is melted and replaced with another redundancy cell, so that the redundancy repair efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device of the present invention.

FIG. 2 is a circuit configuration diagram of a memory unit shown in FIGS. 1 and 7.

FIG. 3 is a circuit configuration diagram of a redundancy circuit unit in FIG.

FIG. 4 is a redundancy circuit diagram of the redundancy circuit unit shown in FIG.

FIG. 5 is a test flowchart of the redundancy circuit according to the present invention.

FIG. 6 is a circuit configuration diagram of a fuse element of the redundancy circuit of the present invention.

FIG. 7 is a circuit diagram of a conventional semiconductor memory device.

8 is a circuit configuration diagram of the redundancy circuit unit in FIG. 7.

9 is a redundancy circuit of the redundancy circuit unit of FIG.

FIG. 10 is a test flowchart of a conventional redundancy circuit.

[Explanation of symbols]

1 ... Memory cell array, 2 ... Redundancy cell, 3 ... Spare row line, 4 ... Memory cell, 5 ... Row line, 6 ... GND line,
7 ... bit line, 8 ... row decoder,
9: Column selector and sense amplifiers 10, 2
0 ... Circuit for detecting match between input address bit and memory address bit, 11 ... AND circuit,
12 ... Level shifter, 13 ... NOR circuit,
24 ... Exclusive OR circuit (exOR), 25 ...
Buffer, 26 ... Inverter, 27 ... Fuse element memory element.

Claims (4)

[Claims] 1. A memory cell array composed of a plurality of memory cells arranged in a plurality of word lines, and a means for replacing the defective bit of a word line to which a defective bit of the word line is connected with a redundancy cell to repair the defective bit. And non-volatile storage means for storing address relief information, redundancy cell replacement permission information, and redundancy cell replacement prohibition information, and means for storing information that prohibits replacement of the redundancy cell. A semiconductor memory device, characterized in that a priority is set higher than a means for storing information that permits replacement. 2. The semiconductor memory device according to claim 1, wherein the non-volatile storage means comprises a fuse element. 3. The semiconductor memory device according to claim 1, wherein the non-volatile storage means comprises a non-volatile memory. 4. A first step of checking whether all bits are initialized, a second step of checking for writing if all bits are initialized, and the second step. If the redundancy circuit is not used for relief, the third step is to perform a high-temperature storage test for the write-in OK and read all bits with a tester to see if the written data has been erased after the third step. And a fourth step of performing a check, and determining whether all bits are uninitialized can be repaired with a prescribed row line replacement number when repairing is performed by the redundancy circuit based on the first step. And a redundancy circuit for a bit in which some of all bits cannot be written based on the second step. A sixth step of determining whether it is possible to repair with a more specified number of row line replacements, and a seventh step of cutting the fuse element of the redundancy circuit based on the replacement address and the replacement permission information based on the sixth step. A process, an eighth process for performing initialization (erase) and a write check of the redundancy cell for a device that can be repaired by the redundancy circuit based on the seventh process, and a fuse based on the eighth process. If there is a defect in the redundancy cell at the replaced address after fusing, or if the fuse is not blown correctly, the fuse bit that prohibits replacement is blown to prevent access to the defective redundancy cell. The ninth step of fusing the fuse bit group of the set, and the roll address based on the repair address. And a tenth step of performing a read check of all bits in a state in which the data is replaced, and the data is passed through the third and fourth steps as in the case where the redundancy circuit does not perform repair after the tenth step. 4. The method for manufacturing a semiconductor memory device according to claim 1, wherein the check is performed.