KR100210528B1 - A semiconductor memory device a microcontroller and method of manufacturing the semiconductor memory device - Google Patents

Abstract

Provided are a semiconductor memory device having a nonvolatile memory means and a fuse element, and a method of manufacturing the same, and a one-chip microcontroller, which aims to increase the efficiency of a test that enables testing of a duplicate cell before melting the fuse element.

A first register 21 for storing data read from the storage means having a predetermined depth and pattern formed in the insulating film on the semiconductor substrate 20, a second register 22 for storing data from the outside, and a first register; And a selection circuit 25 for selectively outputting each output of the second register based on the predetermined mode signal, and in the first mode other than the test mode, bad bits are based on the relief information of the first register data address. In the second mode, which is a test mode, a test is performed by replacing a bad bit with a duplicate cell based on the relief information of the address of the data of the second register.

Description

Method of manufacturing semiconductor memory device, microcontroller and semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a redundant circuit, a single-chip microcontroller and a semiconductor memory device incorporating the semiconductor memory device.

As semiconductor devices embedded in semiconductor substrates (chips) of semiconductor devices are miniaturized and the number of devices contained in a single chip is increased, the level of countermeasure against defect density is improved, but low production is at the development stage or in the early stage of mass production. Rate is a problem. In order to solve this problem, a redundant circuit (hereinafter, referred to as a redundancy or a redundant circuit) has been proposed and put into practical use. Here, for example, a redundant circuit for repairing a defect created during a manufacturing process in a memory element will be described. If there are defective rows or columns in the array of memory cells, prepare several rows or columns of spares, and select a spare row or column when an address signal corresponding to the defective portion is input. I can treat it as a good article while including a defect by constituting it. This redundant circuit slightly increases the chip area, but greatly increases the production rate. In realizing such a redundant circuit, it is very important to select one type of programming means for allocating an address corresponding to a defect location occurring randomly on each chip to the spare unit.

2, 11, and 12 are circuit diagrams of a conventional semiconductor memory device including a redundant circuit. The semiconductor memory device shown in the figure is an example for relieving a word line (row line) having a bad bit. The semiconductor memory device stores a bad address for address signals A0 to An for determining a bad row address. The circuit 10 for detecting coincidence of the memory address bits is provided as many as the number of replacement row addresses (m). Spare row lines SWL1 to SWLm 3 are provided for the signals AE1 to AEm that are satisfied when they match the bad address, and the row line 5 is accessed and the main row decoder 8 is provided. This configuration can be prevented by the spare enable signal / (SE) (where "/" indicates to be written on the SE and indicates the enable inversion signal. The same applies hereinafter).

The memory cell array 1 and the redundant cell 2 are provided in the memory section of the semiconductor memory device (FIG. 2). Gates of the redundant cells 2 are connected to the m spare row lines 3, and k redundant cells 2 are connected to one spare row line 3. On the other hand, the gates of the memory cells 4 of the memory cell array 1 are connected to the row lines WL1 to WLm 5, and k memory cells 4 are connected to one row line 5. One of the source / drain electrodes of the memory cell 4 and the redundant cell 2 is connected to the GND line 6, and the other is connected to k bit lines 7. The bit line 7 is connected to the column selector and the sensor amplifier 9, and the data signals D0 to Dn from each sensor amplifier are configured to be transmitted to the data bus.

The output of the circuit 10 which stores the bad address for the address signal for determining the bad row address and detects the coincidence of each of the input address bits and the memory address bits is input to the AND circuit 11, and the outputs AE1 to < RTI ID = 0.0 > AEm) is input to the spare row line 3 through each level shift circuit 12. In addition, the outputs AE1 to AEm of the AND circuit 11 are input to the NOR circuit 13, and the output / (SE) is input to the row line 5 through the row decoder 8. The address signals A0 to An from the address bus are also input to the row line 5 via the row decoder 8 at the same time as the inverted signal.

FIG. 13 shows a circuit configuration diagram of a circuit that stores a conventional bad address and detects a match between each input address and a storage address bit. First, it is necessary to enable the address detection circuit used in the case of using a redundant circuit. For this purpose, the fuse element F whose bits are FE1-FEm and one side is connected to GND is connected to the power supply via the resistor R. As shown in FIG. The connection point fg of the resistor R to which the fuse element F is melted by a current or a laser and the fuse element is at the H level, and this is input to the buffer, so that the spare enable signal SE is 1. Similarly, the bad address information is stored in the on / off state of the fuse element. For example, when the address signals A0 = 0, A1 = 1, ... are bad addresses, if the fuse element of bit F01 is cut off, SA0 = 1 when A0 = 0 is input, and the fuse element of bit F11 is removed. When it is turned on, the input from each fuse element and the address input are input to the exclusive logic circuit exOR such that SA1 = 1 when A1 = 1 is input. When a bad address is input, SA0 of the output is input. 1 is made to be satisfied in all -SAn.

The test flow of such a conventional redundant circuit is shown in FIG. First, it is checked whether all bits are in the initial state (erasing) (1), and if it is OK, writing is checked (2). In the case where the relief due to duplication has not been performed, the high temperature standing test is then performed by separating the tester from the tester once for the reliability test (3). Then, all the bits are read out by the tester to check whether or not the recorded data is erased, and the wafer test is completed (4). In the case of performing relief due to duplication, it is determined whether or not relief is possible with the prescribed number of row substitutions for the NG by erasing (5), and then it is determined whether or not relief is possible with the prescribed number of row substitutions for the NG in recording (6). ), The fuse element of the redundant circuit is cut based on the replacement address information (7).

Since this conventional test flow process cannot be carried out to the tester, it is necessary to separate it from the tester machine and perform it as a separate machine. Then, the cut of the fuse element is returned to the tester to perform erase and write checks on the replaced rows (8), and then read out all the bits (9), and further, separate from the tester and perform a high temperature leaving test ( 3). Then, all bit reads are performed again by the tester and checked (4).

As shown in Fig. 14, when the relief by overlapping is performed, the number of off-racks (separating from the tester) is twice, which is increased by one than when not removed. If the number of such off-racks is large, there is a problem that the number of times the needle of the tester is brought into contact with the wafer increases, and the risk of damaging the pad on the semiconductor substrate on which the semiconductor device such as LSI is formed increases.

In addition, since the test of the redundant spare cell (spare low line) is impossible only after the fuse element is cut off, there is a problem in that if the spare cell is inherently defective, it is impossible to remedy, but only the test time is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a semiconductor memory device having a nonvolatile memory means and a fuse element which aims at the efficiency of a test which enables a test of a duplicate cell before melting the fuse element, and the semiconductor memory device Provided is a 1-chip microcontroller provided therein.

The semiconductor memory device of the present invention comprises a memory cell array comprising a plurality of memory cells arranged on a plurality of word lines, means for replacing the defective bits of a word line to which bad bits are connected in the word line by replacing the defective bits with redundant cells; Nonvolatile storage means for storing address relief information and replacement permission information of a duplicate cell, a first register for reading data from the storage means, storing the data, and a second register for storing data from outside And a selection circuit for selectively outputting each of the outputs of the first register and the second register based on a predetermined mode signal, wherein in the first mode other than the test mode, the address of the data of the first register is rescued. A second mode that is a test mode by replacing the bad bit with the duplicated cell based on the information; Stand is characterized in that said second relief so that on the basis of the information of the data address of the register performing the test by substituting a redundant cell for a defective bit.

An address area for externally reading / writing data of a duplicate cell is provided, and an address area for reading out the first register and an address area for reading / writing out the second register are provided in another address area. It is characterized by having a 3rd mode provided respectively. It is also possible to use only a fuse element in which a nonvolatile storage means for storing the above-mentioned address relief information and replacement permission information of a duplicate cell is fused with a current or a laser.

Further, the one-chip microcontroller of the present invention includes the semiconductor memory device to read data from the nonvolatile storage means during a reset period, store data in the first register by a reset release signal, and store the data. Based on the information, the bits of the bad address are replaced and rescued.

In addition, in the first mode, a first step of checking whether all bits are in an initial state, a second step of checking for writing when all bits are in an initial state, and the second step are based on the second step. If the remedy is not performed by the redundant circuit, the third step of performing the high temperature leaving test after separating from the tester once for the reliability test to confirm that the recording is OK, and whether or not the recorded data is erased after the third step by all testers In the fourth step of reading and checking, and in the case of performing relief by the redundant circuit based on the first step, it is determined whether or not all bits are not initialized and can be remedied by the prescribed number of row (word line) substitutions. A fifth step of performing an operation and a partial bit cannot be written in all bits based on the second step. The sixth step of determining whether or not remedies are possible by the number of row (word line) substitutions specified in the solution, and the initialization (erasing) of the duplicated cells in the third mode for the remedy by the redundant circuit based on the sixth step. And a seventh step of checking the recording and writing the relief address and the substitution permission information to the second register, and in the state of being row-substituted based on the relief address stored in the second register in the second mode. An eighth step of performing a read check of all bits, and a ninth step of cutting a fuse element of the redundant circuit based on the substitution address and the substitution permission information based on the eighth step; The data is checked through the third and fourth steps as in the case where the relief by the circuit is not performed.

The data written in the duplicated cell replaced in the seventh step may be the same data as the data written in the row (word line) cell to be replaced in the second step. In the case where the nonvolatile memory means is a laser-fused fuse element type memory, the write / read test of the duplicated cell is possible during the first tester test before the fuse element is actually melted. Therefore, the write / read test only for the duplicated cell after the fuse element is melted. It is only necessary to test whether the defective memory cell is actually replaced by a duplicate cell in the second test after the high temperature leaving test, and the damage to the pad of the semiconductor device formed on the semiconductor substrate can be minimized. At the same time, testing can be made more efficient.

1 is a circuit diagram of a semiconductor memory device according to the first embodiment of the present invention.

FIG. 2 is a circuit diagram of a memory unit of FIGS. 1, 12, and 13;

3 is a circuit configuration diagram of the redundant circuit of FIG. 1 and FIG.

4 is a redundant circuit diagram of the present invention.

5 is a test flow chart of a redundant circuit of the present invention.

6 is a timing diagram of a redundant circuit of the present invention.

7 is a timing diagram of a redundant circuit of the present invention.

8 is a timing diagram of a redundant circuit of the present invention.

9 is a memory mapping diagram of the semiconductor memory device of the present invention.

10 is a test pattern diagram of a semiconductor memory device of the present invention.

11 is a circuit diagram of a conventional semiconductor memory device.

FIG. 12 is a circuit diagram of the redundant circuit of FIG. 10. FIG.

13 is a conventional redundant circuit diagram.

14 is a test flow chart of a conventional redundant circuit.

* Explanation of symbols for main parts of the drawings

1: memory cell array 2: redundant cell

3: spare row line 4: memory cell

5: low line 6: GND line

7: bit line 8: row decoder

9: column selector and sensor amplifier

10,20: circuit for detecting coincidence of input address bits with memory address bits

11 AND circuit 12 level shifter

13: NOR circuit 21: 1st register

22: 2nd register 23: 3 state buffer

24: Exclusive Logic Circuit (exOR) 25: Multiplexer Circuit

26: OR circuit

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of the semiconductor memory device of this invention is described with reference to drawings.

First, an embodiment of the first invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a circuit configuration diagram of a semiconductor memory device, FIG. 2 is a circuit configuration diagram of a memory unit in which a memory cell array and a redundant cell are formed, and FIG. 3 is a circuit configuration diagram of a redundant circuit section of the semiconductor memory device of FIG. This semiconductor memory device stores a bad address for the address signals A0 to An for determining the bad row address, and replaces the circuit 20 for detecting the coincidence of each input address bit with the memory address bit (m). Spare row lines SWL1 to SWLm are provided for the signals AE1 to AEm which are established when the address matches a bad address, and if any of the spare row lines is accessed, the main decoder is spared. The configuration is prohibited by the enable signal / (SE). Each circuit 20 has redundant enable bits F'E1 to F'Em for enabling the address detection circuit used in the case of using a redundant circuit, and bits for replacement address detection F'01 to F'nm. ).

The difference from the conventional circuit (circuit of FIG. 12) is that a data bus is connected to a circuit 20 which stores a bad address and detects coincidence of each input address bit and a storage address bit, and controls RDFUSE / The WRFUSE signal, the RESET signal for latching the FUSE data into the register, and the register selection signal (RSELECT) are input. In addition, the address signals A0 to An are input to each bit F'01 to F'nm of each circuit 20.

In the memory area, a memory cell array 1 and a redundant cell 2 are provided. Gates of the redundant cells 2 are connected to the m spare row lines 3, and k redundant cells 2 are connected to one spare row line 3. On the other hand, the gates of the memory cells 4 constituting the memory cell array 1 are connected to row lines WL1 to WLm'5, and one row line 5 has k memory cells 4 connected to each other. Connected. One of the source / drain electrodes of the memory cell 4 and the redundant cell 2 is connected to the GND line 6, and the other is connected to k bit lines 7. The bit line 7 is connected to the column selector and the sensor amplifier 9, and the data signals D0 to Dn from each sensor amplifier are configured to be transmitted to the data bus (FIGS. 1 and 2).

The output of the circuit 20 which stores a bad address with respect to the address signal for determining the bad row address, and detects the coincidence of each input address bit and the memory address bit is input to the AND circuit 11, and the output AE1. AEm is controlled by the signal TEST2 which becomes 1 at the time of the test mode 2 and is input to the multiplexer circuit 25 to the address signal for determining the spare row address, and through each level shifter 12. It is input to the spare row line 3. The outputs AE1 to AEm and the TEST2 signals of the AND circuit 11 are input to the NOR circuit 13, and the output / (SE) is input to the row line 5 through the row decoder 8. The address signals A0 to An from the address bus are also input to the row line 5 via the row decoder 8 together with the inverted signals (FIGS. 1 and 3).

FIG. 4 shows a specific circuit configuration diagram of the circuit 20. As shown in FIG. In each of the redundant enable bits F'E1 to F'Em, the P-channel load transistor Tr, to which the RESET inversion signal is input, is connected to the other end gate of the fuse element F having one end connected to GND, The connection point fE is the data input of the first register 21. The first register 21 is for storing data from the fuse element F, and the latch signal input is a RESET signal.

Further, a second register 22 for storing test replacement address data is provided externally, the data input DATA is supplied from the data bus, and the latch signal is a FUSE data write control signal (WRFUSE). Then, a circuit (selection circuit) 25 is provided which multiplexes the outputs of the first and second registers 21 and 22 by a register select signal. When the normal mode (RSELECT = 0) is provided, the first register 21 is provided. ), And outputs the data of the second register 22 in the TEST mode (RSELECT = 1). Further, a tri-state buffer 23 for discharging this output to the data bus is provided between the data output DATA and the output of the multiplex circuit 25 and controlled by the read signal RDFUSE of the FUSE data. The redundant enable bits F'E1 to F'Em take out the output of the previous multiplex circuit 25 as it is and use it as the spare enable signal SE.

The replacement address detection bits F'01 to F'n1 can be obtained by inputting the output of the multiplex circuit 25 and the address signals A0 to An to the exclusive logic circuit exOR 24. The output signals SA0 to SAn are used, and the other configuration is the same as the enable bit that is redundant. The first register (F01 to fnm) connecting the fuse element F and the P-channel load transistor Tr is connected to the first register. Enter the data in 21).

Next, the operation of the device incorporating the redundant nonvolatile memory circuit of the present invention in a single-chip microcomputer will be described. The microcomputer incorporating the nonvolatile memory of the present invention has four modes as shown in FIG. 9, that is, one chip mode, a writer mode, a test mode 1, and a test mode 2. Among them, the one-chip mode and the lighter mode are the normal use modes open to the user, and the test mode 1 and the test mode 2 are the dedicated test modes to the maker which are not open to the user. First, the spare row replacement operation after the reset cancellation of the redundant circuit in the one-chip mode (the mode in which the instruction is executed while reading the program data in the memory) is described. The microcomputer must first initialize the reset state and then cancel the reset to read program data from memory and execute instructions.

In this mode, the preceding Pch load transistor Tr is turned on by the RESET inversion signal in order to read the redundant fuse element data during the reset period. Since the on resistance of the Pch load transistor Tr is set higher than the resistance of the fuse element F, when the fuse element F is set in the connected state, the fuse element F and the Pch load transistor Tr are set. 0 is outputted to the connection node fE (fn) with 1, and 1 is output when the fuse element F is cut off. fE (fn) represents the signal levels of fE, f1 to fn, and there are two cases where the fuse element is disconnected and a case in which the fuse element is set in the connected state. In this mode, the output selection signal RSELECT = 0 of the multiplex circuit 25 is set, and SE (SAn) is a signal of SE, SA1 to SAn based on the data of the first register, that is, fuse data. The level also includes (1) when the fuse element is cut and (2) when the fuse element is set in the connected state.

When reset of the read fuse element data, the data is latched in the first register 21, the Pch load transistor Tr is turned off, the through current to the fuse element F is blocked, and unnecessary current Do not flow. Then, when the CPU starts to operate and access to the memory is made, and the address reaches the address of the defective cell of the main memory, that is, the address to be replaced, the fuse element stored in the first register 21 is stored. On the basis of the address match is detected, SE = 1 (i.e., / SE = 0), access to the word line WLx of the main cell where the original bad bit is present is prohibited, and a spare row line is selected (SWL). = 1), the spare cell is read out and the substitution is performed.

Next, in the writer mode, this mode is a mode in which a user writes data to a memory built in a microcomputer (here, EPROM) using a general-purpose writer or the like. Since the CPU is not operated, the mode is set to the RESET state. At this time, the fuse element data is read out while the previous Pch load transistor Tr is always turned on by the RESET inversion signal, and 0 is set to fE (fn) when the fuse element F is set in the connected state. 1 is output when the fuse element F is cut off. FE (fn) is fE and signal levels f1 to fn are 1 when the fuse element is disconnected and 2 when the fuse element is set in the connected state. Also in this mode, it is the same as in the one-chip mode, and RESELECT = 0 is set. Based on the data of the first register, that is, fuse data, SE (SAn) is SE, and signal levels of SA1 to SAn are also fuse elements. Is cut off and ① are set in the connected state.

If the address from the writer (external) reaches the address of the defective cell of the main memory, that is, the address to be replaced, the address matches based on the fuse data read out through the first register as in the RESET period in the one-chip mode. Is detected, when SE = 1, the spare row line SWL = 1, and the word line is replaced. At this time, writing to the spare cell is performed when the write signal WR comes, and reading is performed when the read signal RD comes.

Next, in the present invention, the test mode has two modes (test mode 1 and test mode 2), and test mode 1 is a mode for reading out a memory (here EPROM) built in the same microcomputer as the lighter mode. The register selection signal RSELECT input to the selection circuit 25 of the first and second register outputs is set to 1, which is different from the writer mode, and the test replacement address in the circuit 20 shown in FIG. Based on the data of the second register 22 that stores the data, the bad bit is replaced with a duplicate cell to perform a test.

In the test mode 2, the write / read check of the spare bit installed to replace the bad bit can be performed directly before the redundant fuse is cut, and at the same time, the data stored in the first register, that is, the read of the fuse data, Each address area is provided in the second register so that the test replacement address data (similar fuse data) in the previous test mode 1 can be recorded and read. When reading and writing a spare row (duplicate cell) in this mode, if an address signal for determining the row address of the duplicated cell is inputted from the outside, the signal is input to the multiplexer circuit 25 in FIG. In test mode 2, since TEST2 = 1 is set, it is input to the spare row line 3 through the level shifter 12. In addition, the TEST2 signal is input to the NOR circuit 13, and its output / SE becomes 0 at this time, and the row decoder 5 of the main cell is all unselected with all of the row decoders 8 disabled. Like the writer mode, the spare cell can be read and recorded.

When the address provided for the first register is set from the outside, RSELECT = 0 is set, and the output of the first register 21 controls the output to the data bus by the multiplexer 25 and the register data read signal RDFUSE. It is output to the data bus via the tri-state buffer 23, and the fuse data can be read from the outside. In addition, an address provided for the second register is set from the outside, and test replacement address data (similar fuse data) is input from the data bus data to the data input terminal D of the second register 22, and the latch signal terminal is provided. By controlling the write signal WRFUSE to the second register 22 connected to?, data can be written to the second register, and RSELECT = 1 is set, and the recorded data is multiplexed to the multiplexer 25 and three states. It is also possible to read from the outside through the buffer 23.

Incidentally, the greatest feature of the present invention resides in the redundant test flow described below and the circuit for realizing the test. Referring to the duplication test flow of FIG. 5, first, it is checked whether all the bits of the memory are initialized (erased) in the writer mode (first step). Thus, if all bits are in the initial state, the check for writing is performed (second step). Passing this second step is performed by separating the tester from the tester for high temperature and leaving it at a high temperature standing test (step 3), and reading all the bits into the tester whether or not the data recorded in the second step is after the third step. Check by performing (step 4). In the first step, the NG can be judged whether or not relief is possible by the specified number of row (word line) substitutions when the relief by the redundant circuit is performed (fifth step) and can be recorded in the second step. In the case where there is none, it is determined by the redundant circuit whether or not it is possible to remedy by the prescribed number of row (word line) substitutions (sixth step). Initialization (erasure) and writing are checked, and in the fifth and sixth relief determinations, initialization (erasure) and recording of duplicate cells are performed, and the relief addresses and replacements calculated in the fifth and sixth relief determinations are performed. The permission information is recorded in the second register (7th step).

In the test mode 1, the read check of all bits in the row-substituted state is performed based on the relief address stored in the second register (step 8), and the replacement address in the fifth and sixth steps The fuse element of the redundant circuit is cut based on the substitution permission information (ninth step). Finally, the high temperature standing test (the third step) and all subsequent bit readings are performed in the same manner as in the case where the relief by the redundant circuit is not performed, and it is checked whether the recorded data is erased (the fourth step), and the wafer test is finished. do.

The data written in the duplicated cells replaced in the seventh step may be the same as the data written in the cells of the row (word line) to be replaced in the second step. For example, a diagonal pattern as shown in FIG. 10 is written in the second step so that, when a bad bit exists in the word line WLa, the pattern being written in the word line WLa is recorded. When the data is written to the spare spare row SWL to be replaced, the comparison data pattern used to read all the bits of data in the fourth and eighth steps can be made the same as that without performing redundant relief, thereby improving test efficiency. This has the effect of reducing the pattern memory.

7 shows a timing chart of the test in the seventh step. In the seventh step, TEST2 = 1 for setting to test mode 2, and in order to first read the erased state of the duplicate cells, the memory map of the test mode 2 in FIG. 9 is sequentially used, for example, up to address 00000-000FF. When input, the spare row is accessed through the multiplexer 25 in FIG. 1, and the cell data can be read. If the check of the erased state of the duplicated cells is OK, then, based on the rescue address data determined in the fifth and sixth steps, the test pattern to be originally written to the bad word line is replaced with a spare row to be replaced with it. Recording, if it is OK, then set the address to the second register 22 (e.g., 0FF00 in this case), and replace replacement information and replacement address information of the duplicated cell from the outside. To store in each bit, RSELECT = 1 is set. When the WRFUSE signal is 1, data is input to the second register. When the WRFUSE signal is 1 or 0, the data is latched. In addition, in order to confirm that data is actually stored, setting the RDFUSE signal to 1 enables the output of the second register to be output to the data bus through the multiplexer circuit and the tri-state buffer of FIG.

8 is a timing diagram of the test in the eighth step.

In the eighth step, in order to set the test mode (1), a test is performed by substituting a bad bit based on TEST2 = 0, reading all the bits based on the replacement address data for the test stored in the second register in the seventh step. . Therefore, RSELECT = 1 is set so that the data of the second register is output through the multiplexer 25. Next, when an address is sequentially input from the outside as in the writer mode, when the address of the bad bit is reached, the output AE of the address detection circuit 20 of the address becomes 1 since the address is already stored in the second register. With / SE = 0, all of the main word lines are unselected and the spare row SWLx is accessed to read the data of the duplicate cells. In this way, the one-chip mode used by the user and the writer mode (that is, a mode other than the test mode used by the manufacturer) then replaces the bad bit based on the address relief information of the data of the first register, that is, the fuse data. have. On the other hand, it is a feature of the present invention that in the test mode used by the manufacturer at the time of testing, the substitution is performed based on the address relief information of the second register data, that is, the test fuse data.

In order to perform the repair by the conventional redundancy, it is judged whether or not the NG can be repaired by the prescribed low line replacement number in the initialization / write, and in the next step, the cut of the redundant fuse element is made based on the replacement address information. In order to do so, it needed to be separated from the tester.

However, in the present invention, the initial state / write check of the spare row line to be replaced by inputting a test address from the outside in the previous test mode can be performed as described above, and the test replacement address data (similar fuse data) can be inputted. By storing in two registers, the defective address can be replaced (7) and all the bit read checks can be performed (8) without actually cutting the fuse element. When the fuse is cut in the next step 9 only in the case of passing the step OK, the defective rate after the cut of the fuse element is lowered, and the test time is shortened.

The fuse element cut is then subjected to a high temperature standing test as in the prior art, and all bits are read and checked by the tester. Therefore, according to this test flow, the number of OFF racks (called off-racks once separated from the tester) is about one time as in the case of not performing rescue by overlapping, and the number of times of contacting the needle with the wafer does not change. Damage to the pads of semiconductor devices such as LSI can be suppressed to the minimum, and the test time and handling times can be shortened, thereby reducing the test efficiency.

A first register for reading and storing data from a nonvolatile storage means for storing address relief information, and a second register for storing replacement address data for testing externally; and in the normal use mode, the first register. By replacing the cells of the bad bit redundantly based on the address remedy information of the data of the data, in the test mode by replacing the cells of the bad bit with duplicate cells based on the address remedy information of the data of the second register to enable the test In the first tester test before the nonvolatile memory, in which the nonvolatile memory device includes the laser fusion fuse element, actually fuses the fuse element, the write / read test of the duplicated cell becomes possible, and only the duplicate cell is written after the fuse element melting. / Finished without reading test, after high temperature standing, In the second test, it is only necessary to test whether it is actually substituted, and the damage to the pad of the semiconductor device such as the LSI can be minimized and the test can be made more efficient.

Claims (6)

A memory cell array comprising a plurality of memory cells arranged on a plurality of word lines, a means for replacing the defective bits of the word line to which the defective bits are connected in the word line by replacing them with duplicate cells, and remedy information of the address and the duplicate cells Nonvolatile storage means for storing replacement permission information of the first and second registers for reading data from the storage means and storing the data, a second register for storing data from the outside, the first register and A selection circuit for selectively outputting each output of the second register based on a predetermined mode signal, and in the first mode other than the test mode, the bad bit based on the relief information of the address of the data of the first register. Is replaced with the duplicated cell, and in the second mode, which is a test mode, data of the second register is And performing a test by replacing the defective bit with a duplicate cell based on the relief information of the address of. The address area for performing read / write of data of a duplicate cell from the outside, and an address area for reading said first register and a good write / read of said second register are provided in another address area. And a third mode in which address areas for performing the above operation are provided, respectively. The semiconductor memory according to any one of claims 1 to 2, wherein the nonvolatile storage means for storing the relief information of the address and the replacement permission information of the duplicated cell comprises a fuse element melted with a current or a laser. Device. The semiconductor memory device according to any one of claims 1 to 3, further comprising: mounting a semiconductor memory device, reading data from said nonvolatile gear means during a reset period, and storing data in said first register by means of a reset release signal; And replacing the bits of the bad address based on the information of the data to rescue the microcontroller. 5. The first process according to any one of claims 1 to 4, wherein the first process checks whether all bits are in an initial state in the first mode, and (1) checks for writing if all bits are in an initial state. (2) a second step of performing a second step; and a third step of performing a high temperature leaving test once separated from the tester for the reliability test, if the remedy by the redundant circuit is not performed based on the second step; (3) In the fourth step (4) of checking all the bits by the tester to check whether the recorded data is erased after the third step, and (4) when the relief is performed by the redundant circuit based on the first step. A fifth step (5) of determining whether or not all the bits are not initialized and can be remedied by a prescribed number of row (word line) substitutions; and a part of bits in all bits based on the second step. The sixth step (6) of determining whether it is possible to save by the specified row (word line) substitution number by the redundant circuit with respect to the unrecordable, and the thing that can be saved by the redundant circuit based on the sixth step A seventh step (7) of performing initialization (erase) of the duplicate cells and checking of the duplicated cells in the third mode, and writing relief addresses and replacement permission information to the second register; and (7) in the second mode. An eighth step (8) of performing a read check of all bits in the row-substituted state based on the relief address stored in the second register; and an overlapping circuit based on the substitution address and the substitution permission information based on the eighth step. The ninth process 9 which cuts a fuse element is provided, and goes through the said 3rd and 4th process like the case where the relief by a redundant circuit is not performed after the said 9th process. A method for fabricating a semiconductor memory device, characterized in that performing the check rudder. 6. The semiconductor according to claim 5, wherein the data written in the duplicated cell replaced in the seventh step is the same data as the data written in the row (word line) cell to be replaced in the second step. Method of manufacturing a memory device.