JP2005018983A - Semiconductor nonvolatile memory device and memory system - Google Patents

Semiconductor nonvolatile memory device and memory system Download PDF

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JP2005018983A
JP2005018983A JP2004281465A JP2004281465A JP2005018983A JP 2005018983 A JP2005018983 A JP 2005018983A JP 2004281465 A JP2004281465 A JP 2004281465A JP 2004281465 A JP2004281465 A JP 2004281465A JP 2005018983 A JP2005018983 A JP 2005018983A
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data
memory cells
program
error
memory
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JP2005018983A5 (en
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Kenshirou Arase
Tadahachi Naiki
Masanori Noda
Hisanobu Sugiyama
唯八 内貴
寿伸 杉山
謙士朗 荒瀬
昌敬 野田
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Sony Corp
ソニー株式会社
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Abstract

A semiconductor nonvolatile memory device capable of high-speed data programming is realized.
Error correction means (20, 30) is provided for correcting error bits when page data is read in units of word lines and there are less than a predetermined number of error bits in the page read data. In a unit page program, when there are unprogrammed memory cells after a predetermined number of program / verify operations, the count circuit 40 counts the number of program-unfinished memory cells, and the number is corrected for error. When the number of possible error bits is within the predetermined number, the data program is terminated while leaving unprogrammed memory cells, and the error correction unit rescues the error bits. Therefore, the data program can be performed at a high speed without being limited by a very slow memory cell that exists very rarely.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor nonvolatile memory device and a memory system that can electrically program data, and more particularly, to data programming and erasing speedup.

In a semiconductor nonvolatile memory device such as a NAND flash memory or a DINOR flash memory, a data program is performed for all memory cells connected to a selected word line.
That is, page programming is performed in units of word lines.

  FIGS. 7A and 7B are diagrams showing the memory array structures in the NAND type and DINOR type flash memories, respectively.

FIG. 7A is a diagram showing a NAND flash memory array when four memory cells are connected to one NAND string connected to one bit line for convenience.
In FIG. 7A, BL indicates a bit line, and a NAND string in which two selection transistors ST1 to ST2 and four memory cells MT1 to MT4 are connected in series is connected to the bit line BL.
Select transistors ST1 to ST2 are controlled by select gate lines SL1 and SL2, respectively, and memory cells MT1 to MT4 are controlled by word lines WL1 to WL4, respectively.

FIG. 7B is a diagram showing a DINOR type flash memory array in the case where four memory transistors are connected to one sub bit line connected to one main bit line for convenience.
In FIG. 7B, MBL indicates a main bit line, SBL indicates a sub bit line, and the main bit line MBL and the sub bit line SBL are operatively operated via a selection transistor ST1 controlled by a selection gate line SL. Connected.
The sub-bit line SBL intersects the four word lines WL1 to WL4, and four memory cells MT1 to MT4 are arranged at each intersection position.

  In a semiconductor nonvolatile memory device such as a NOR flash memory, data is rewritten after data is erased in a predetermined block unit (for example, about 64 Kbytes) and then the data is stored in the memory cell of the erase block. The program is performed.

  FIG. 8 is a diagram showing a memory array structure and a bias condition at the time of data erasure in a general NOR type flash memory.

  In the NOR flash memory of FIG. 8, for convenience, memory cells MT11 to MT44 are arranged in a matrix at lattice positions of the four word lines WL1 to WL4 and the four bit lines BL1 to BL4.

Next, a data erasing operation in the NOR type flash memory of FIG. 8 will be described.
As shown in FIG. 8, in the data erasure, all the word lines WL1 to WL4 in the erase block memory array are set to the ground level (0V), all the bit lines BL1 to BL4 are set in the floating state, and the common source line VSS is set high. An erase voltage pulse of a voltage (for example, 12V) is applied.
As a result, electrons stored in each memory cell at the time of data programming are extracted from the source side by a tunnel current, and the threshold voltage Vth of each memory cell is changed from 6 V to 7 V in the data program state to 2 V in the erase state. Transition to 3V.

By the way, in a semiconductor nonvolatile memory device that performs page programming in units of word line sectors such as the above-mentioned NAND type, DINOR type flash memory, etc., data programming is performed for all memory cells connected to a selected word line. Data program.
However, each memory cell connected to the selected word line has a difference in program speed due to variations in size and the like due to the manufacturing process.

FIG. 9 is a diagram showing a difference in program speed between the memory cells connected to each of the selected word lines.
In FIG. 9, the horizontal axis represents tPROG (program time), that is, the program required time of each memory cell.
The vertical axis represents the distribution frequency of the number of memory cells corresponding to N (number of memory cells), that is, the horizontal axis tPROG (program time).

As shown in FIG. 9, in a semiconductor nonvolatile memory device that performs page programming in units of word line sectors such as a NAND flash memory or the like, a distribution occurs in the required program time tPROG between memory cells.
In consideration of such variations in the program speed, in a general NAND flash memory or the like, the program operation is performed via the verify operation from the viewpoint of suppressing the distribution of the threshold voltage Vth during programming, In addition, a so-called bit-by-bit verify operation is performed in which the program / verify operation is sequentially prohibited from the program end memory cell until the program of all the memory cells is completed.

However, as shown in FIG. 9, in the case of a general memory cell, the program required time tPROG is t0 in the figure, but a memory that requires a very long program required time tPROG, for example, t1 or more in the figure, due to a variation factor such as a process. There may be rare cells.
In such a case, the number of program / verify operations described above is very large, for example, 100 times or more due to a memory cell having a slow program that exists very rarely, and as a result, it is necessary to complete the page program. The time is also very long.

FIG. 10 is a diagram showing a sequence flow at the time of data programming in a semiconductor nonvolatile memory device that performs page programming in units of word line sectors such as the conventional NAND flash memory.
Hereinafter, the sequence flow of FIG. 10 will be described in order.

In step SF1, a data program is started. First, in step SF2, page program data is transferred to a data latch circuit provided for each bit line in the memory array.
Next, in step SF3, the program verify count K is reset to 0, a program operation for applying a program pulse (step SF4), and a verify read operation for automatically setting reprogram data after verify read (step SF5) are continuously performed. Done.
Next, in step SF6, end point detection as to whether or not the programming of all the memory cells has been completed is performed by examining whether or not at least one or more unprogrammed memory cells remain in the reprogram data.

As a result, when the end point of the end of all bit programs is detected, the data program is completed (step SF9).
On the other hand, when the end point detection of the end of all bit programs cannot be detected, the program verify count K is further incremented (step SF7), and whether K is less than a preset predetermined count k0 (for example, about 100). Is examined (step SF8).
If K is less than k0, the sequence flow of steps SF4 to SF8 described above is repeated, and it is determined that the data program has failed when K reaches k0 (step SF10).

  The predetermined number of program verifications K0 is extremely large, for example, 100 times or more in the case of a conventional NAND flash memory or the like because of a rarely-programmed memory cell, and as a result, the page program is terminated. The time required for this was very long.

In a semiconductor nonvolatile memory device such as the NOR flash memory described above, data is rewritten by erasing data in a predetermined block unit (for example, about 64 Kbytes) and then executing a data program in the block unit. Do.
However, each memory cell in the erase block unit has a difference in erase speed due to variations in size and the like due to the manufacturing process.

FIG. 11 is a diagram showing a difference in erase speed between memory cells in the erase block.
In FIG. 11, the horizontal axis represents terase (erase time), that is, the time required for erasing each memory cell.
The vertical axis represents the distribution frequency of the number of memory cells corresponding to N (number of memory cells), that is, the horizontal axis terase (erasing time).

As shown in FIG. 11, in a semiconductor nonvolatile memory device that erases data in a predetermined block unit such as a NOR flash memory, a distribution occurs in the required erase time terase between memory cells.
In consideration of such variation in the erase speed, in a general NOR flash memory, the erase operation is performed through the verify operation, and the erase / verify operation is performed on the data of all the memory cells in the erase block. This process is repeated until erasing is completed.

However, as shown in FIG. 11, in the case of a general memory cell, the erase required time terase is t0 in the figure. However, a memory that requires a very long erasing required time terase, for example, t1 or more in the figure due to a variation factor such as process There may be rare cells.
In such a case, the number of erase / verify operations described above becomes extremely large, for example, 100 to 1000 times or more due to a memory cell that is slow to erase, and as a result, the erase operation ends. The time required for the data becomes very long, and the time required for rewriting the data also becomes long.
Furthermore, if the number of erase / verify operations is extremely large due to a rarely erasable memory cell, the memory cell that is quickly erased is over-erased and the threshold voltage Vth of the memory cell is depleted. (Vth <0), causing malfunction.

FIG. 12 is a diagram showing a sequence flow at the time of data erasure and subsequent data programming in a semiconductor nonvolatile memory device in which data is rewritten in a predetermined block unit such as the conventional NOR type flash memory.
Hereinafter, the sequence flow of FIG. 12 will be described in order.

In step SF21, data erasure is started, and in step SF22, an erase operation (step SF23) in which the erase verify number K is set to the first 1 and an erase pulse is applied, and a verify read operation (step SF24) are successively performed. .
As a result of the verify read operation in step SF24, when the end point of the erase end of all the memory cells in the block can be detected (step SF25), the data erase is completed and the data program operation in step SF101 is started. .

On the other hand, as a result of the verify read operation in step SF24, if the end point of the end of erasure of all the memory cells in the block cannot be detected (step SF25), in step SF26, the erase verify count K is set in advance. It is checked whether the number of times is less than K0 (for example, about 100 to 1000 times).
As a result, if the erase verify count K is less than the set count K0, the erase verify count K is further incremented (step SF27), and the above-described sequence flow of steps SF23 to SF27 is repeated. When the erase verify count K reaches the set count K0, it is determined that the data erase has failed (step SF28).

Next, when the end point of the end of erasure of all the memory cells in the block can be detected, the data program is subsequently started.
First, in step SF101, the memory cell address address Ar-NO is set to the first one, and the data program is performed on the memory cell in accordance with the data contents (step SF102), and the address address Ar-NO is final. It is checked whether or not there is an address address (step SF103).
As a result, when the address address Ar-NO is not the final address address, the address address Ar-NO is further incremented (step SF104), and the above-described sequence flow of steps SF102 to SF104 is repeated. When the address address Ar-NO reaches the final address address, the data program is completed (step SF105).

In the above-described sequence flow, the predetermined erase verify number K0 is very large, for example, about 100 to 1000 times in the case of a conventional NOR type flash memory or the like because of a rarely present memory cell that is slowly erased. As a result, the time required to complete the erasing operation is very long, and the time required for rewriting data is also long.
Furthermore, because of the slow erasing memory cell, the fast erasing memory cell is over-erased, causing a malfunction.

  The present invention has been made in view of such circumstances, and its purpose is to enable data programming at high speed, data rewriting at high speed, and generation of overerased memory cells. An object of the present invention is to provide a semiconductor nonvolatile memory device and a memory system that can be prevented and improve reliability.

  In order to achieve the above object, a first aspect of the present invention is a semiconductor nonvolatile memory device in which memory cells for electrically processing data are arranged in a matrix, and within a predetermined number of bits in a plurality of bits of data. When there is an error bit, the error correction means for correcting the error bit and the processing of the data in units of the multi-bit data are performed on the memory cells of the plurality of units, and the data processing is not completed after the data is processed Means for counting the number of memory cells, and when the number of data processing unfinished memory cells is within the predetermined number of error bits, the processing of data is terminated while leaving the data processing unfinished memory cells, Means for relieving the error bit by the error correction means.

  A second aspect of the present invention is a semiconductor nonvolatile memory device in which memory cells in which data is electrically programmed are arranged in a matrix, data is read out in units of a plurality of bit data, and the plurality An error correction unit that corrects the error bit when there is a predetermined number of error bits in the bit data, and a data program that uses the plurality of bit data as a unit is performed on the plurality of units of memory cells. Means for counting the number of unprogrammed memory cells later, and if the number of unprogrammed memory cells is an error bit within the predetermined number, the data program is terminated with the unprogrammed memory cells remaining. And means for relieving the error bit by the error correction means.

  According to a third aspect of the present invention, sector-unit page program data is transferred to a data latch circuit provided for each bit line, and the data program is electrically stored in the memory cells of the sector selected according to the data. Is a semiconductor nonvolatile memory device in which memory cells are arranged in a matrix, and page data is read in units of memory cells in a selected sector, and there is a predetermined number of error bits in the page read data. Error correction means for correcting the error bit, and a data program according to the page program data is performed by repeatedly performing a program operation a plurality of times through a verify read operation, and a program unfinished memory for each program operation Means for detecting whether a cell exists and a predetermined number of times Means for counting the number of non-programmed memory cells when there are non-programmed memory cells after repeatedly performing a program operation, and the number of unprogrammed memory cells is an error bit within the predetermined number In this case, there is provided means for ending the data program while leaving the non-programmed memory cell and causing the error correction means to rescue the error bit.

  According to a fourth aspect of the present invention, there is provided a memory system in which memory cells in which data is electrically programmed are arranged in a matrix, data is read out in units of multi-bit data, and the multi-bit data is stored in the multi-bit data. An error correction means for correcting the error bit when there is a predetermined number of error bits and a data program in units of the multi-bit data are performed on the memory cells of the plurality of units, and the program is not completed after the data program Means for determining the number of memory cells, and when the number of unprogrammed memory cells is within the predetermined number of error bits, the data program is terminated with the program unfinished memory cells left, and the error bit Means for relieving the error correction means.

  Preferably, the error correction means includes means for generating an error check code from normal data to be programmed, a normal memory array unit for recording the normal data, and a parity for recording the error check code. A memory array composed of a memory array unit, means for page-programming page program data synthesized from the normal data and an error check code into the memory array, and normal data read when the page program data is read And means for correcting an error bit at the time of data programming using an error check code.

  Preferably, the non-programmed memory cell detecting means sequentially inverts the data latched in the data latch circuit connected to the programmed memory cell for each verify read operation after each program operation. Means for automatically setting reprogram data, and end point detection means for detecting whether or not there is at least one data latch circuit that latches unprogrammed data after the reprogram data is automatically set And.

According to the semiconductor nonvolatile memory device of the present invention, even if there are unprogrammed memory cells after repeating a predetermined number of data processing, for example, a program operation, the number of unprogrammed memory cells is determined by the error correction means. If the number of error bits is within a predetermined number that can be corrected, the data program is terminated while leaving unprogrammed memory cells.
Therefore, the data program can be performed at a high speed without being limited by a very slow memory cell that exists very rarely.

  According to the present invention, a data program can be performed at high speed.

First Embodiment FIG. 1 is a diagram showing a specific configuration example of a semiconductor nonvolatile memory device according to the present invention, for example, a NAND flash memory.

  In FIG. 1, reference numeral 10 denotes a memory body. The memory body 10 includes a memory array unit 11, a row decoder 12, a data latch circuit group 13 provided for each bit line, a column selection unit 14, a reprogram data automatic setting circuit. A group 15 and an end point detection circuit 16 are included.

The memory array 11 includes a normal memory array 11a and a parity memory array 11b.
N (usually about 512 bytes) normal bit lines B1 to Bn are wired to the normal memory array 11a, and j (usually about 10 bytes) parity bit lines b1 to bj are wired to the parity memory array 11b. Has been.
In the figure, the word line Wm is selected and page programming is performed on the normal memory cells MT1 to MTn and the parity memory cells mT1 to mTj.

The data latch circuit group 13 includes normal data latch circuits SA1 to SAn and parity data latch circuits sA1 to sAj, and the column selection unit 14 includes a normal column selection unit 14a and a parity column selection unit 14b.
The column selector 14 operates in synchronization with the data transfer clock signal φCL, shifts and transfers page program data to the normal data latch circuits SA1 to SAn and the parity data latch circuits sA1 to sAj, and reads page data from the data latch circuit. I do.

The reprogram data automatic setting circuit group 15 includes automatic setting circuits 15S-1 to 15S-n and 15s-1 to 15s provided for the regular data latch circuits SA1 to SAn and the parity data latch circuits sA1 to sAj. -J.
The automatic setting circuits 15S-1 to 15S-n and 15s-1 to 15s-j are data latched in the data latch circuit connected to the memory cell to which the program has been completed for each verify read operation after each program operation. The reprogram data is automatically set by sequentially inverting.

The end point detection circuit 16 includes transistors T1 to Tn and Tp1 to Tpj provided for each of the regular data latch circuits SA1 to SAn and the parity data latch circuits sA1 to sAj, a transistor Tset, and an inverting circuit INV1.
The gate electrodes of the transistors T1 to Tn and T1 to Tj are connected to the inverted outputs of the normal data latch circuits SA1 to SAn and the parity data latch circuits sA1 to sAj, the source electrode is connected to the ground potential, and the drain electrode is commonly connected. In the case where there is a non-programmed cell and the inverted output of at least one data latch circuit is at a high level, the endpoint detection potential Va connected in common becomes the ground potential, and the endpoint detection signal ENDout is generated by the inverter circuit INV1. Output as high level.
The transistor Tset is provided to precharge the end point detection potential Va to the VCC level in advance, and is driven by the precharge signal φset prior to the end point detection.

Reference numeral 20 denotes a data input unit. The data input unit 20 includes a data input circuit 21 and an error check code generation circuit 22.
The data input circuit 21 inputs the normal input data [Din] 1 to n to the error check code generation circuit 22 and generates error check codes (parity input data) [Cin] 1 to j. The page program data synthesized by the normal input data [Din] 1 to n and the error check codes [Cin] 1 to j is synchronized with the data transfer clock signal φCL and the normal data latch circuits SA1 to SAn and the parity data latch, respectively. Shift-transferred to the circuits sA1 to sAj and page-programmed to the corresponding normal memory cells and parity memory cells.

Reference numeral 30 denotes a data output unit. The data output unit 30 includes an error check circuit 31 and a data correction circuit 32.
The error check circuit 31 generates data demodulated codes [S] 1 to j based on the normal output data [Dout] 1 to n and the error check codes (parity output data) [Cout] 1 to j read out from the page.
The data correction circuit 32 detects the error bits within a predetermined number (for example, 1 bit) in the page read data due to the normal output data [Dout] 1 to n and the data demodulation codes [S] 1 to j. Correct and output correct correct output data [DATA] 1 to n after correction.

Reference numeral 40 denotes a count circuit (counting circuit). The count circuit 40 is configured to detect the end point after a predetermined number of program verify times (for example, about 10 times) and the end point cannot be detected because there is an unprogrammed memory cell. When the output of one or more data latch circuits is at a low level, the number of unprogrammed memory cells is counted as follows.
That is, the output DATAver ′ of the inversion circuit INV2 of the verify page read data DATAver synchronized with the basic data transfer clock signal φCL is shifted in, and finally the number of unprogrammed memory cells is counted according to the input of the check signal φCHK.

  When the output signal φCHK of the inverting circuit INV1 of the memory body 10 is input at a high level, the unfinished determination circuit 50 checks that there is a program unfinished memory cell and starts counting the number of program unfinished memory cells. Signal φCHK is output to count circuit 40.

When the output check signal φCNT of the count circuit 40 is switched to the high level, the determination circuit 60 assumes that there is one or more unprogrammed cells and outputs it to a control system (not shown).
In the case of this embodiment, the determination circuit 60 is configured by, for example, a flip-flop.

  FIG. 2 is a diagram showing the relationship between the number n of normal data bits that can deal with a 1-bit error and the number of parity data bits (number of error check bits) j in the error correction means in the semiconductor nonvolatile memory device of FIG.

The principle of error correction, the error check code generation circuit 22, the error check circuit 31, and the data correction circuit 32 are not directly related to the gist of the present invention, and will not be described in detail here.
However, according to FIG. 2, the number of 512-bit normal data bits requires 10 bits of error check bits, and therefore, the normal 512-bit normal input data [Din] 1
It is necessary to generate a 10-bit error check code [Cin] 1 to j in .about.n.

FIG. 3 is a diagram showing a sequence flow at the time of data programming in the semiconductor nonvolatile memory device of FIG.
Hereinafter, the sequence flow of FIG. 3 will be described step by step with reference to the configuration example of FIG.

In step S1, the data program is started. Based on the normal input data [Din] 1 to n input through the data input circuit 21 first, the error inspection code [Cin] 1 to j is generated by the error inspection code generation circuit 22. Is generated (step S2).
Then, the normal input data [Din] 1 to n and the error check codes [Cin] 1 to j are input to the normal column selection 14a and the parity column selection 14b, and the combined page program data is stored for each bit line in the memory array. The data is transferred to the provided normal data latch circuits SA1 to SAn and parity data latch circuits sA1 to sAj (step S3).

  Next, a program control system (not shown) resets the program verify count K to 0 in step S4, and a program operation for applying a program pulse is performed (step S5). After verify read, the automatic setting circuits 15S-1 to 15S- In n, 15s-1 to 15s-j, a verify read operation for automatically setting reprogram data by sequentially inverting the data in the normal data latch circuits SA1 to SAn and the parity data latch circuits sA1 to sAj of the program end memory cell (step S6) is performed continuously.

  Next, in step S7, in the end detection circuit 16 and the incomplete determination circuit 50, end point detection as to whether or not the program of all the memory cells has been completed is detected in at least one program incomplete memory cell in the reprogram data. This is done by checking whether the corresponding data remains.

As a result, when the end point of the end of all bit programs can be detected, the data program is completed (step S12).
However, if the end point detection of the end of all bit programs cannot be detected, the program verify count K is further incremented (step S8), and is K less than a predetermined count k0 (for example, about 10)? It is checked whether or not (step S9).
If K is less than k0, the sequence flow of steps S5 to S9 described above is repeated, and the process proceeds to step S10 when K reaches k0.

In step S10, the data in the data latch circuit is page-read and the number of unprogrammed memory cells is counted by the count circuit 40. Next, in step S11, it is checked whether or not the counted number of unprogrammed memory cells is within a predetermined number (for example, one) that can be error-corrected.
As a result, when the number of unprogrammed memory cells is within a predetermined number capable of error correction, the data program is completed (step S12), and when it exceeds the predetermined number, it is determined that the data program has failed (step S12). Step S13).

  In the semiconductor nonvolatile memory device of the present invention in which the data program is performed by the above sequence flow, the error check circuit 31 and the data correction circuit 32 perform error correction of the unprogrammed memory cell at the time of data reading, and correct normal Data [DATA] 1 to n are read.

As described above, according to the semiconductor nonvolatile memory device according to the first embodiment, even if a non-programmed memory cell exists after a predetermined number of program operations are repeated, the program-unfinished memory cell If the number of error bits is within a predetermined number that can be corrected by the error correction means, the data program is terminated while leaving unprogrammed memory cells.
Therefore, the data program can be performed at a high speed without being limited by a very slow memory cell that exists very rarely.

Second Embodiment FIG. 4 is a diagram showing a specific configuration example of a semiconductor nonvolatile memory device according to the present invention, for example, a NOR flash memory.

  That is, in FIG. 4, reference numeral 100 denotes a memory body. The memory body 100 includes a memory array unit 111, a row decoder 112, a data latch circuit group 113 provided for each bit line, a column selection unit 114, a reprogram data automatic The circuit includes a setting circuit group 115, an end point detection circuit 116, and the like.

The memory array 111 is composed of a regular memory array 111a and a parity memory array 111b.
N (usually about 512 bytes) normal bit lines B1 to Bn are wired to the normal memory array 111a, and j (usually about 10 bytes) parity bit lines b1 to bj are wired to the parity memory array 111b. Has been.
In the figure, a case where the word line Wm is selected and page reading is performed on the normal memory cells MT1 to MTn and the parity memory cells mT1 to mTj is illustrated.

The data latch circuit group 113 includes normal data latch circuits SA1 to SAn and parity data latch circuits sA1 to sAj, and the column selection unit 114 includes a normal column selection unit 114a and a parity column selection unit 114b.
The column selector 114 operates in synchronization with the data transfer clock signal φCL, shifts and transfers page program data to the normal data latch circuits SA1 to SAn and the parity data latch circuits sA1 to sAj, and from the data latch circuit in units of word lines. Read page data.

The reprogram data automatic setting circuit group 115 includes automatic setting circuits 115S-1 to 115S-n and 115s-1 to 115s provided for the regular data latch circuits SA1 to SAn and the parity data latch circuits sA1 to sAj. -J.
The automatic setting circuits 115S-1 to 115S-n and 115s-1 to 115s-j store the data latched in the data latch circuit connected to the memory cell to which the program has been completed for each verify read operation after each program operation. The reprogram data is automatically set by sequentially inverting.

The end point detection circuit 116 includes transistors T1 to Tn and Tp1 to Tpj provided for each of the regular data latch circuits SA1 to SAn and the parity data latch circuits sA1 to sAj, a transistor Tset, and an inverting circuit INV100.
The gate electrodes of the transistors T1 to Tn and Tp1 to Tpj are connected to the inverted outputs of the normal data latch circuits SA1 to SAn and the parity data latch circuits sA1 to sAj, the source electrode is connected to the ground potential, and the drain electrode is commonly connected. When the incomplete erased cell exists and the inverted output of at least one data latch circuit is at the high level, the end point detection potential Va connected in common becomes the ground potential, and the end point detection signal ENDout is generated by the inversion circuit INV1. Output as high level.
The transistor Tset is provided to precharge the end point detection potential Va to the VCC level in advance, and is driven by the precharge signal φset prior to the end point detection.

Reference numeral 120 denotes a data input unit, and the data input unit 120 includes a data input circuit 121 and an error check code generation circuit 122.
The data input circuit 121 inputs the normal input data [Din] 1 to n to the error check code generation circuit 122 and generates error check codes (parity input data) [Cin] 1 to j. The page program data in units of word lines synthesized by the normal input data [Din] 1 to n and the error check codes [Cin] 1 to j are respectively synchronized with the data transfer clock signal φCL and the normal data latch circuits SA1 to SAn. The data is shifted and transferred to the parity data latch circuits sA1 to sAj, and data is sequentially programmed into the corresponding normal memory cells and parity memory cells.

Reference numeral 130 denotes a data output unit. The data output unit 130 includes an error check circuit 131 and a data correction circuit 132.
The error check circuit 131 generates data demodulated codes [S] 1 to j based on the normal output data [Dout] 1 to n and the error check codes (parity output data) [Cout] 1 to j read out from the page.
When the normal output data [Dout] 1 to n and the data demodulated codes [S] 1 to j indicate that there are less than a predetermined number (for example, 1 bit) of error bits in the page read data, the data correction circuit 132 detects this. Correct and output correct normal output data [DATA] 1 to n after correction.

Reference numeral 140 denotes a count circuit (counting circuit). The count circuit 140 repeats a predetermined number of erase verify times (for example, about 10 to several tens of times) and then erased unfinished memory cells are included in each page in the erase block. When the end point cannot be detected because it exists, that is, when the output of one or more data latch circuits is at the high level during the verify read for each page, the number of unerased memory cells is counted as follows.
That is, verify page read data DATAver synchronized with the basic data transfer clock signal φCL is shifted in, and finally the number of unerased memory cells is counted according to the input of the check signal φCHK.

  When the output signal φCHK of the inverting circuit INV100 of the memory main body 100 is input at a high level, the incomplete determination circuit 150 checks to start counting the number of unerased memory cells, assuming that there are unerased memory cells. Signal φCHK is output to count circuit 140.

When the output check signal φCNT of the count circuit 140 is switched to the high level, the determination circuit 160 assumes that there is one or more cells that have not been erased and outputs them to a control system (not shown).
Also in the present embodiment, the determination circuit 160 is configured by, for example, a flip-flop.

  In the error correction means in the semiconductor nonvolatile memory device of FIG. 4, the relationship between the number n of normal data bits that can deal with a 1-bit error and the number of parity data bits (number of error check bits) j is the same as in the first embodiment. The relationship is as shown in FIG.

The principle of error correction, the error check code generation circuit 122, the error check circuit 131, and the data correction circuit 132 are not directly related to the gist of the present invention and will not be described in detail here.
However, according to FIG. 2, the number of regular data bits of 512 bits requires 10 bits of error check bits.
Therefore, when the erase block unit is composed of 64 Kbytes of 128 pages with a word line of 512 byte page size, 512-bit regular input data [Din] 1 to n has a 10-bit error check for each page. It is necessary to generate codes [Cin] 1 to j.

FIG. 5 is a diagram showing a sequence flow at the time of erasing data when data is rewritten in the semiconductor nonvolatile memory device of FIG.
FIG. 6 is a diagram showing a sequence flow in the subsequent data program.
Hereinafter, the sequence flows of FIGS. 5 and 6 will be described in order with reference to the configuration example of FIG.

First, the sequence flow at the time of data erasure in FIG. 5 will be described.
In step S21, data erasure is started, and in step S22, an erase operation (step S23) in which the erase verify count K is first set to 1 and an erase pulse is applied, and a verify read operation (step S24) are successively performed. .
As a result of the verify read operation in step S24, if the end point of the end of erasure of all the memory cells in the block can be detected (step S25), the data erasure is completed.

On the other hand, as a result of the verify read operation in step S24, if the end point of the erase end of all the memory cells in the block cannot be detected (step S25), in step S26, the erase verify count K is set in advance. It is checked whether the number of times is less than K0 (for example, about 100 to 1000 times).
As a result, if the erase verify count K is less than the set count K0, the erase verify count K is further incremented (step S27), and the sequence flow of steps S23 to S27 described above is repeated. Then, when the erase verify count K reaches the set count K0, it is determined that there is an unerased memory cell, and the process proceeds to step S28.

  In step S28, the page address Pg-NO in the erase block is first set to 1, the erase data of the data latch circuit is read out, and the number of unerased memory cells is counted (step S29). .

Next, in step S30, it is checked whether or not the counted number of unerased memory cells is within a predetermined number (for example, one) until error correction is possible.
As a result, if the number of unerased memory cells exceeds a predetermined number capable of error correction, it is determined that data erasure has failed (step S34).
On the other hand, if the number of unerased memory cells is within a predetermined number that can be error-corrected, it is checked whether or not the page address Pg-NO is the final address (step S31).
If the page address Pg-NO is not the final address address, the page address Pg-NO is further incremented (step S32), and the sequence flow of steps S29 to S32 described above is repeated. Then, when the page address Pg-NO reaches the last page address, it is determined that the data erasure is completed (step S33).

Next, the sequence flow at the time of data programming in FIG. 6 will be described.
When the erasing of data is completed (step S33 in FIG. 3), the data program is subsequently started (step S101).
First, in step S102, the page address Pg-NO in the block is first set to 1, and based on the normal input data [Din] 1 to n of the page, the error check code generation circuit 22 performs error check code [Cin ] 1 to j are generated (step S103).
Next, the address address Pg-NO of the memory cell is set to the first 1 in the page (step S104), and data programming is performed on the memory cell according to the data content (step S105). It is checked whether or not the address Ar-NO is the final address (step S106).
As a result, when the address address Ar-NO is not the final address address, the address address Ar-NO is further incremented (step S107), and the above-described sequence flow of steps S103 to S107 is repeated. When the address address Ar-NO reaches the final address address, the data program for the page is completed.

Next, in step S108, it is checked whether or not the page address Pg-NO is the final address.
As a result, if the address address Pg-NO is not the final address, the page address Pg-NO is further incremented (step S109), and the sequence flow of steps S103 to S109 described above is repeated. When the address address Ar-NO reaches the final address address, the data program for the page is completed (S110).

In the semiconductor nonvolatile memory device of the present invention in which data has been rewritten by the above sequence flow, the error check circuit 31 and the data correction circuit 32 perform error correction of the unerased memory cells at the time of data reading, and correct Regular data [DATA] 1
~ N is read.

As described above, according to the semiconductor nonvolatile memory device according to the second embodiment, even if there is an unerased memory cell after the erase operation is repeated a predetermined number of times, the unerased memory cell is erased. If the number of error bits is within a predetermined number that can be corrected by the error correction means, the data program is performed with the memory cells not yet erased remaining.
Therefore, the data program can be performed at a high speed without being limited by a very slow erasing memory cell, which can be rewritten at a high speed.
Furthermore, it is possible to prevent excessively erased memory cells from being quickly erased, and to realize a highly reliable semiconductor nonvolatile memory device.

1 is a diagram showing a configuration example of a first embodiment of a semiconductor nonvolatile memory device according to the present invention. FIG. 2 is a diagram showing the relationship between the number n of normal data bits that can deal with a 1-bit error and the number of parity data bits (number of error check bits) j in the error correction means in the semiconductor nonvolatile memory device of FIG. FIG. 2 is a diagram showing a sequence flow at the time of data programming in the semiconductor nonvolatile memory device of FIG. 1. It is a figure which shows the structural example of 2nd Embodiment of the semiconductor non-volatile memory device which concerns on this invention. FIG. 2 is a diagram showing a sequence flow at the time of data erasure in the semiconductor nonvolatile memory device of FIG. 1. FIG. 2 is a diagram showing a sequence flow at the time of data programming in the semiconductor nonvolatile memory device of FIG. 1. 1 is a diagram showing a memory array structure in NAND type and DINOR type flash memories. FIG. FIG. 3 is a diagram showing a memory array structure and bias conditions at the time of data erasure in a general NOR type flash memory. FIG. 10 is a diagram illustrating a difference in program speed between memory cells of a semiconductor nonvolatile memory device that performs page programming in units of conventional word line sectors. It is a figure which shows the sequence flow at the time of a data program in the semiconductor non-volatile memory device which performs the page program in the unit of the conventional word line sector. It is a figure which shows the difference of the erase speed between the memory cells in an erase block. It is a figure which shows the sequence flow at the time of the data rewriting in the conventional NOR type flash memory.

Explanation of symbols

B1-Bn: normal bit lines, b1-bj: parity bit lines, Wm: selected word lines, MT1-MTn: normal memory cells, mT1-mTj: parity memory cells, SA1-SAn: normal data latch circuits, sA1-sAj ... Parity data latch circuit, [Din] 1 to n ... Normal input data, [Dout] 1 to n ... Normal output data, [DATA] 1 to n ... Normal output data after error correction, [Cin] 1 to j ... Input error check code, [Cout] 1 to j ... Output error check code, [S] 1 to j ... Data demodulation code, DATAver ... Verify page read data, φCL ... Data transfer clock signal, φcheck ... Check signal, φset ... Pre Charge signal, ENDout ... end point detection signal, Va ... end point detection potential, INV1 to INV2, INV100 ... ..., 10, 100... Memory body, 11, 111... Memory array section, 11a, 111a... Regular memory array, 11b, 111b .. parity memory array, 12, 112. , 114 ... column selection unit, 14a, 114a ... regular column selection unit, 14b, 114b ... parity column selection unit, 15, 115 ... reprogram data automatic setting circuit, 16, 116 ... end point detection circuit, 20, 120 ... data input , 21, 121 ... data input circuit, 22, 122 ... error check code generation circuit, 30, 130 ... data output unit, 31, 131 ... error check circuit, 32, 132 ... data correction circuit, 40, 140 ... count circuit , 50, 150... Unfinished determination circuit, 60, 160.

Claims (10)

  1. A semiconductor nonvolatile memory device in which memory cells for electrically processing data are arranged in a matrix,
    Error correction means for correcting the error bit when there is a predetermined number of error bits in the multi-bit data;
    Means for processing the data in units of the plurality of bit data with respect to the memory cells of the plurality of units, and counting the number of unfinished memory cells after data processing;
    If the number of unprocessed memory cells is within the predetermined number of error bits, the data processing is terminated with the unprocessed memory cells remaining, and the error bits are repaired to the error correction means. A semiconductor non-volatile storage device comprising:
  2. A semiconductor nonvolatile memory device in which memory cells in which data is electrically programmed are arranged in a matrix,
    Error correction means for reading out data in units of multi-bit data, and correcting the error bits when there are a predetermined number of error bits in the multi-bit data;
    Means for performing a data program in units of the plurality of bit data on the memory cells of the plurality of units, and grasping the number of unprogrammed memory cells after the data programming;
    Means for ending the data program while leaving the non-programmed memory cells remaining when the number of unprogrammed memory cells is within the predetermined number, and causing the error correction means to rescue the error bits; A semiconductor non-volatile memory device.
  3. A semiconductor in which memory program cells are arranged in a matrix so that page program data in units of sectors is transferred to a data latch circuit provided for each bit line, and memory cells in a sector selected in accordance with the data are electrically programmed. A non-volatile storage device,
    Error correction means for reading page data in units of memory cells of a selected sector and correcting the error bit when there is a predetermined number of error bits in the page read data;
    Means for detecting whether or not an unprogrammed memory cell exists for each program operation, wherein a data program according to the page program data is repeatedly performed a plurality of program operations through a verify read operation;
    Means for counting the number of non-programmed memory cells when there are non-programmed memory cells after repeating a predetermined number of program operations;
    Means for ending the data program while leaving the non-programmed memory cells remaining when the number of unprogrammed memory cells is within the predetermined number, and causing the error correction means to rescue the error bits; A semiconductor non-volatile memory device.
  4. 4. The semiconductor nonvolatile memory device according to claim 3, wherein the sector unit is a word line unit.
  5. The error correction means includes means for generating an error checking code from regular data to be programmed;
    A memory array composed of a normal memory array unit for recording the normal data and a parity memory array unit for recording the error check code;
    Means for page-programming the memory array with page program data synthesized by the regular data and the error check code;
    4. The semiconductor nonvolatile memory device according to claim 3, further comprising means for correcting an error bit at the time of data programming based on the read regular data and an error check code when the page program data is read.
  6. The unprogrammed memory cell detecting means sequentially inverts the data latched in the data latch circuit connected to the programmed memory cell for each verify read operation after each program operation to reprogram data. Means for automatic setting;
    4. The semiconductor nonvolatile memory according to claim 3, further comprising: end point detecting means for detecting whether or not there is at least one data latch circuit in which unprogrammed data is latched after the reprogram data is automatically set. Storage device.
  7. The counting means for the non-programmed memory cells reads a page by the operation of a column decoder synchronized with a fixed clock pulse, and sequentially shifts and transfers the page read data to a counting circuit to count the number of unprogrammed data. The semiconductor nonvolatile memory device according to claim 3.
  8. The semiconductor nonvolatile memory device according to claim 3, wherein the memory array in which the memory cells are arranged in a matrix has a NAND structure in which a plurality of memory cells are connected in series.
  9. The memory array in which the memory cells are arranged in a matrix has a NOR structure,
    4. The semiconductor nonvolatile memory device according to claim 3, wherein the main bit line is hierarchized into a plurality of sub bit lines via the operative connection means.
  10. A memory body in which memory cells in which data is electrically programmed are arranged in a matrix;
    Error correction means for reading out data in units of multi-bit data, and correcting the error bits when there are a predetermined number of error bits in the multi-bit data;
    Means for performing a data program in units of the plurality of bit data on the memory cells of the plurality of units, and grasping the number of unprogrammed memory cells after the data programming;
    Means for ending the data program while leaving the non-programmed memory cells remaining when the number of unprogrammed memory cells is within the predetermined number, and causing the error correction means to rescue the error bits; With a memory system.
JP2004281465A 1996-12-03 2004-09-28 Semiconductor nonvolatile memory device and memory system Pending JP2005018983A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008041171A (en) * 2006-08-07 2008-02-21 Fujitsu Ltd Semiconductor memory device changeable of code length of ecc
US7352630B2 (en) 2005-07-26 2008-04-01 Samsung Electronics Co., Ltd. Non-volatile memory device having improved program speed and associated programming method
US7746703B2 (en) 2007-05-25 2010-06-29 Samsung Electronics Co., Ltd. Flash memory device and method of programming flash memory device
JP2011170927A (en) * 2010-02-19 2011-09-01 Toshiba Corp Semiconductor memory device
JP2012069180A (en) * 2010-09-21 2012-04-05 Toshiba Corp Semiconductor storage device
US8661294B2 (en) 2010-01-19 2014-02-25 Samsung Electronics Co., Ltd. Nonvolatile memory device and related program verification circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7352630B2 (en) 2005-07-26 2008-04-01 Samsung Electronics Co., Ltd. Non-volatile memory device having improved program speed and associated programming method
JP2008041171A (en) * 2006-08-07 2008-02-21 Fujitsu Ltd Semiconductor memory device changeable of code length of ecc
US7746703B2 (en) 2007-05-25 2010-06-29 Samsung Electronics Co., Ltd. Flash memory device and method of programming flash memory device
US8661294B2 (en) 2010-01-19 2014-02-25 Samsung Electronics Co., Ltd. Nonvolatile memory device and related program verification circuit
JP2011170927A (en) * 2010-02-19 2011-09-01 Toshiba Corp Semiconductor memory device
JP2012069180A (en) * 2010-09-21 2012-04-05 Toshiba Corp Semiconductor storage device

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