JP2008205268A - Capacitor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor with reduced leak current and enhanced reliability, and to provide a manufacturing method for such a capacitor. <P>SOLUTION: A capacitor 100 includes a lower electrode layer 10, a dielectric layer 20 provided above the lower electrode layer 10, and an upper electrode layer 30 provided above the dielectric layer 20. At least one of the lower electrode layer 10 and the upper electrode layer 30 has a conductive oxide layer provided in contact with the dielectric layer 20 and a metal layer provided at the outer side from the conductive oxide layer relative to the dielectric layer 20. Viewed from a planar surface, a contour of the conductive oxide layer is at the inner side from a contour of the surface on the side where the dielectric layer is in contact with the conductive oxide layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a capacitor and a manufacturing method thereof.

A capacitor generally has a structure in which a dielectric layer made of an inorganic oxide is sandwiched between two electrode layers made of metal. Capacitors having such a structure are used in various electronic devices. For example, a memory element uses dielectric polarization, and a piezoelectric element uses dielectric deformation. The performance of such a capacitor depends on the characteristics of the dielectric layers, the electrodes, and their interfaces. In order to improve the performance of the capacitor, in addition to improving the characteristics of each part, it is necessary to minimize damage to the capacitor during the manufacturing process.
When the capacitor is damaged in the manufacturing process, the leakage current generated between the two electrodes may increase or the reliability may deteriorate due to deterioration of the interface. In particular, in the process of patterning the capacitor by dry etching, the plasma acts directly on the dielectric, so that the damage is large.
JP 2003-243625 A

  According to the inventors' research, it has been found that the increase in leakage current due to the capacitor dry etching mainly occurs along the side surface of the capacitor, that is, the side surface of the dielectric layer. The dielectric near the side surface has a composition shift due to dry etching, the crystallinity is destroyed by ion collision, and the charge in the plasma is injected, etc. This is considered to be the cause of the increase.

  An object of the present invention is to provide a highly reliable capacitor with low leakage current and a method for manufacturing the same.

The capacitor according to the present invention is
A lower electrode layer;
A dielectric layer provided above the lower electrode layer;
An upper electrode layer provided above the dielectric layer;
Including
At least one of the lower electrode layer and the upper electrode layer is
A conductive oxide layer provided in contact with the dielectric layer;
A metal layer provided outside the conductive oxide layer with respect to the dielectric layer;
Have
In plan view, the outline of the conductive oxide layer is on the inner side of the outline of the surface of the dielectric layer on the side in contact with the conductive oxide layer.

  In the present invention, when a specific B layer (hereinafter referred to as “B layer”) provided above a specific A layer (hereinafter referred to as “A layer”), the B layer is directly on the A layer. This includes the case where it is provided and the case where the B layer is provided on the A layer via another layer.

  In the present invention, in a plan view, when the contour of a specific C is inside the contour of a specific D, when C and D are drawn on the same plan view, inside the line indicating the outer periphery of D, It means that all the lines indicating the outer periphery of C exist.

  In such a capacitor, an electric path between at least one of the electrodes and the side surface of the dielectric layer is cut, so that a leakage current is reduced.

The capacitor according to the present invention is
The lower electrode layer and the upper electrode layer are
A conductive oxide layer provided in contact with the dielectric layer;
A metal layer provided outside the conductive oxide layer with respect to the dielectric layer;
Can have.

The capacitor according to the present invention is
An outline of a surface in contact with the dielectric layer of the conductive oxide layer constituting the lower electrode layer;
The outline of the surface of the conductive oxide layer that constitutes the upper electrode layer that is in contact with the dielectric layer may coincide.

  In this way, the regions in contact with the dielectric layers of the upper and lower electrodes are coincident in plan view, so that the dielectric layers existing in the regions other than the regions do not contribute to the function of the capacitor. The reliability of the capacitor is improved.

The capacitor according to the present invention is
The lower electrode layer is
A conductive oxide layer provided in contact with the dielectric layer;
A metal layer provided outside the conductive oxide layer with respect to the dielectric layer;
Have
The contour of the surface of the conductive oxide layer constituting the lower electrode layer that contacts the dielectric layer may coincide with the contour of the surface of the upper electrode layer that contacts the dielectric layer.

The capacitor according to the present invention is
The conductive oxide layer may have a layer made of at least one of an oxide containing La and Ni and an oxide containing Sr and Ru.

The method for manufacturing a capacitor according to the present invention includes:
Forming a lower electrode layer;
Forming a dielectric layer above the lower electrode layer;
Forming an upper electrode layer above the dielectric layer;
Forming a patterned mask layer above the upper electrode layer;
A first etching step of patterning by performing dry etching from the upper electrode layer to at least the upper surface of the lower electrode layer using the mask layer as a mask;
A second etching step for performing wet etching;
Including
At least one of the step of forming the lower electrode layer and the step of forming the upper electrode layer,
Forming a conductive oxide layer in contact with the dielectric layer;
Forming a metal layer outside the conductive oxide layer with respect to the dielectric layer;
Have
The second etching step is a step of performing wet etching on a peripheral portion of the conductive oxide layer.

  According to such a manufacturing method, the capacitor in which the outline of the conductive oxide layer is inside the outline of the surface of the dielectric layer on the side in contact with the conductive oxide layer in a plan view is manufactured. be able to.

The method for manufacturing a capacitor according to the present invention includes:
The step of forming the lower electrode layer and the step of forming the upper electrode layer include:
Forming a conductive oxide layer in contact with the dielectric layer;
Forming a metal layer outside the conductive oxide layer with respect to the dielectric layer;
Can have.

  Preferred embodiments of the present invention will be described below with reference to the drawings. In addition, the following embodiment demonstrates an example of this invention.

1. Capacitor FIG. 1 is a cross-sectional view schematically showing a capacitor 100 according to the present embodiment. FIG. 2 is a plan view schematically showing the capacitor 100 according to the present embodiment. FIG. 3 is a cross-sectional view schematically showing a main part of the capacitor 100 according to the present embodiment.

  Capacitor 100 includes a lower electrode layer 10, a dielectric layer 20, and an upper electrode layer 30.

  The lower electrode layer 10 includes a first metal layer 12 and a first conductive oxide layer 14 formed on the first metal layer 12. Lower electrode layer 10 is paired with upper electrode layer 30 to form capacitor 100. The first metal layer 12 does not necessarily have the same shape as the lower part of the dielectric layer 20. For example, when there is another capacitor next to the capacitor 100, it can be electrically connected so as to be a common lower electrode with the lower electrode of the capacitor. The first metal layer 12 has a function of electrically connecting to the first conductive oxide layer 14 to supplement the conductivity of the first conductive oxide layer 14. The first metal layer 12 has, for example, a single layer or a laminated structure composed of one selected from gold, platinum, nickel, iridium, and alloys thereof.

  The outline of the first conductive oxide layer 14 is the outline of the lower surface of the dielectric layer 20 in plan view (in FIG. 2, the outline of the lower surface of the dielectric layer 20 is equal to the outline of the first metal layer 12). ) Is inside. The first conductive oxide layer 14 may include a layer including at least one of an oxide containing La and Ni (LNO) and an oxide containing Sr and Ru (SRO). The material of the first conductive oxide layer 14 is more preferably LNO.

  The dielectric layer 20 is provided between the lower electrode layer 10 and the upper electrode layer 30. The dielectric layer 20 has an upper surface area smaller than the lower surface area. As shown in FIGS. 1 and 3, the region 22 on the side surface of the dielectric layer 20 is formed in a tapered shape. In the drawing, the inclination of the taper is exaggerated. As shown in FIG. 3, there is a region 21 that is not in contact with the lower electrode layer 10 at the periphery of the lower surface of the dielectric layer 20. Similarly, there is a region 23 that is not in contact with the upper electrode layer 30 at the peripheral edge of the upper surface of the dielectric layer 20.

  For the dielectric layer 20, lead zirconate titanate (PZT) containing Pb, Zr, and Ti as constituent elements can be suitably used. In addition, for the dielectric layer 30, lead zirconate titanate niobate (PZTN) in which PZT is further doped with Nb can be suitably used.

  The upper electrode layer 30 includes a second conductive oxide layer 34 and a second metal layer 32 formed on the second conductive oxide layer 34. Upper electrode layer 30 is paired with lower electrode layer 10 to form capacitor 100.

  The second metal layer 32 has a function of electrically connecting to the second conductive oxide layer 34 to supplement the conductivity of the second conductive oxide layer 34. The second metal layer 32 has, for example, a single layer or a laminated structure composed of one selected from gold, platinum, nickel, iridium, and alloys thereof.

  The outline of the second conductive oxide layer 34 is the outline of the upper surface of the dielectric layer 20 in plan view (the outline of the upper surface of the dielectric layer 20 in FIG. 2 is equal to the outline of the second metal layer 32). ) Is inside. The second conductive oxide layer 34 may have at least one layer of an oxide containing La and Ni and an oxide containing Sr and Ru. The material of the first conductive oxide layer 14 preferably includes at least one of LNO and SRO. The material of the first conductive oxide layer 14 is more preferably LNO.

2. Capacitor Manufacturing Method FIGS. 4 to 6 are cross-sectional views schematically showing manufacturing steps of the capacitor 100 shown in FIG. FIG. 7 is a cross-sectional view schematically showing a part of the manufacturing process of the capacitor 100 shown in FIG. 4 to 7 show the base 1 for the purpose of explanation.

  First, as shown in FIG. 4, the first metal layer 12a, the first conductive oxide layer 14a, the dielectric layer 20a, the second conductive oxide layer 34a, and the second metal layer 12a are sequentially formed on the base 1 from the bottom. The metal layer 32a is laminated. A mask layer 40 patterned into a predetermined shape is formed thereon.

  The substrate 1 can be a diaphragm when the capacitor 100 is used in a piezoelectric device, and can be an interlayer insulating layer or a wiring layer when the capacitor 100 is used in a memory device.

  The first metal layer 12a is formed on the substrate 1 by a method such as sputtering, vacuum deposition, or CVD (Chemical Vapor Deposition). The first conductive oxide layer 14a is formed by a method such as sputtering, vacuum deposition, or CVD. The dielectric layer 20a is formed by a method such as a sol-gel method or CVD. The second conductive oxide layer 34a is formed by a method such as sputtering, vacuum deposition, or CVD. The second metal layer 32a is formed by a method such as sputtering, vacuum deposition, or CVD. The mask layer 40 is patterned by a known method such as photolithography using a photoresist.

Next, as shown in FIG. 5, a first etching process is performed in which dry etching is performed from the upper electrode layer 30 to at least the upper surface of the lower electrode layer 10 using the mask layer 40 as a mask. FIG. 6 shows a state in which the lower electrode layer 10 has been dry etched. The dry etching in the first etching step can be performed by an etching apparatus that generates high-density plasma such as ICP (Inductively Coupled Plasma). For example, the upper electrode layer 30 and the lower electrode layer 10 can be dry-etched with a mixed gas of chlorine and argon at a low pressure of 1.0 Pa or less and a bias of a high bias power of 400 W or more. The dielectric layer 20 is made of a mixed gas of a chlorine-based gas (for example, BCl ₃ or Cl ₂ ) and a fluorine-based gas (for example, CF ₄ or C ₄ F ₈ ) with the same dry etching apparatus as the electrode layer. Dry etching can be suitably performed with a low pressure of 0 Pa or less and a high bias power of 400 W or more. In this step, as shown in FIG. 7, at least a part of the lower electrode layer 10 may be left by dry etching to the upper surface of the lower electrode layer 10. In this case, the lower electrode layer 10 can be a wiring electrically connected to an adjacent capacitor or the like.

  Next, as shown in FIGS. 6 and 7, the mask layer 40 is removed. The removal of the mask layer 40 can be performed by a known method such as an ashing process using oxygen plasma.

  Next, as shown in FIG. 1 and FIG. 8, the outlines of the first conductive oxide layer 14 and the second conductive oxide layer 34 in the plan view are the conductive oxide layers (14, 14) of the dielectric layer 20. 34) A second etching step of performing wet etching is performed so as to be inside the contour of the surface on the side in contact with 34). In the second etching step, the first conductive oxide layer 14 and the second conductive oxide layer 34 are finally etched from the side surfaces. As the etchant used in the second etching step, an etchant having an etching rate with respect to the material of the conductive oxide layer higher than that with respect to the material constituting the other member may be used. For example, when LNO is used for each member, one selected from a hydrogen fluoride aqueous solution, a hexafluorosilicic acid aqueous solution, a hydrochloric acid aqueous solution, a nitric acid aqueous solution, or a mixture thereof can be used. Thus, the conductive oxide layer (14, 34) can be removed with almost no damage to the dielectric layer 20. The etching rate can be performed by changing the composition and thickness of the conductive inorganic oxide and the composition of the etchant. As the thickness of the layer is smaller, the etchant is less likely to diffuse during etching, and the etching rate decreases. Therefore, for example, even with conductive oxide layers having the same composition, the etching rate can be changed depending on the layer thickness.

  Through the second etching step, the lower electrode layer 10 and the upper electrode layer 30 are partially removed from the conductive oxide layer on the dielectric layer 20 side. Thereby, in a plan view, the contour of the upper surface of the lower electrode layer 10 is inside the contour of the lower surface of the dielectric layer 20, and the contour of the lower surface of the upper electrode layer 30 is more than the contour of the upper surface of the dielectric layer 20. Become inside. As a result, the capacitor 100 has a shape in which the peripheral portions of the upper and lower electrodes are not in contact with the dielectric layer 20 as shown in FIGS. 1 to 3, and the lower and upper peripheral regions of the dielectric layer 20 are exposed.

  The formation method of the region 21 and the region 23 of the dielectric layer 20 exposed in this step is different from the region 22 on the side surface of the dielectric layer (FIG. 3). That is, the region 21 and the region 23 are selectively formed by wet etching, while the region 22 is formed by dry etching. Therefore, the region 21 and the region 23 are less damaged than the region 22.

  As described above, according to the method for manufacturing the capacitor 100 of the present embodiment, the capacitor 100 can be obtained by a simple process.

  The capacitor 100 of this embodiment has the following characteristics.

  In the capacitor 100 of this embodiment, a region 21 that is not in contact with the electrode on the lower surface of the dielectric layer 20 and a region 23 that is not in contact with the electrode on the upper surface of the dielectric layer 20 are formed. The region 21 and the region 23 are regions with little damage and have little conductivity. Therefore, the lower electrode layer 10 and the upper electrode layer 30 are not electrically connected to the region 22 on the side surface of the dielectric layer by the region 21 and the region 23, and a path where leakage current is generated is blocked. Thereby, the leakage current of the capacitor 100 is suppressed.

  Further, the region 22 on the side surface of the dielectric layer 20 of the capacitor 100 of this embodiment can function as a protective film itself. That is, the dielectric in the vicinity of the region 22 on the side surface of the dielectric layer 20 has a function of blocking impurities from outside the capacitor system and protecting the internal dielectric. Therefore, deterioration of the dielectric inside the dielectric layer 20 is suppressed, and the reliability of the capacitor 100 is improved.

3. Modifications The present invention is not limited to that described in the above embodiment, and various modifications can be made. Hereinafter, modified examples will be described, but description of components that are substantially the same as the configuration of the capacitor 100 described above will be omitted.

  9 and 11 are cross-sectional views schematically showing modifications of the capacitor 100. FIG. 10 and 12 are plan views schematically showing modifications of the capacitor 100. FIG.

  Capacitor 100 can have a conductive oxide layer on one of lower electrode layer 10 and upper electrode layer 30. And the other electrode layer can be comprised only with a metal layer. 9 and 10 show a modification in which the upper electrode layer 30 has a conductive oxide layer 34 and the lower electrode layer 10 is composed only of the metal layer 12. 11 and 12 show a modification in which the lower electrode layer 10 has the conductive oxide layer 14 and the upper electrode layer 30 is composed of only the metal layer 32. Even in this case, either the region 21 not in contact with the lower electrode layer 10 or the region 23 not in contact with the upper electrode layer 30 is formed on the lower surface or the upper surface of the dielectric layer 20. The region is a region with little damage and has almost no conductivity. Therefore, according to the region, any one of the lower electrode layer 10 and the upper electrode layer 30 is not electrically connected to the region 22 on the side surface of the dielectric layer, and a path through which a leakage current flows is blocked. Even if such a modification is performed, the capacitor 100 has a small leakage current.

  FIG. 13 is a cross-sectional view schematically showing a modified example of the capacitor 100. FIG. 14 is a plan view schematically showing another modification.

  Capacitor 100 can match the contour of first conductive oxide layer 14 and the contour of second conductive oxide layer 34 in plan view. Such deformation of the capacitor 100 can be performed, for example, by changing the etching rate by changing the thickness of the conductive oxide layer.

  When such deformation is performed, the dielectric existing in the peripheral region 24 of the dielectric layer 20 formed in a tapered shape does not contribute to the function of the capacitor 100. Thereby, when using as a piezoelectric capacitor, the distortion produced in the area | region 24 becomes small. Further, when used as a dielectric capacitor, the charge accumulated in the region 24 is reduced, so that the reliability of the capacitor 100 is further improved.

  The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. In addition, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

1 is a cross-sectional view schematically showing a capacitor 100 according to the present invention. The top view which shows typically the capacitor 100 concerning this invention. Sectional drawing which shows typically the principal part of the capacitor 100 concerning this invention. Sectional drawing which shows a part of manufacturing process of the capacitor of this invention typically. Sectional drawing which shows a part of manufacturing process of the capacitor of this invention typically. Sectional drawing which shows a part of manufacturing process of the capacitor of this invention typically. Sectional drawing which shows a part of manufacturing process of the capacitor of this invention typically. 1 is a cross-sectional view schematically showing a capacitor 100 according to the present invention. Sectional drawing which shows the modification of the capacitor 100 concerning this invention typically. The top view which shows typically the modification of the capacitor 100 concerning this invention. Sectional drawing which shows the modification of the capacitor 100 concerning this invention typically. The top view which shows typically the modification of the capacitor 100 concerning this invention. Sectional drawing which shows the modification of the capacitor 100 concerning this invention typically. The top view which shows typically the modification of the capacitor 100 concerning this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Base | substrate, 10 Upper electrode layer, 12 1st metal layer, 14 1st electroconductive oxide layer,
20 dielectric layer, 21-24 region, 30 upper electrode layer, 32 first metal layer,
34 first conductive oxide layer, 40 mask layer, 100 capacitor

Claims (7)

A lower electrode layer;
A dielectric layer provided above the lower electrode layer;
An upper electrode layer provided above the dielectric layer;
Including
At least one of the lower electrode layer and the upper electrode layer is
A conductive oxide layer provided in contact with the dielectric layer;
A metal layer provided outside the conductive oxide layer with respect to the dielectric layer;
Have
In a plan view, the outline of the conductive oxide layer is inside the outline of the surface of the dielectric layer on the side in contact with the conductive oxide layer. In claim 1,
The lower electrode layer and the upper electrode layer are:
A conductive oxide layer provided in contact with the dielectric layer;
A metal layer provided outside the conductive oxide layer with respect to the dielectric layer;
A capacitor. In claim 2,
An outline of a surface in contact with the dielectric layer of the conductive oxide layer constituting the lower electrode layer;
A capacitor, wherein an outline of a surface of the conductive oxide layer constituting the upper electrode layer that is in contact with the dielectric layer is matched. In claim 1,
The lower electrode layer is
A conductive oxide layer provided in contact with the dielectric layer;
A metal layer provided outside the conductive oxide layer with respect to the dielectric layer;
Have
An outline of a surface in contact with the dielectric layer of the conductive oxide layer constituting the lower electrode layer;
A capacitor in which a contour of a surface of the upper electrode layer in contact with the dielectric layer coincides. In any one of Claim 1 thru | or 4,
The capacitor, wherein the conductive oxide layer includes a layer made of at least one of an oxide containing La and Ni and an oxide containing Sr and Ru. Forming a lower electrode layer;
Forming a dielectric layer above the lower electrode layer;
Forming an upper electrode layer above the dielectric layer;
Forming a patterned mask layer above the upper electrode layer;
A first etching step of patterning by performing dry etching from the upper electrode layer to at least the upper surface of the lower electrode layer using the mask layer as a mask;
A second etching step for performing wet etching;
Including
At least one of the step of forming the lower electrode layer and the step of forming the upper electrode layer,
Forming a conductive oxide layer in contact with the dielectric layer;
Forming a metal layer outside the conductive oxide layer with respect to the dielectric layer;
Have
The method of manufacturing a capacitor, wherein the second etching step is a step of performing wet etching on a peripheral portion of the conductive oxide layer. In claim 6,
The step of forming the lower electrode layer and the step of forming the upper electrode layer include:
Forming a conductive oxide layer in contact with the dielectric layer;
Forming a metal layer outside the conductive oxide layer with respect to the dielectric layer;
A method for manufacturing a capacitor.

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