TWI752377B - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A method of manufacturing a semiconductor device includes the following steps. A plurality of first via are formed in the first dielectric layer in the memory cell region and the peripheral region. A surface treatment is performed on the plurality of first via to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layer are formed in the recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second via are formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first via in the peripheral region respectively.

Description

Semiconductor element and method of manufacturing the same

The present invention relates to an integrated circuit and a manufacturing method thereof, and more particularly, to a semiconductor device and a manufacturing method thereof.

With the advancement of technology, all kinds of electronic products are developing towards the trend of high speed, high performance, and light, thin and short size. How to effectively utilize the chip area and improve the yield is a very important topic at present.

The development of resistive memory (such as resistive random access memory (RRAM)) has been extremely rapid in recent years, and it is the structure of the future memory that attracts the most attention. Due to the potential advantages of low power consumption, high-speed operation, high density, and compatibility with complementary metal-oxide-semiconductor (CMOS) process technology, resistive memory is very suitable for the next generation of non-volatile memory devices.

However, during the etching process for forming the memory element, the vias located in the peripheral region will be over-etched, resulting in exposed gaps in the vias, and the slurry of the subsequent chemical mechanical polishing process will remain in the gaps, resulting in The contact resistance is too high, or even the subsequently formed vias cannot contact them.

Embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, which can avoid problems such as high contact resistance or failure of normal contact between vias.

An embodiment of the present invention provides a method for manufacturing a semiconductor element, which includes the following steps. A plurality of first vias are formed in the first dielectric layer in the memory cell region and the peripheral region. Surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of grooves. A memory element is formed on the first dielectric layer of the memory cell region. A second dielectric layer is formed on the memory element and on the first dielectric layer. forming a plurality of second vias in the memory cell region and the second dielectric layer in the peripheral region to electrically connect the memory elements in the memory cell region and the memory elements in the memory cell region respectively the first via in the peripheral region.

An embodiment of the present invention provides a semiconductor device including a plurality of first vias, respectively in the first dielectric layer in the memory cell region and the peripheral region; a plurality of protective layers embedded in the plurality of first vias a memory element on the protective layer and the first dielectric layer in the memory cell region; a second dielectric layer on the memory element and on the first dielectric layer; and A plurality of second vias are located in the second dielectric layer in the memory cell region and the peripheral region. The second via in the memory cell region is electrically connected to the memory element, and the second via in the peripheral region is electrically connected to the first via through the protective layer sexual connection.

Based on the above, the semiconductor device and the manufacturing method thereof according to the embodiments of the present invention can increase the process margin by forming the protective layer, avoid problems such as excessive contact resistance or normal contact between the vias, and can reduce the size of the memory device. spacing between.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Referring to FIG. 1A , vias 108 and 109 connected to the conductor layer 100 are formed in the dielectric layer 102 of the memory cell region 10A and the peripheral region 10B, respectively. The dielectric layer 102 may be a single layer or a multi-layered layer, which may include silicon oxide, silicon nitride or a combination thereof, and the dielectric layer 102 is a planarized layer by a planarization process. The conductor layer 100 is, for example, any metal layer (conductor layer) of the metal interconnect structure formed on the substrate, for example, the first metal layer closest to the substrate. The substrate may be a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. The metal layer is, for example, tungsten, aluminum, copper or a combination thereof formed by physical vapor deposition. Other elements, such as transistors, may be included between the substrate and the metal layer.

Vias 108 and 109 may include barrier layers 104 and plugs 106, respectively. The barrier layer 104 and the plug 106 may be formed by, for example, forming a via opening (not shown) in the dielectric layer 102 first. After that, a barrier material layer is conformally formed on the dielectric layer 102 and the opening of the via, and then, the conductor layer is filled into the opening of the via. After that, a chemical mechanical polishing process or an etch-back process is performed to remove the barrier material layer and the conductor layer on the dielectric layer 102 . The material of the barrier layer 104 can be, for example, tungsten nitride, titanium nitride, tantalum nitride or a combination thereof, and the formation method thereof is, for example, chemical vapor deposition. The material of the plug 106 includes a metallic material. The metal material may be, for example, tungsten, and the formation method may be, for example, chemical vapor deposition. Although the memory cell area 10A in FIG. 1A only shows two vias, and the peripheral area 10B only shows one via, the invention is not limited to this, and in other embodiments, the number of vias can be determined according to requirements to make adjustments.

Referring to FIGS. 1A and 1B , a surface treatment process 105 is performed to react the surface of the plug 106 to form a sacrificial layer 107 . The treatment process 105 is, for example, an oxidation process. In one embodiment, the oxidation process may be a wet oxidation process. The wet oxidation process can use an aqueous solution of sulfuric acid and hydrogen peroxide or an aqueous solution of phosphoric acid as an oxidant. When the treatment process 105 is an oxidation process, the sacrificial layer 107 is a metal oxide, such as tungsten oxide.

Referring to FIGS. 1B and 1C, an etching process is performed to remove the sacrificial layer 107 and expose the plug 106a. The plug 106a and the barrier layer 104 form the recess 110 . The depth T1 of the groove 110 is, for example, 40 nm to 100 nm. The etching process is, for example, a wet etching process. When the sacrificial layer 107 is a metal oxide, ammonia water can be used as an etchant.

Referring to FIGS. 1C and 1D , a protective layer 112 is formed in the groove 110 . The material of the protective layer 112 is different from that of the plug 106a. The material of the protective layer 112 includes a conductor material. The conductor material is, for example, tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), platinum (Pt), aluminum (Al), or the like formed by physical vapor deposition or chemical vapor deposition. combination. The protective layer 112 is formed by, for example, forming a protective material layer on the dielectric layer 102 and the groove 110 , and then planarizing by chemical mechanical polishing (CMP) process or etch back to remove the dielectric layer 102 . layer of protective material. The top surface of protective layer 112 may be coplanar with the top surface of dielectric layer 102 . During the planarization process, the protective layer 112 can protect the plugs 106a underneath, so that the etching solution or slurry used in the planarization process can be prevented from flowing into the gaps of the plugs 106a.

Next, the first electrode layer 114 , the variable resistance layer 118 , the second electrode layer 120 and the cap layer 122 are sequentially formed on the dielectric layer 102 and the protective layer 112 . Materials of the first electrode layer 114 and the second electrode layer 120 may include metals and metal nitrides. Materials of the first electrode layer 114 and the second electrode layer 120 include titanium nitride (TiN), platinum (Pt), iridium (Ir), ruthenium (Ru), titanium (Ti), tungsten (W), and tantalum (Ta) , aluminum (Al), zirconium (Zr), hafnium (Hf), nickel (Ni), copper (Cu), cobalt (Co), iron (Fe), gadolinium (Y), manganese (Mo) or a combination thereof, which The formation method may be, for example, a physical vapor deposition method or a chemical vapor deposition method. The first electrode layer 114 and the second electrode layer 120 may be a single layer or multiple layers. In some embodiments, the second electrode layer 120 may further include one or more barrier layers. The material of the barrier layer includes metal oxides, such as titanium oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof. The barrier layer can prevent the non-uniformity of the conductive filaments caused by the larger current flowing through the second electrode when setting or resetting.

The material of the variable resistance layer 118 may include metal oxides, such as hafnium oxide (for example, HfO or HfO _{2 ,} etc.), lanthanum oxide, gadolinium oxide, yttrium oxide, zirconium oxide, titanium oxide, tantalum oxide, nickel oxide, oxide Tungsten, copper oxide, cobalt oxide, iron oxide, aluminum oxide, or a combination thereof, for example, a chemical vapor deposition method. The thickness T2 of the variable resistance layer 118 is greater than the thickness T1 of the protective layer 112 . When the thickness T1 is, for example, 40 nm to 100 nm, the thickness T2 is, for example, 50 nm to 120 nm. The cap layer 122 can protect the second electrode layer 120 from being damaged by plasma in the subsequent etching process. In addition, the cap layer 122 can also be used as an anti-reflection layer in the subsequent lithography process. The material of the capping layer 122 is, for example, silicon oxynitride, silicon nitride or a combination thereof formed by chemical vapor deposition. The cap layer 122 may be a single layer or a multi-layer.

Referring to FIG. 1E, lithography and etching processes are performed to pattern the capping layer 122 and the second electrode layer 120 to form the capping layer 122a and the second electrode 120a in the memory cell region 10A. The etching process includes an anisotropic etching process, such as a reactive ion etching process. The etching gas used in the reactive ion etching process is, for example, methane, boron trichloride (BCl ₃ ), carbon tetrafluoride (CF ₄ ), trifluoromethane (CHF ₃ ) or a combination thereof. The capping layer 122a and the second electrode 120a have substantially vertical sidewalls, and the capping layer 122a has a dome.

Referring to FIG. 1F , the etching process is continued to pattern the variable resistance layer 118 and the first electrode layer 114 to form the variable resistance layer 118 a and the first electrode 114 a in the memory cell region 10A. Due to the difference in etching characteristics, the variable resistance layer 118a and the first electrode 114a both have inclined sidewalls. In addition, during the etching process, over-etching is performed to ensure that the first electrodes 114a of adjacent memory cells in the memory cell region 10A can be completely separated, so part of the dielectric layer 102 may also be etched. Since the material of the protective layer 112 is different from that of the variable resistance layer 118 and the first electrode layer 114, and the etching rate is different, the protective layer 112 in the peripheral region 10B can protect the plug 106a below and prevent the plug 106a from being etched of destruction. Therefore, the process window can be increased by the formation of the protective layer 112 .

In some embodiments, the first electrode 114 a , the variable resistance layer 118 a , the second electrode 120 a and the cap layer 122 a in the memory cell region 10A constitute the memory cell 50 . In other embodiments, the protective layer 112 in the memory cell region 10A can also be regarded as a part of the memory cell 50 . The second electrode 120 a serves as the upper electrode 120 a of the memory element 50 , and the protective layer 112 and the first electrode 114 a in the memory cell region 10A can be collectively regarded as the lower electrode 116 of the memory element 50 .

Referring to FIG. 1G , a barrier layer 124 and a dielectric layer 126 are formed in the memory cell region 10A and the peripheral region 10B. The material of the barrier layer 124 includes metal oxides, such as hafnium oxide, lanthanum oxide, gium oxide, yttrium oxide, zirconium oxide, titanium oxide, tantalum oxide, nickel oxide, tungsten oxide, copper oxide, cobalt oxide, iron oxide, oxide Aluminum, or a combination thereof, may be formed by, for example, atomic layer deposition or chemical vapor deposition. The material of the dielectric layer 126 may include silicon oxide, silicon nitride or a combination thereof, and the formation method thereof may be, for example, chemical vapor deposition. Dielectric layer 126 may be a single layer or multiple layers. The material of the dielectric layer 126 may include silicon oxide, silicon nitride or a combination thereof, and the formation method thereof may be, for example, chemical vapor deposition. The dielectric layer 126 may be a planar layer planarized by a CMP process.

Referring to FIG. 1H , lithography and etching processes are performed to remove part of the dielectric layer 126 , the barrier layer 124 , and the cap layer 122 a in the memory cell region 10A to form a via opening exposing the second electrode 120 a 128. In addition, portions of the dielectric layer 126 , the barrier layer 124 and the protective layer 112 in the peripheral region 10B are also removed to form via openings 130 exposing the plugs 106a.

During the etching process, since the material of the cap layer 122 is different from the material of the dielectric layer 126 and has a lower etching rate, the cap layer 122 can be used as an etch stop layer. After the protective layer 112 of the peripheral region 10B is exposed, the cap layer 122 in the memory cell region 10A is removed. After that, the protective layer 112 of the peripheral region 10B is removed. In the process of removing the protective layer 112 in the peripheral region 10B, even though part of the second electrode 120a is etched, since the thickness T2 of the second electrode 120a is greater than the thickness T1 of the protective layer 112 in the peripheral region 10B, when the peripheral After the protective layer 112 of the region 10B is completely removed, a sufficient thickness of the second electrode 120a remains.

Referring to FIG. 1I, vias 136 and 138 are formed in the via openings 128 and 130, respectively. Vias 136 and 138 may include barrier layers 132 and plugs 134, respectively. The formation method of the barrier layer 132 and the plug 134 may be, for example, to form a barrier material layer conformally on the dielectric layer 126 and the via openings 128 and 130 first, and then to form the conductor layer. After that, a chemical mechanical polishing process or an etch-back process is performed to remove the barrier material layer and the conductor layer on the dielectric layer 126 . The material of the barrier material layer can be, for example, tungsten nitride, titanium nitride, tantalum nitride or a combination thereof, and the formation method thereof is, for example, chemical vapor deposition. The material of the conductor layer includes a metal material, and the metal material may be, for example, tungsten, and the formation method thereof may be, for example, a chemical vapor deposition method.

Thereafter, a dielectric layer and metal features electrically connected to vias 136 and 138, respectively, may be formed on dielectric layer 126 . The metal feature is part of the metal interconnect structure, which may be a metal layer, such as a second metal layer.

In this embodiment, the via 136 is electrically connected to and in physical contact with the second electrode 120a. The via 138 passes through the dielectric layer 126 and extends into the dielectric layer 102 , and is electrically connected to and in physical contact with the via 109 . The variable resistance layer 118 and the first electrode 114a have inclined sidewalls. The bottom area of the variable resistance layer 118 is substantially the same as the top area of the first electrode 114a.

The first electrode 114a covers the protective layer 112 , the barrier layer 104 and a part of the dielectric layer 102 and is in physical contact therewith. The protective layer 112 is embedded in the via 108 and is in physical contact with the plug 106 and the barrier layer 104 of the via 108 and is surrounded by the plug 106 and the barrier layer 104 of the via 108 .

Referring to FIG. 2A , this embodiment is very similar to the first embodiment. According to the method of the first embodiment, after the dielectric layer 126 ( FIG. 1G ) is formed, via layers are respectively formed in the memory cell region 10A and the peripheral region 10B Window openings 128 and 130a. The via opening 128 passes through the dielectric layer 126 , the barrier layer 124 and the capping layer 122a to expose the second electrode 120a. The via opening 130a exposes the protective layer 112 . In other words, in the process of forming the via openings 128 and 130a, the protective layer 112 in the peripheral region 10B is retained without being removed by etching.

Referring to FIG. 2B , vias 136 and 138a are formed in the via openings 128 and 130a, respectively, according to the method of the above-mentioned embodiment. Vias 136 and 138a may include barrier layers 132 and plugs 134, respectively. The via 136 is electrically connected to and in physical contact with the second electrode 120a. The via 138 a is not in physical contact with the via 109 , but is electrically connected through the protective layer 112 . The protective layer 112 is embedded in the via 109 . The protective layer 112 is in physical contact with the plug 106 of the via 109 and the barrier layer 104 and is surrounded by the plug 106 and the barrier layer 104 of the via 109 .

Referring to FIG. 3 , this embodiment is very similar to the first embodiment. According to the method of the first embodiment, after the protective layer 112 is formed in the groove 110 , the first electrode layer 114 is not formed, and the variable resistor is directly formed layer 118, second electrode layer 120, and capping layer 122 (FIGS. 1C, 1D). Thereafter, the method of the first embodiment is followed until vias 136 and 138 are formed.

The structure of the semiconductor element of this embodiment is very similar to the structure of the semiconductor element of the first embodiment, the difference is that in this embodiment, the protective layer 112 in the memory cell region 10A is used as the first electrode of the memory element (or lower electrode). Therefore, the first electrode (protective layer 112 ) of the memory element is in physical contact with the plug 106 and the barrier layer 104 of the via 108 and is surrounded by the plug 106 and the barrier layer 104 of the via 108 . The variable resistance layer 118a has sidewalls inclined toward the second electrode 120a due to the characteristics of etching. In other words, the size of the top surface of the variable resistance layer 118a is smaller than that of the bottom surface.

On the other hand, since the via opening for forming the via 108 may have vertical sidewalls or sidewalls inclined toward the conductor layer 100 . Therefore, the first electrode (protective layer 112 ) may have vertical sidewalls or sidewalls inclined toward the conductor layer 100 . Therefore, the size of the top surface of the first electrode (protective layer 112 ) may be greater than or equal to the size of the bottom surface of the first electrode (protective layer 112 ).

The first electrode (protective layer 112 ) is discontinuous with the sidewall of the variable resistance layer 118a. The top area of the first electrode (protective layer 112 ) is smaller than the bottom area of the variable resistance layer 118 . The first electrode (protective layer 112 ), the barrier layer 104 and a portion of the dielectric layer 102 are covered by the variable resistance layer 118 and are in physical contact therewith.

Since the first electrode (protective layer 112 ) is formed in the via 108 in a damascene manner, and self-aligns the via 108 , it can be regarded as a self-aligned process. In addition, since the first electrode (protective layer 112 ) is formed in a damascene manner, there is no problem that the first electrode is difficult to etch in the manufacturing process. In addition, there is no need to increase the spacing in order to ensure that two adjacent first electrodes may not be disconnected due to their inclined sidewalls. Since the size of the first electrode (protective layer 112 ) is small, the distance between the memory elements can be reduced.

Referring to FIG. 4 , this embodiment is very similar to the third embodiment, and the difference lies in that: in this embodiment, in the process of forming the via opening of the peripheral region 10B, the protective layer 112 is retained instead of being etched remove. Therefore, the structure of the semiconductor element of this embodiment is very similar to the structure of the semiconductor element of the third embodiment, and the difference lies in that the via 138a in this embodiment passes through the dielectric layer 126 and the barrier layer 124, and The protective layer 112 is electrically connected and in physical contact. In other words, the via 138 a and the via 109 are not in physical contact, but are electrically connected through the protective layer 112 .

In the embodiment of the present invention, through the surface treatment process and the etching process, a groove can be formed on the lower via, and a protective layer can be formed in the groove. The formation of the protective layer can prevent the via from being damaged by etching and increase the process margin.

Furthermore, in some embodiments, the protective layer can be completely removed, so that there is a good contact between the upper-layer via formed in the peripheral area and the lower-layer via, and the contact resistance is too high or normal contact is avoided. And other issues.

In addition, in other embodiments, the protective layer can be left behind and directly used as the first electrode of the memory element. Since the protective layer can be self-aligned to the underlying via, no additional mask is required, so the process steps can be reduced. with cost. On the other hand, since the size of the protective layer serving as the first electrode is small, the distance between the memory elements can be reduced.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10A: Memory cell area 10B: Surrounding area 50: Memory unit 100: Conductor layer 102, 126: Dielectric layer 104, 124, 132: Barrier layer 105: Surface treatment process 106, 106a, 134: Plug 107: Sacrificial Layer 108, 109, 136, 138, 138a: Vias 110: Groove 112: Protective layer 114: the first electrode layer 114a: first electrode 116: Lower electrode 118, 118a: variable resistance layer 120: the second electrode layer 120a: second electrode/upper electrode 122, 122a: top cover layer 128, 130, 130a: Via opening T1: Depth/Thickness T2: Thickness

1A to 1I are schematic cross-sectional views of a manufacturing process of a semiconductor device according to a first embodiment of the present invention. 2A to 2B are schematic cross-sectional views of a manufacturing process of a semiconductor device according to a second embodiment of the present invention. 3 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention. 4 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

10A: Memory cell area

10B: Surrounding area

100: Conductor layer

102: Dielectric layer

104: Barrier Layer

105: Surface treatment process

106: Plug

108: Via

109: Via

Claims (9)

A method of manufacturing a semiconductor device, comprising: forming a plurality of first vias in a first dielectric layer in a memory cell region and a peripheral region; and performing surface treatment on the plurality of first vias to form a plurality of first vias. a plurality of sacrificial layers; removing the plurality of sacrificial layers to form a plurality of grooves; forming a plurality of protective layers in the plurality of grooves; forming on the first dielectric layer of the memory cell region memory element; forming a second dielectric layer on the memory element and on the first dielectric layer; forming a plurality of second vias, in the memory cell region and the peripheral region in the first two dielectric layers to electrically connect the memory element in the memory cell region and the first via in the peripheral region respectively; and before forming the second via The protective layer is removed in the peripheral region, wherein the second via in the peripheral region is in physical contact with the first via. The method for manufacturing a semiconductor element according to claim 1, wherein forming the memory element comprises: forming a first electrode layer, a variable resistance layer, a first electrode layer, a variable resistance layer, a two electrode layers and a capping layer; and patterning the capping layer, the second electrode layer, the variable resistance layer and the first electrode layer to form the memory contacting the protective layer element. The method for manufacturing a semiconductor element according to claim 1, wherein forming the memory element comprises: using the protective layer as a first electrode layer; forming a variable resistance layer, a second electrode layer on the protective layer an electrode layer and a capping layer; and patterning the second electrode layer, the variable resistance layer and the first electrode layer to form the memory element in contact with the first via. The method for manufacturing a semiconductor device according to claim 1, wherein the second via and the first via in the peripheral region are electrically connected through the protective layer. A semiconductor device, comprising: a plurality of first vias, respectively in a first dielectric layer in a memory cell region and a peripheral region; a plurality of protective layers embedded in the plurality of first vias; and a memory element located on the protective layer and the first dielectric layer in the memory cell region; a second dielectric layer located on the memory element and the first dielectric layer; and a plurality of first dielectric layers Two vias located in the second dielectric layer in the memory cell region and the peripheral region, wherein the second via in the memory cell region is electrically connected to the memory element, The second via in the peripheral region is electrically connected to the first via through the protective layer, The second via in the peripheral region passes through the first dielectric layer and extends into the first dielectric layer, and is electrically connected and physically in contact with the first via. The semiconductor device according to claim 5, wherein a material of the protective layer includes a conductor material different from that of the plurality of first vias. The semiconductor device according to claim 5, wherein the protective layer is used as the first electrode of the memory device. The semiconductor element of claim 5, wherein the protective layer is in contact with the first electrode of the memory element. The semiconductor element according to claim 7 or 8, wherein the thickness of the protective layer is smaller than the thickness of the second electrode of the memory element.

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