KR100781546B1 - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided to prevent damage of a dielectric of a capacitor by bypassing electrons being piled on a plate electrode. A field region and an active region are divided on a semiconductor substrate(100) by an isolation layer(102). Cell transistors are formed on a cell region of the semiconductor substrate. Peripheral circuit transistors are formed on peripheral circuit transistors of the semiconductor substrate. A first interlayer dielectric(110) including a contact pad(112) is located on the semiconductor substrate. A gate electrode is formed between the contact pads. The contact pad is electrically connected to an impurity region formed in the semiconductor substrate. The contact pad electrically connects the impurity region to an upper bit line(132) and a storage node electrode(142). A second interlayer dielectric(120) is formed on the first interlayer dielectric. The bit line of the cell region and a wire(131) of the peripheral circuit region are located on the second interlayer dielectric. A lower gate electrode is insulated with the bit line and the wire by the second interlayer dielectric.

Description

Semiconductor device and method for fabricating the same

1 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

2 to 4 are cross-sectional views of a sequential semiconductor memory device manufacturing process according to FIG. 1.

5A and 5B are a plan view and a cross-sectional view of an element of a dummy capacitor according to another embodiment of the present invention.

6 is a plan view of a dummy capacitor according to still another embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100: semiconductor substrate 102: device isolation film

110: first interlayer insulating film 112: contact pad

120: second interlayer insulating film 130: third interlayer insulating film

132: bit line 134: storage node contact plug

142: storage node electrode 144: dielectric film

146: plate electrode 150: capacitor

151: dummy capacitor 152: sacrificial dummy storage node electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device of a dummy capacitor and a method of manufacturing the same for preventing damage to a dielectric film.

As the manufacturing technology of semiconductor devices has developed, the size of transistors has become smaller and the degree of integration of semiconductor memory devices has increased. In particular, in the case of DRAM, the area of a memory cell is rapidly reduced as the degree of integration increases.

The DRAM consists of one transistor and one capacitor, and as the area of the semiconductor device decreases, the height of the device increases (eg, a capacitor) to improve the DRAM device performance, thereby increasing the thickness of the interlayer insulating film for insulating the device and the device. Is increased. In forming a contact hole exposing a lower conductive layer in such a thick interlayer insulating film, the value of the etching process parameters may be quite large. As a result, excessive plasma ions, electrons, radicals, etc. are piled up on the plate electrode of the capacitor, thereby stressing the dielectric film of the capacitor. Accordingly, in the case of DRAM devices, when the dielectric film of the capacitor is damaged, the refresh characteristic may be degraded, thereby causing a defect in data storage.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device manufacturing method for forming a capacitor that prevents damage to a dielectric film.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, a semiconductor device includes at least one cell capacitor formed in a cell region and at least one dummy capacitor formed in a dummy cell region, wherein each cell capacitor is stored by a dielectric film. The node electrode and the plate electrode are electrically separated, and each dummy capacitor includes an electrically connected dummy storage node and the plate electrode.

According to another aspect of the present invention, a semiconductor device includes a cell region, a substrate on which a first dummy cell region and a second dummy cell region are defined, and are formed on a cell region. A plurality of first dummy cells formed on the plurality of cells, the first dummy cell region and comprising the cylindrical capacitor; A plurality of second dummy cells formed on a second dummy cell region, the one side of which includes a partial cylindrical capacitor, wherein the dummy storage node electrode and the plate electrode of the partial cylinder type capacitor are electrically connected; It includes.

According to another aspect of the present invention, a semiconductor device includes a MOS transistor and a partial cylindrical capacitor having one side connected to one node of the MOS transistor, wherein the partial cylinder type capacitor is a dummy storage node. It includes that the electrode and the plate electrode is electrically connected.

According to an aspect of the present invention, a method of manufacturing a semiconductor device includes forming a cell storage node electrode in a cell region of a cell block and a dummy storage node electrode in a dummy region on a semiconductor substrate, and forming a cell storage node. Forming a dielectric film on an electrode and an upper surface of the dummy storage node electrode, etching a dielectric film on an upper surface of the dummy storage node electrode, and forming a plate electrode on a semiconductor substrate on which the dielectric film on the upper surface of the dummy storage node electrode is etched to form a cell capacitor and a dummy capacitor It includes forming a.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

A semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 1.

1 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention. In particular, FIG. 1 shows a dummy area of a cell block.

Referring to FIG. 1, the semiconductor substrate 100 is divided into a field region and an active region by the device isolation layer 102. Cell transistors (not shown) are formed in the cell region and peripheral circuit transistors (not shown) are formed in the peripheral circuit region on the semiconductor substrate 100 through a conventional CMOS process. The first interlayer insulating layer 110 including the contact pads 112 is positioned on the semiconductor substrate 100. The contact pad 112 is formed of a conductive material such as polysilicon doped with a high concentration of impurities or a metal material, and is electrically connected to an impurity region (not shown) formed in the semiconductor substrate 100. A gate electrode (not shown) is formed between the contact pads 112. The contact pad 112 may electrically connect the impurity region (not shown), the upper bit line 132, and the storage node electrode 142.

The second interlayer insulating layer 120 is formed on the first interlayer insulating layer 110, and the bit line 132 of the cell region and the wiring 131 of the peripheral circuit region are positioned on the second interlayer insulating layer 120. . The lower gate electrode (not shown), the bit line 132, and the wiring 131 are insulated by the second interlayer insulating layer 120.

Meanwhile, a bit line contact plug (not shown) is formed in the second interlayer insulating layer 120 to electrically connect the bit line 132 and the wiring 131 to an impurity region (not shown) in the semiconductor substrate 100. Can be. The bit line 132 or the wiring 131 is positioned on the bit line contact plug (not shown).

The bit line 132 and the wiring 131 may have a structure in which a diffusion barrier 132a, a metal layer 132b, and an insulating layer 132c are stacked, and spacers 132d are disposed on sidewalls.

As such, the third interlayer insulating layer 130 is positioned on the second interlayer insulating layer 120 on which the bit line 132 and the wiring 131 are formed, and the bit lines are disposed on the second and third interlayer insulating layers 120 and 130. The storage node contact plug 134 is positioned between the 132. The storage node contact plug 134 is connected to the lower contact pad 112 to electrically connect the storage node electrode 142 to an impurity region (not shown).

Here, the storage node contact plug 134 is located between the bit lines 132. Since the upper portion of the storage node contact plug 134 is extended, the contact area with the storage node electrode 142 positioned at the upper portion is increased, and the storage node electrode 142 may be disposed diagonally to increase the degree of integration. .

Subsequently, a storage node electrode 142 of the capacitor 150 and a dummy storage node electrode 142a of the dummy capacitor 151 are formed. The dummy storage node electrode 142a is formed at one edge of a cell block. The storage node electrode 142 and the dummy storage node electrode 142a are in contact with the storage node contact plug 134. The storage node electrode 142 and the dummy storage node electrode 142a are formed of a conductive material such as doped polysilicon.

The dielectric layer 144 is conformally formed along the storage node electrode 142. The dielectric layer 144 is an insulating layer, and electrically insulates the storage node electrode 142 from the plate electrode 146.

In addition, the plate electrode 146 completely covers the cylindrical storage node electrode 142 and the dielectric layer 144. The plate electrode 146 is formed of a conductive material such as doped polysilicon.

 The dummy storage node electrode 142a according to the embodiment of the present invention does not have the dielectric layer 144.

In more detail, unlike the storage node electrode 142 of the capacitor 150, the dummy capacitor 151 has a plate electrode 146 covering the dummy storage node electrode 142a without the dielectric layer 144. Therefore, the dummy storage node electrode 142a forms a dummy capacitor 151 shorted with the plate electrode 146. As a result, the dummy capacitor 151 may be electrically shorted to bypass electrons even when electrons generated by the plasma are piled up on the plate electrode 146 in a subsequent contact hole process. .

That is, in the dummy capacitor 151, the plate electrode 146 formed of the conductive layer and the storage node electrode 142 formed of the conductive layer are directly connected without the dielectric layer 144 and electrically shorted. Thus, the electrons piled up on the plate electrode 146 may be bypassed to the substrate 100 through the shorted dummy capacitor 151 and through the lower storage node contact plug 134 and the contact pad 112. .

Then, a plate contact 172a for connecting with the plate electrode 146 and a wiring contact 172b for connecting with the lower wiring 131 are formed.

An upper wiring 182 is formed on the plate electrode 146 and the fourth interlayer insulating film 171 covering the contacts 172a and 172b to contact the contacts 172a and 172b.

2 to 4 will be described in detail a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

2 to 4 are step-by-step cross-sectional views of a semiconductor memory device manufacturing process according to an embodiment of the present invention.

First, referring to FIG. 2, a gate electrode (not shown) is formed on a semiconductor substrate 100 divided into a field region and an active region by the device isolation layer 102, and semiconductor substrates on both sides of the gate electrode (not shown) are formed. An ion implantation process is performed in 100 to form an impurity region (not shown).

Next, an insulating material is deposited on the semiconductor substrate 100 on which the gate electrode (not shown) and the impurity region (not shown) are formed. Then, the first interlayer insulating layer 110 is formed by planarizing the upper portion by performing a chemical mechanical polishing (CMP) or etch back process.

In addition, a normal photolithography process is performed on the first interlayer insulating layer 110 to form a contact hole exposing impurity regions (not shown) in the semiconductor substrate 100. In the case where the contact hole is formed in the first interlayer insulating layer 110 made of silicon oxide, the contact holes are magnetized relative to the gate electrode (not shown) by using an etching gas having a high etching selectivity with respect to the gate electrode (not shown). While self-aligning, an impurity region (not shown) in the semiconductor substrate 100 is exposed.

Next, a conductive film is formed by depositing a conductive material or a metal material such as polysilicon doped with a high concentration of impurities filling the contact hole on the entire surface of the first interlayer insulating film 110 on which the contact hole is formed. Subsequently, the conductive layer is planarized until the upper portion of the first interlayer insulating layer 110 is exposed to form a self-aligned contact pad 112 in the first interlayer insulating layer 110.

Next, an insulating material is deposited and planarized on the first interlayer insulating layer 110 including the contact pad 112 to form a second interlayer insulating layer 120. Then, a bit line contact hole is formed in the second interlayer insulating layer 120, and a conductive material is deposited and planarized to form a bit line contact plug (not shown) in the second interlayer insulating layer 120. In this case, the bit line contact plug (not shown) is selectively connected to the contact pad 112 located in the first interlayer insulating layer 110.

The wire 131 is formed on the second interlayer insulating layer 120 to connect the plurality of peripheral circuit contacts together with the bit line 132 connected to the bit line contact plug (not shown). In detail, the bit line 132 and the wiring 131 may have a structure in which the diffusion barrier 132a, the metal layer 132b, and the insulating layer 132c are stacked, and spacers 132d are formed on the sidewalls. . In this case, the diffusion barrier 132a may be formed of a titanium / titanium nitride layer (Ti / TiN), and the metal layer 132b may be formed of a tungsten layer (W). The insulating layer 132c and the spacer 132d may be formed of a nitride film. Alternatively, the bit line 132 may be formed of polysilicon doped with a high concentration of impurities instead of the diffusion barrier 132a and the metal layer 132b.

As such, after forming the bit line 132 and the wiring 131 on the second interlayer insulating layer 120, as shown in FIG. 3, the insulating material filling the bit line 132 and the wiring 131 on the front surface thereof. Depositing and planarizing to form a third interlayer insulating film (130).

Thereafter, a normal photolithography process is performed on the second and third interlayer insulating layers 120 and 130 to form contact holes exposing the lower contact pads 112. In this case, an upper portion of the contact hole may be extended to increase a contact area between the storage node contact plug 134 and the storage node electrode 142. Then, the inside of the contact hole is filled with a conductive material or a metal material and planarized to complete the storage node contact plug 134.

Subsequently, the storage node electrode 142 and the dummy storage node electrode 142a which are connected to the storage node contact plug 134 are formed. The storage node electrode 142 and the dummy storage node electrode 142a are formed in a single cylinder using doped polysilicon or the like.

Here, the storage node electrode 142 and the dummy storage node electrode 142a have been described as a single cylinder type, but are not limited thereto. Depending on the configuration and shape of the semiconductor device, the storage electrode may be an OCS or a storage electrode having a stack structure.

3, the dielectric layer 144 is conformally formed along the storage node electrode 142 and the dummy storage node electrode 142a.

The dielectric layer 144 is formed on the entire surface of the substrate 100 on which the storage node electrode 142 and the dummy storage node electrode 142a are formed. The dielectric film 144 may be formed of a single film of a tantalum oxide film Ta2O5 or an aluminum oxide film Al2O3, or a laminated film of a tantalum oxide film / titanium oxide film or an aluminum oxide film / titanium oxide film. In addition, as the dielectric film 144, a laminated film having a high dielectric constant such as oxide-nitride-oxide (ONO) may be used.

Next, FIG. 4 etches the dielectric layer 144 of the dummy storage node electrode 142a according to an embodiment of the present invention.

The photoresist film PR is formed to expose only the dummy storage node electrode 142a. The dielectric layer 144 on the dummy storage node electrode 142a is etched through the etching process. The etching process may be wet or dry.

As a result, the dielectric layer 144 may be removed from the dummy storage node electrode 142a and may be shorted to the plate electrode 146 in a subsequent process.

Referring again to FIG. 1, the capacitor 150 and the dummy capacitor 151 are completed.

The plate electrode 146 is formed by depositing polysilicon doped with impurities on the dielectric layer 144 of the storage node electrode 142 and the dummy storage node electrode 142a. As a result, the capacitor 150 having the dielectric layer 144 and the plate electrode 146 formed on the storage node electrode 142 may be completed.

Meanwhile, the plate electrode 146 is formed on the dummy storage node electrode 142a according to an embodiment of the present invention to complete the dummy capacitor 151 without the dielectric layer 144. Therefore, the dummy capacitor 151 according to the embodiment of the present invention electrically shorts the conductive dummy storage node electrode 142a and the conductive plate electrode 146.

Subsequently, a fourth interlayer insulating film 171 is formed on the entire surface of the resultant product. A contact hole is formed in a portion of the fourth interlayer insulating film 171 to be a plate contact 172a for connecting with the plate electrode 146 and a wiring contact 172b for connecting with the metal film 132b serving as the lower conductive layer.

First, the plate electrode 146 and the lower metal film 132b are exposed by etching and exposing the photoresist film or the hard mask film of the portions to be the contacts 172a and 172b. Here, the etching process may be a high density plasma reactive ion etching (HDP RIE) process. The main reaction gas used in the HARC process is a fluorocarbon gas, and examples of the addition reaction gas include oxygen (O ₂ ) and argon (Ar) gas. Fluorocarbon-based gases can be classified into saturated and unsaturated types.

Here, in the etching process of the plate and wiring contacts 172a and 172b having a high aspect ratio, excessive electrons may be generated by the plasma by performing the process with a high process parameter. Although these electrons are piled up on the plate electrode 146, the dummy capacitor 151 according to the embodiment of the present invention may bypass these electrons.

Specifically, the electrons piled up on the plate electrode 146 may be formed by the plate electrode 146 of the dummy capacitor 151 immediately shorting the storage node electrode 142 without the dielectric layer 144 to form a lower storage formed of a conductive material. It may be bypassed to the substrate 100 through the node contact plug 134 and the contact pad 112.

Thus, even when electrons generated excessively due to the etching process at a high process parameter are piled up on the plate electrode 146 during the contact 172a and 172b processes having a high etching rate, the dummy capacitor 151 which is forcibly shorted is removed. Can be bypassed. Accordingly, electrons piled up on the plate electrode 146 are bypassed to the substrate 100, thereby preventing excessive electrons from piled up on the plate electrode 146, thereby causing stress to damage the dielectric layer 144. In addition, it is possible to prevent the dielectric film 144 from being damaged by reducing the refresh characteristics of the semiconductor DRAM device.

Next, an upper metal wiring 182 is formed on the upper surface of the fourth interlayer insulating film 171. After forming a conductive film made of Al, Ti, W, Ti / Al, TiN / Al, TiN / Al / TiN, or a combination thereof, the upper metal is patterned and connected to the plate contacts and the wiring contacts 172a and 172b. The wiring 182 and the like are formed.

Therefore, the wiring contact 172b can be electrically connected to the upper metal wiring 182 and the metal film 132b of the lower wiring formed in the semiconductor substrate 100.

Subsequently, although not shown in the drawings, a guard ring pattern film is formed in the multilayer metal wiring process of the via and the second metal wiring and the fuse region, and a passivation film is finally formed.

Next, a dummy capacitor according to another exemplary embodiment of the present invention in which the storage node electrode and the plate electrode of the dummy capacitor are shorted will be described with reference to FIGS. 5A and 5B.

5A and 5B are a plan view and a cross-sectional view of an element of a dummy capacitor according to another embodiment of the present invention.

Referring first to FIG. 5A, the sacrificial dummy storage node electrode 152 is formed.

A plurality of dummy storage node electrodes 142 are formed at the dummy area of the cell block 200, that is, at one edge thereof. In addition, the sacrificial dummy storage node electrode 152 is formed in the sacrificial dummy capacitor region 160 according to another embodiment of the present invention.

A portion of the sacrificial dummy storage node electrode 152 may be formed over the outermost edge of the cell block 200. A portion of the sacrificial dummy storage node electrode 152 is formed at the outermost edge so that the dummy storage node electrode 152 may also be etched when the conductive film for the plate electrode is deposited and patterned to be suitable for the cell block 200. Can be. The sacrificial dummy storage node electrode 152 may be etched to form a partially cylindrical dummy capacitor having one side open.

Referring to FIG. 5B, it can be seen that the dielectric layer 144 is formed on the sacrificial dummy storage node electrode 152. However, when the plate electrode 146 is formed by depositing and patterning a plate electrode conductive film, it can be seen that a portion of the sacrificial dummy storage node electrode 152 is etched. In addition, the dielectric layer 144 on the sacrificial dummy storage node electrode 152 is also etched. As a result, the sacrificial dummy storage node electrode 152 is etched by predetermined, and thus, the dielectric layer 144 is also etched to electrically connect the plate electrode 146 and a portion of the sacrificial dummy storage node electrode 152. Like the exemplary embodiment of the present invention, the forcibly shorted sacrificial dummy capacitor may bypass electrons piled up on the plate electrode 146.

6 is a plan view showing another embodiment of the present invention.

Referring to FIG. 6, it can be seen that a plurality of dummy storage node electrodes 142 are formed in a dummy area of the cell block 201, that is, at one edge thereof. Here, the patterning is performed such that a part of the dummy storage node electrode 142 is cut when the plate electrode 146 is patterned.

As a result, the dummy storage node electrode 142a and the dielectric layer 144 are etched by only the patterning of the plate electrode 146 without forming the sacrificial dummy storage node electrode. Thus, the plate electrode 146 and the dummy storage node electrode 142a are etched. It is possible to form a dummy capacitor that is shorted.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the method of manufacturing a semiconductor device as described above has one or more of the following effects.

First, electrons piled up on the plate electrode can be bypassed to the substrate.

Second, by bypassing the electrons, damage to the dielectric film of the capacitor can be prevented.

Third, it is possible to prevent the deterioration of the refresh characteristics of the semiconductor DRAM device by preventing damage to the dielectric film of the capacitor.

Claims (7)

At least one cell capacitor formed in the cell region and at least one dummy capacitor formed in the dummy cell region, Each cell capacitor is electrically separated from the storage node electrode and the plate electrode by a dielectric film. Wherein each dummy capacitor includes a dummy storage node electrically connected to the plate electrode. A substrate in which a cell region, a first dummy cell region and a second dummy cell region are defined; A plurality of cells formed on said cell region, said plurality of cells comprising a cylinder type capacitor; A plurality of first dummy cells formed on the first dummy cell region and including the cylindrical capacitors; And A plurality of second dummy cells formed on the second dummy cell region and including a partial cylindrical capacitor having one side open; And a dummy storage node electrode and the plate electrode of the partial cylinder type capacitor. The method of claim 2, And the opening of one side of the partial cylindrical capacitor is 1/4 or more. MOS transistors; And A partial cylindrical capacitor having one side connected to one node of the MOS transistor open; The partial cylinder type capacitor may include a dummy storage node electrode and a plate electrode electrically connected to each other. Forming a cell storage node electrode of a cell region of a cell block and a dummy storage node electrode of a dummy region on a semiconductor substrate, Forming a dielectric layer on the cell storage node electrode and the dummy storage node electrode; Etching the dielectric layer on an upper surface of the dummy storage node electrode, And forming a plate electrode on the semiconductor substrate on which the dielectric layer on the dummy storage node electrode is etched to form a cell capacitor and a dummy capacitor. The method of claim 5, Forming the dummy capacitor forms the dielectric layer on an upper surface of the dummy storage node electrode, Etching the dielectric layer and a portion of the dummy storage node electrode; And forming the plate electrode on the semiconductor substrate on which the dielectric layer and the portion of the dummy storage node electrode are etched to electrically connect the dummy storage node electrode and the plate electrode. The method of claim 5, Forming the dummy capacitor forms the dielectric layer on an upper surface of the dummy storage node electrode, Forming the plate electrode on the dielectric layer, And patterning the plate electrode to etch a portion of the dummy storage node electrode to electrically connect the dummy storage node electrode and the plate electrode.

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