JP2008205255A - Solid-state imaging device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To deposit a film substantially on the same level from an imaging section to a peripheral circuit by reducing stepped portions on a boundary of the imaging section and the peripheral circuit, even if a wiring layer in the peripheral circuit of a solid-state imaging device is multilayered, and to prevent a dielectric breakdown without exposing a wiring pattern during the etch-back of an upper layer film to improve sensitivity characteristics. <P>SOLUTION: The solid-state imaging device includes on a semiconductor substrate 1: an imaging section 10 including at least a photoelectric conversion section that generates signal charges based on an incident light; and a peripheral circuit section 20 that inputs/outputs signals and driving signals from/to the imaging section 10, both signals being generated by the signal charge, wherein the peripheral circuit 20 is formed in a place lower than the imaging section 10 of a semiconductor substrate 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device including an imaging unit and a peripheral circuit unit for inputting and outputting signals to and from the imaging unit on a semiconductor substrate, and a method for manufacturing the same.

In recent years, solid-state imaging devices used for video cameras, electronic cameras, and the like have been further improved in image quality and functionality. This solid-state imaging device has an imaging unit configured by two-dimensionally arranging a large number of pixels on one semiconductor chip, and a peripheral circuit unit arranged outside the imaging unit. In the imaging unit, a photodiode (photoelectric conversion element) generates a signal charge according to the incident light, and in the peripheral circuit unit, the signal charge generated in the imaging unit is driven based on the drive signal, and is taken out as an image signal. Output to the outside.
In the peripheral circuit section, wiring for extracting a pixel signal from the imaging section, and signal processing for subjecting the pixel signal from the imaging section to predetermined signal processing such as CDS (correlated double sampling), gain control, A / D conversion, etc. A circuit and a drive control circuit that controls output of a pixel signal by driving output charges from each pixel unit in the imaging unit are provided. And these image pick-up parts and peripheral circuit parts are formed on a flat semiconductor substrate (for example, refer to patent documents 1).
JP 2004-363473 A

However, as in the configuration described in Patent Document 1 and the like, in the imaging element manufacturing process, the wiring metal layer does not exist in the imaging unit, and the wiring metal layer is formed in the peripheral circuit unit outside the imaging unit. For this reason, when an optical layer such as a flattening film, a protective film, a color filter layer, or a microlens is formed on the imaging unit after the wiring metal layer is formed, the stacking thickness of the wiring metal layer on the imaging unit and peripheral circuit unit There will be a difference in level.
For example, if a flattening film is formed so as to completely cover the wiring metal layer of the peripheral circuit part, the flattening film thickness on the imaging part becomes thicker than necessary, so the rate at which received light reaches the photoelectric conversion part Decreases, the sensitivity of the image sensor decreases, and the F value dependency increases. In addition, due to the effect of the step, the thickness of the planarizing film is different between the vicinity of the step and the position away from the step, which causes a characteristic defect that causes uneven sensitivity of the image sensor. In order to solve these problems, a flattening film on the imaging unit that has become excessively thicker than necessary, for example, as shown in FIG. When adjusting an appropriate film thickness, the wiring metal layer 5 formed in the peripheral circuit portion is exposed from the protective film and the planarization film (upper layer film), and the wiring metal layer is etched and damaged, or plasma damage is caused. In some cases, a breakdown may occur due to insulation breakdown.
As the functionality of solid-state image sensors increases, multilayer wiring has been promoted in the peripheral circuit portion, and two, three, or more wiring layers tend to be formed, and the above problem becomes more prominent. .

The present invention was made in view of the above situation, and even when the wiring layer in the peripheral circuit portion of the solid-state imaging device is multilayered, by eliminating the step of the upper layer film at the boundary portion between the imaging portion and the peripheral circuit portion, The upper layer film is formed at almost the same height from the imaging part to the peripheral circuit part, and the dielectric pattern is prevented without exposing the wiring pattern when the upper layer film is etched back. An object of the present invention is to provide an element and a manufacturing method thereof.

The above object of the present invention is achieved by the following configuration.
(1) An imaging unit including at least a photoelectric conversion unit that generates a signal charge corresponding to incident light on a semiconductor substrate, and a peripheral circuit that inputs and outputs a signal and a drive signal generated by the generated signal charge to and from the imaging unit A solid-state imaging device comprising:
The solid-state imaging device, wherein the peripheral circuit unit is formed at a position lower than the imaging unit of the semiconductor substrate.

  According to this solid-state imaging device, the peripheral circuit unit is formed at a position lower than the imaging unit of the semiconductor substrate, so that the imaging unit and the peripheral circuit unit can be used even when the peripheral circuit unit is multilayered due to function addition or the like. Therefore, a transparent upper layer film can be formed at substantially the same height from the imaging unit to the peripheral circuit unit. As a result, the film thickness of the upper layer film is not greatly different between the part in the vicinity of the step part and the part away from the step part, and the sensitivity of the imaging unit can be made uniform. Further, even when a protective film or the like is formed and etched back in the subsequent manufacturing process, the wiring metal layer in the peripheral circuit portion is not exposed from the upper layer film. And by suppressing the increase in the thickness of the imaging unit, the optical path length in each layer is shortened, the light absorption is reduced, and the decrease in light receiving performance such as light vignetting due to the light shielding film or the transfer electrode can be suppressed. , Sensitivity reduction and F value dependency can be eliminated.

(2) The solid-state imaging device according to (1),
A slope portion for connecting different substrate heights between the image pickup portion and the peripheral circuit portion; and a wiring for connecting the image pickup portion and the peripheral circuit portion to each other is formed in the slope portion. A solid-state imaging device.

  According to this solid-state imaging device, signals can be exchanged between the peripheral circuit unit and the imaging unit by wiring formed in the slope unit.

(3) The solid-state imaging device according to (1) or (2),
A solid-state imaging device, wherein the wiring formed in the slope portion is a wiring made of polysilicon or metal.

  According to this solid-state imaging device, the wiring is made of polysilicon or metal, so that the manufacture is facilitated.

(4) The solid-state imaging device according to (1) or (2),
The solid-state imaging device, wherein the wiring formed in the slope portion is a buried layer made of a high concentration impurity diffusion layer.

  According to this solid-state imaging device, the device structure can be simplified because the wiring is a buried layer made of a high-concentration impurity diffusion layer.

(5) The solid-state imaging device according to any one of (1) to (4),
The solid-state imaging device, wherein the wiring includes a wiring extending from an output unit of the imaging device.

  According to this solid-state imaging device, by extending the wiring from the output unit of the imaging device, the imaging unit and the peripheral circuit unit can be separated by a necessary and sufficient distance, and the imaging unit and the peripheral circuit unit can be separated from each other at a desired height. Can be set to the difference.

(6) The solid-state imaging device according to any one of (1) to (5),
The solid-state imaging device, wherein the wiring includes a wiring for inputting a driving signal of the imaging device.

  According to this solid-state imaging device, by extending the wiring for inputting the driving signal of the imaging device, the imaging unit and the peripheral circuit unit can be separated by a necessary and sufficient distance, and the imaging unit and the peripheral circuit unit can be separated from each other as desired. Can be set to different heights.

(7) A method of manufacturing a solid-state imaging device for producing the solid-state imaging device according to any one of (1) to (6),
Etching the semiconductor substrate so that the peripheral circuit portion is deeper than the imaging portion on the semiconductor substrate;
Forming a wiring connecting the imaging unit and the peripheral circuit unit on the etched semiconductor substrate;
The manufacturing method of the solid-state image sensor characterized by including.

  According to this method for manufacturing a solid-state imaging device, the wiring of the peripheral circuit unit can be formed deeper than the imaging unit 10, the step at the boundary between the imaging unit and the peripheral circuit unit is eliminated, and the transparent upper layer film is formed on the imaging unit. The film can be formed at substantially the same height from the peripheral circuit part to the peripheral circuit part. As a result, the film thickness of the upper layer film is not greatly different between the part in the vicinity of the step part and the part away from the step part, and the sensitivity of the imaging unit can be made uniform. Further, even when a protective film or the like is formed and etched back in a subsequent manufacturing process, the wiring in the peripheral circuit portion is not exposed from the protective film. As a result, problems such as dielectric breakdown and damage to the wiring itself do not occur.

(8) A method for manufacturing a solid-state imaging device according to (7),
The method of manufacturing a solid-state imaging device, wherein the etching process includes forming a slope portion between the imaging portion and the peripheral circuit portion by etching.

  According to this method for manufacturing a solid-state imaging device, by forming a slope portion between the imaging portion and the peripheral circuit portion, wiring can be formed in the slope portion, for example, through holes are formed. The wiring structure can be greatly simplified as compared with the configuration for achieving conduction.

According to the present invention, since the peripheral circuit unit is formed at a position lower than the imaging unit of the semiconductor substrate, the step at the boundary between the imaging unit and the peripheral circuit unit is eliminated, and the transparent upper layer film is removed from the imaging unit. Films can be formed at substantially the same height over the circuit portion. As a result, the film thickness of the upper layer film is not greatly different between the part in the vicinity of the step part and the part in the vicinity of the step part, and the part in the vicinity of the step part due to the difference in the distance that the received light passes through the upper layer film. It is possible to prevent a difference in sensitivity of the imaging unit between a part separated from the step part. Therefore, the occurrence of uneven sensitivity in the solid-state image sensor is prevented.
Further, even when a protective film or the like is formed and etched back in the subsequent manufacturing process, the wiring in the peripheral circuit portion is not exposed. Further, by suppressing the increase in the thickness of the imaging unit, the optical path length in each layer is shortened, so that a decrease in light receiving performance such as vignetting can be suppressed, and a decrease in sensitivity and F value dependency can be eliminated.

Preferred embodiments of a solid-state imaging device according to the present invention will be described in detail with reference to the drawings.
FIG. 1 is a conceptual plan view of a solid-state imaging device according to the present invention, and FIG. 2 is a partially enlarged cross-sectional view showing a cross section AB of FIG.
As shown in FIG. 1, a solid-state imaging device 100 according to the present invention is formed on a semiconductor substrate 1 that is a silicon substrate, and a plurality of photoelectric conversion units (photodiodes) 11 and signal charges generated by each photoelectric conversion unit 11. Are connected to a plurality of vertical charge transfer paths 13 for transferring each of them, a horizontal transfer path 15 for receiving and transferring signal charges transferred from the plurality of vertical charge transfer paths 13, and a terminal portion of the horizontal charge transfer path 15. The imaging unit 10 includes an output unit 17 that converts the transferred signal charge into a voltage signal and outputs the voltage signal. In addition, the solid-state imaging device 100 includes a peripheral circuit unit 20 including a signal processing circuit that inputs drive signals for performing vertical transfer driving and horizontal transfer driving to the imaging unit 10 and outputs image signals from the imaging unit 10. Have. The peripheral circuit unit 20 is provided in the vicinity of the imaging unit 10 and has an input / output interface function and a signal processing function of the solid-state imaging device 100.

  2, the peripheral circuit unit 20 of the solid-state imaging device 100 is formed at a lower position on the semiconductor substrate 1 than the imaging unit 10, and the imaging unit 10 and the peripheral circuit unit 20 has a slope portion 30 that connects different substrate heights to each other, and the slope portion 30 has a wiring 16 made of an N-type high-concentration impurity layer that connects the imaging portion 10 and the peripheral circuit portion 20 to each other. Is formed. In the peripheral circuit portion 20, the wiring 16 is electrically connected to another wiring layer 19 through the contact hole 18, and a pad portion for external connection is formed on the uppermost layer. Although not shown, the peripheral circuit unit 20 may also include a semiconductor circuit for signal processing.

  According to this configuration, even when the wiring layer in the peripheral circuit unit 20 of the solid-state imaging device 100 is multi-layered, the base surface of the semiconductor substrate 1 is lowered in advance in the region of the peripheral circuit unit 20. The thickness of the entire solid-state imaging device 100 can be prevented from becoming unnecessarily thick without being aware of the exposed state of the 20 wiring patterns. When the surface of the semiconductor substrate 1 is formed low in the region of the peripheral circuit portion 20, the substrate surface can be dug down by isotropic etching such as CDE (Chemical Dry Etching). According to this method, the semiconductor substrate 1 can be removed with low damage.

Here, a plan view of the vicinity of the cross section of FIG. 2 is shown in FIG.
FIG. 3 is an enlarged plan view of the main part of the end portion of the horizontal transfer path 15 and the output unit 17 (see FIG. 1).
The channel region CH of the horizontal charge transfer path 13 gradually decreases in width as it approaches the end, and eventually becomes a constant width so as to surround the high concentration region 31 of the floating diffusion FD. A first polycrystalline silicon transfer electrode P1 and a second polycrystalline silicon transfer electrode P2 are disposed above the channel region CH.

An output gate electrode 33 is formed of a polycrystalline silicon layer on the left side of the leftmost first polycrystalline transfer electrode P1. An N ⁺ type high impurity concentration region 31 of the floating diffusion FD is formed in the channel region CH at a certain distance from the output gate 33. A silicon oxide layer is formed on the surface of the silicon substrate 1 and has an opening on the impurity concentration region 31.

  On the other hand, a wiring 35 made of a buried impurity diffusion layer is formed at a position adjacent to the channel region CH. The high impurity concentration region 31 of the FD is connected to one end side of the gate electrode 37 through the opening of the silicon oxide layer, and the other end side of the gate electrode 37 is disposed on the wiring 35. The wiring 35 includes a wiring 35A connected to the source potential VSS and a wiring 35B to the output drain OD (drain potential VDD).

  Further, a reset transistor 39 is formed ahead of the high impurity concentration region 31 in order to reset and discard the charge transferred to the FD region. That is, the channel region CH extends beyond the high impurity concentration region 31, and the gate electrode 41 to the reset gate RS is formed so as to cross the extended channel region CH. A wiring 43 to the reset drain RD is formed on the left side of the channel region CH with the electrode 41 to the reset gate RS interposed therebetween. A wire 45 to the reset gate RS is connected to the end of the electrode 41 opposite to the channel region CH. By applying a voltage to the reset drain RD and applying a voltage to the reset gate RS to extract the charge of the floating diffusion FD, the charge of the floating diffusion FD is cleared. Note that the line width, shape, area, and the like of the gate electrode and wiring shown in FIG. 3 are conceptually shown and are not accurate.

  The wirings 35A, 35B, 43, and 45 extend to the peripheral circuit unit 20 through the slope unit 20, and are connected to the output drain OD, the reset drain RD, the reset gate RS, and the like in the peripheral circuit unit 20.

  That is, as shown in FIG. 2, the slope portion 30 between the imaging portion 10 and the peripheral circuit portion 20 is composed of an N-type high concentration impurity diffusion layer along the inclined surface of the silicon substrate selectively removed by etching. The wiring 16 (35A, 35B, 43, 45) is laid. These wirings are examples of the output unit, and there are a plurality of other wirings. And the inclination of the slope part 30 shown by FIG. 2 is exaggerated rather than the actual thing for description.

Here, FIG. 4 shows a procedure for forming the high concentration impurity layer.
When the wiring is formed of a high-concentration impurity layer, as shown in FIG. 4A, a mask 71 is patterned on the silicon substrate and As ⁺ or P ⁺ is ion-implanted. Then, as shown in FIG. 4B, by removing the mask 71, a buried wiring 73 made of an N-type high concentration impurity diffusion layer is easily formed. According to this configuration, the wiring structure can be further simplified.

FIG. 5 is a cross-sectional view showing a state of a cross section of the image pickup element when the slope portion 30 is provided between the image pickup portion 10 and the peripheral circuit portion 20 as described above.
In the silicon substrate 1, the peripheral circuit unit 20 is formed lower than the imaging unit 10 by an etching process or the like, and a slope unit 30 having a gentle inclined surface is formed between the imaging unit 10 and the peripheral circuit unit 20. . In the imaging unit 10, a photodiode 51, which is a photoelectric conversion unit, and a transfer channel 53 that forms a vertical charge transfer path are formed in the silicon substrate 1, and a transfer electrode 55 is formed above the transfer channel. .

  A BPSG film 57 is formed on the photodiode 51, and after the wiring metal layer 5 is formed in the peripheral circuit portion 20, the planarization film 3 is further formed thereon. A color filter 59 for each color and a condensing microlens 61 are formed on the flattening film 3.

  According to this configuration, even when the peripheral circuit unit 20 is formed as a multilayer wiring due to function addition or the like, the silicon substrate surface of the peripheral circuit unit 20 is formed in advance lower than the silicon substrate surface of the imaging unit 10, so that imaging is performed. When a transparent upper layer film is formed from the imaging unit 10 to the peripheral circuit unit 20 by eliminating the step of the upper layer film at the boundary between the unit 10 and the peripheral circuit unit 20, the film can be formed at substantially the same height. As a result, the film thickness of the upper layer film is not greatly different between the part in the vicinity of the step part and the part in the vicinity of the step part, and the part in the vicinity of the step part due to the difference in the distance that the received light passes through the upper layer film. It is possible to prevent a difference in the sensitivity of the imaging unit 10 from occurring at a position away from the step portion. Therefore, the occurrence of uneven sensitivity is prevented.

  Furthermore, since the increase in the thickness of the imaging unit 10 is suppressed, the distance from the photodiode 51 to the microlens 61 can be shortened, the optical path length in each layer is shortened, the light absorption is reduced, the light shielding film and the transfer are performed. It is possible to suppress a decrease in light receiving performance such as vignetting caused by electrodes. Thereby, a sensitivity fall and F value dependency can be eliminated.

Further, by forming the slope portion 30 between the imaging portion 10 and the peripheral circuit portion 20, it is possible to form a wiring in the slope portion 30, for example, compared with a configuration in which through holes are formed to achieve conduction. Thus, the wiring structure can be greatly simplified.

  The above-mentioned effects are not limited to the CCD solid-state image sensor, but are the same for, for example, a CMOS solid-state image sensor.

Next, a modification of the solid-state imaging device according to the present invention will be described.
As shown in FIG. 2 described above, each wiring 16 made of an N-type high-concentration impurity diffusion layer is formed in the slope portion 30 between the imaging unit 10 and the peripheral circuit unit 20. Instead of the wiring of the diffusion layer, it can also be formed of wiring made of metal wiring such as polysilicon, aluminum, refractory metal such as W, Mo and the like.

FIG. 6 is a cross-sectional view showing a state where wiring is formed of polysilicon, and FIG. 7 is a cross-sectional view showing a state where metal wiring is formed on the insulating film.
As shown in FIG. 6, by forming the wiring 65 made of polysilicon, the wiring can be formed by a simple photolithography technique. Further, as shown in FIG. 7, an insulating film made of SiO ₂ or the like is formed on the semiconductor substrate 1, and a metal wiring 67 is formed thereon, and connected to the high-concentration impurity diffusion layer 70 in the imaging unit 10. Also good. As described above, the wiring of the slope portion 30 may be any of polysilicon, metal, high-concentration impurity diffusion layer, or a combination thereof.

8 and 9 are plan views corresponding to FIGS.
FIG. 8 is a plan view showing a structure in which the peripheral portion 20 and the imaging unit 10 are connected by polysilicon wiring, and FIG. 9 shows a structure in which metal wiring is extended from the peripheral portion 20 to the vicinity of the FD portion of the imaging unit 10. FIG.
As shown in FIG. 8, the polysilicon wiring 75 extending from the peripheral portion 20 through the slope portion 30 to the imaging portion 10 is contacted with the embedded wiring 35A in the vicinity of the FD portion on the imaging portion 10 side. 77 is connected. Similarly, the other wirings 78, 79, and 80 are connected to the wirings 35B, 43, and 45 through the slope portion 30, respectively. In this way, by extending the polysilicon wirings 75, 78, 79, 80 to the imaging unit 10 through the slope portion 30, the wiring in the slope portion 30 can be unified with the polysilicon wiring, and the manufacturing process is simplified.

  Further, as shown in FIG. 9, metal wirings 81, 82, 83, 84 may be used instead of the polysilicon wiring of FIG. Also in this configuration, the wiring in the slope portion 30 can be unified with the metal wiring, and the manufacturing process is simplified.

  As described above, the solid-state imaging device of the present invention does not increase the film thickness of the imaging unit more than necessary, can be manufactured with a simple manufacturing process, and can suppress a decrease in light receiving performance such as vignetting in the imaging unit. Decrease and F value dependency can be eliminated. Therefore, the present invention can be applied to a solid-state imaging device such as a high-quality digital camera.

1 is a conceptual plan view of a solid-state imaging device according to the present invention. It is a partially expanded sectional view which shows the AB cross section shown in FIG. It is a principal part enlarged plan view of the termination | terminus part and output part of a horizontal transfer path. It is a conceptual explanatory view showing procedures (a) and (b) for forming a high concentration impurity layer. It is sectional drawing which shows the mode of the cross section between the imaging part and peripheral circuit part of the position where the photoelectric conversion part is arrange | positioned. It is sectional drawing which shows the state in which the polysilicon wiring was formed. It is sectional drawing which shows the state which formed the metal wiring on the insulating film. It is a top view which shows the structure which connected between the periphery part and the imaging part with the polysilicon wiring. It is a top view which shows the structure which extended metal wiring from the peripheral part to the vicinity of the FD part of an imaging part. It is explanatory drawing which shows the problem of the conventional manufacturing process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 3 Flattening layer 5 Wiring metal layer 10 Imaging part 11 Photoelectric conversion part 13 Vertical charge transfer path 15 Horizontal charge transfer path 16 Wiring 17 Output part 18 Contact hole 19 Other wiring layers 20 Peripheral circuit part 30 Slope part 31 High Concentration impurity diffusion region 33 Output gate electrode 35, 35A, 35B Wiring 37 Gate electrode 39 Reset transistor 41 Gate electrode 43 Wiring to reset drain 45 Wiring to reset gate 51 Photodiode 53 Transfer channel 55 Transfer electrode 57 BPSG film 59 Color filter 61 Microlens 71 Mask 73, 78, 79, 80, 81, 82, 83, 84 Wiring 100 Solid-state imaging device CH Channel region

Claims (8)

An imaging unit including at least a photoelectric conversion unit that generates a signal charge corresponding to incident light on a semiconductor substrate, a peripheral circuit unit that inputs and outputs a signal and a drive signal based on the generated signal charge to the imaging unit, A solid-state imaging device comprising:
The solid-state imaging device, wherein the peripheral circuit unit is formed at a position lower than the imaging unit of the semiconductor substrate. The solid-state imaging device according to claim 1,
A slope portion for connecting different substrate heights between the image pickup portion and the peripheral circuit portion; and a wiring for connecting the image pickup portion and the peripheral circuit portion to each other is formed in the slope portion. A solid-state imaging device. The solid-state imaging device according to claim 1 or 2,
A solid-state imaging device, wherein the wiring formed in the slope portion is a wiring made of polysilicon or metal. The solid-state imaging device according to claim 1 or 2,
The solid-state imaging device, wherein the wiring formed in the slope portion is a buried layer made of a high concentration impurity diffusion layer. It is a solid-state image sensing device according to any one of claims 1 to 4,
The solid-state imaging device, wherein the wiring includes a wiring extending from an output unit of the imaging device. It is a solid-state image sensing device according to any one of claims 1 to 5,
The solid-state imaging device, wherein the wiring includes a wiring for inputting a driving signal of the imaging device. A method for manufacturing a solid-state imaging device for producing the solid-state imaging device according to any one of claims 1 to 6,
Etching the semiconductor substrate so that the peripheral circuit portion is deeper than the imaging portion on the semiconductor substrate;
Forming a wiring connecting the imaging unit and the peripheral circuit unit on the etched semiconductor substrate;
The manufacturing method of the solid-state image sensor characterized by including. It is a manufacturing method of the solid-state image sensing device according to claim 7,
The method of manufacturing a solid-state imaging device, wherein the etching process includes forming a slope portion between the imaging portion and the peripheral circuit portion by etching.

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