JP2008198941A - Semiconductor device and manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a resistance change memory element with stable operation and good reliability. <P>SOLUTION: The semiconductor device has a resistance change memory element 40 structured such that a resistance change layer 41, in which a resistance value changes by applying a voltage, is sandwiched by a lower electrode 42 and an upper electrode 43, wherein a convex portion 43A is formed at the side facing the resistance change layer of at least either one of the two electrodes, a concave portion 41A is formed in the resistance change layer 41 that corresponds to the convex portion 43A, the thickness of the resistance change layer 41 (a transition metal oxide, e.g., a nickel oxide film) becomes thin in a part corresponding to the concave portion 41A, and a resistance value becomes substantially small to surroundings of the concave portion 41A, and thus, an area practically contributing to the operation of the memory is an area corresponding to the convex portion 43A. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a resistance change memory element and a method for manufacturing the semiconductor device.

Currently, as a low-power memory faster than the flash memory which is a mainstream as a nonvolatile memory, the resistance change memory (ReRAM; re sistive r andom a ccess m emory) has attracted attention. The resistance change memory is a memory configured using a resistance change layer whose resistance value is changed by application of a voltage. FIG. 1 shows an example of a change in current value (IV characteristics) when a voltage is applied to the resistance change layer. The resistance change layer is switched between two states, a high resistance state and a low resistance state. For example, when an appropriate voltage is applied to the variable resistance layer that is in a high resistance state, the resistance is changed to a low resistance (set, expressed as “Set” in the figure). Further, when a suitable voltage is applied to the resistance change layer in the low resistance state, the resistance change layer changes to a high resistance state (reset, expressed as “Reset” in the figure).

The material constituting the resistance layer described above, for example a transition metal oxide; is (TMO t ransition m etal o xide ). The transition metal oxide has a good affinity with a device manufacturing process when a device is formed using a silicon wafer, and has attracted attention as a material constituting a resistance change memory element.

  However, in the resistance change memory element, when the area of the resistance change layer (transition metal oxide) increases, the reset current may increase, and the variation of the reset current increases, resulting in unstable memory operation. There is a problem. In order to avoid such unstable operation, it is preferable to reduce the area of the resistance change layer.

  However, for example, if the resistance change layer is reduced to the limit of microfabrication, a contact area with the resist used when pattern-etching the resistance change layer is also reduced, which causes a new problem that resist peeling easily occurs. When the resist peeling occurs in etching of the resistance change layer, there is a concern that the etching shape of the resistance change layer is defective and the reliability of the memory is lowered.

Therefore, as one of the techniques for solving the above-described problem that the operation of the memory becomes unstable, the lower electrode is eliminated from the upper electrode and the lower electrode installed so as to sandwich the resistance change layer, and the plug is substantially formed. structure also serving as a lower electrode (Plug-bE; plug contact type b ottom e lectrode) has been proposed (see non-Patent Document 1). For example, it is effective to contribute to the operation of the resistance change memory while increasing the area of the resistance change layer to, for example, the cell size by configuring the plug connected to the conventional lower electrode to the resistance change layer. The area of the typical resistance change layer can be reduced.
JP 2004-36364 A Samsung, IEDM2005, 31.4

  However, the structure in which the plug is directly connected to the variable resistance layer has a structural problem that electric field concentration is likely to occur at a predetermined portion of the variable resistance layer. For example, the plug is generally formed so as to be embedded in the interlayer insulating layer. For this reason, in order to connect the resistance change layer and the plug, it is preferable that the upper ends of the interlayer insulating layer and the plug are flattened.

  However, a step is likely to occur between the upper end of the interlayer insulating layer made of, for example, a silicon oxide film and the plug made of a metal material such as W or Cu. As described above, when the plug protrudes from the upper end of the interlayer insulating layer or the plug is formed to be recessed from the upper end of the interlayer insulating layer, a portion where the electric field concentrates easily occurs in the resistance change layer. The problem that reliability falls will arise.

  In view of this, the present invention has a general object to provide a new and useful semiconductor device and a method for manufacturing the semiconductor device, which solve the above-described problems.

  A specific problem of the present invention is to provide a semiconductor device including a resistance change memory element that has stable operation and good reliability.

  According to a first aspect of the present invention, there is provided a semiconductor device including a resistance change memory element having a structure in which a resistance change layer whose resistance value is changed by application of a voltage is sandwiched between two electrodes. The semiconductor device is characterized in that a convex portion is formed on the side facing the resistance change layer of at least one of the two electrodes.

  In a second aspect of the present invention, the above-described problem is a method of manufacturing a semiconductor device including a resistance change memory element, the first step of forming a lower electrode of the resistance change memory element, and the lower electrode. And a second step of forming a resistance change layer whose resistance value changes by application of a voltage, and a third step of forming an upper electrode of the resistance change memory element on the resistance change layer. This is solved by a method of manufacturing a semiconductor device, wherein a convex portion is formed on a side facing the resistance change layer of at least one of the upper electrode and the lower electrode.

  According to the present invention, it is possible to provide a semiconductor device including a resistance change memory element that has stable operation and good reliability.

  First, an example of the configuration of a semiconductor device including a resistance change memory element will be described with reference to FIG. 2, and the problems of the semiconductor device of FIG. 2 will be described with reference to FIGS. The outline of will be described with reference to FIG.

  FIG. 2 is a cross-sectional view schematically showing the semiconductor device 10 including the resistance change memory element. Referring to FIG. 2, the semiconductor device 10 shown in the figure is formed on a substrate 11 made of a semiconductor material such as silicon. An element isolation insulating film 12 is formed on the substrate 11 by, for example, STI (shallow trench isolation), and a semiconductor element 20 made of, for example, a MOS transistor is formed in an element formation region defined by the element isolation insulating film 12. Is formed.

  The semiconductor element (MOS transistor) 20 includes a channel 21 formed in the element formation region, a gate insulating film 22 formed on the channel 21, and a gate electrode 23 formed on the gate insulating film 22. ing. A sidewall insulating film 24 is formed on the sidewall of the gate electrode 23. Further, impurity regions 25 and 26 (source region or drain region) having a conductivity type different from that of the substrate 11 (channel 21) are formed on the substrate 11 on both sides of the gate electrode 23, thereby forming a MOS transistor.

  An insulating layer d1 is formed so as to cover the MOS transistor 20, and insulating layers d2, d3, and d4 are sequentially stacked on the insulating layer d1. A plug p1 connected to the impurity region 26 (impurity region 25) is formed so as to penetrate the insulating layer d1. Further, the pattern wiring m1 is connected to the side of the plug p1 opposite to the side connected to the impurity region 26. The insulating layer d2 is formed so as to cover the pattern wiring m1, and the plug p2 connected to the pattern wiring m1 is formed so as to penetrate the insulating layer d2.

  Furthermore, a resistance change memory element 30 in which a resistance change layer 31 is formed between the lower electrode 32 and the upper electrode 33 is formed on the insulating layer d2. The lower electrode 32 is connected to the plug p2, and the upper electrode 33 is connected to the plug p3 that penetrates the insulating layer d3 formed so as to cover the resistance change memory element 30. Further, the pattern wiring m2 is formed on the insulating layer d3, and the insulating layer d4 is formed on the pattern wiring m2, so that the semiconductor device 10 is configured. FIG. 2 shows an area called a unit cell.

  In the above configuration, the plugs p1, p2, and p3 are made of, for example, W, but may be configured using Cu. The pattern wirings m1 and m2 are made of Al, for example, but may be made of Cu.

  In the semiconductor device 10 described above, the resistance change memory element 30 is switched by the MOS transistor 20. The resistance change layer 31 constituting the resistance change memory element 30 is made of a transition metal oxide such as a nickel oxide film, for example, and is switched between two states of a high resistance state and a low resistance state.

  For example, when an appropriate voltage is applied to the resistance change layer in a high resistance state, the resistance change layer changes to a low resistance (set). Further, when an appropriate voltage is applied to the resistance change layer in the low resistance state, the state changes to the high resistance state (reset).

  However, in the resistance change memory element 30, the reset current may increase as the area of the transition metal oxide layer constituting the resistance change layer 31 increases, and the variation in the reset current increases, resulting in a malfunction of the memory. There is a problem that becomes stable. In order to avoid such unstable operation, it is preferable to reduce the area of the resistance change layer 30.

  However, for example, if the resistance change layer 30 is made smaller, the contact area with the resist used when pattern-etching the resistance change layer is also reduced, which causes a new problem that resist peeling tends to occur. When the resist peeling occurs in etching of the resistance change layer, there is a concern that the etching shape of the resistance change layer is defective and the reliability of the memory is lowered.

  For this reason, conventionally, it has been necessary to make the resistance change memory element 30 (resistance change layer 31) sufficiently large with respect to the unit cell. FIG. 3 is an enlarged view showing the vicinity of the resistance change element 30 of the semiconductor device 10 shown in FIG. In the following drawings, the same reference numerals are given to the parts described above, and the description may be omitted. Referring to FIG. 3, the width W1 of the resistance change layer 31 is, for example, about 70% to 80% with respect to the cell size. This is to reduce the concern about the peeling of the resist used for pattern etching of the resistance change layer 31 as described above.

  FIG. 4 is a diagram showing a resistance change memory element 30A having a structure in which the width W1 of the resistance change layer 30 described above is reduced. Referring to FIG. 4, in the resistance change memory element 30A shown in this figure, the width W2 of the lower electrode 32A, the resistance change layer 31A, and the upper electrode 33A is made smaller than the width W1 of the resistance change layer 30. . When the width W2 of the resistance change layer 30A is reduced (for example, slightly larger than the diameter of the plug p3), the area of the resistance change layer 30A is reduced. For this reason, phenomena such as an increase in reset current and variations in reset current are suppressed and the characteristics of the resistance change layer are stabilized, but on the other hand, resist peeling is likely to occur when etching the resistance change layer. There is.

  Therefore, as one of the techniques for solving the problem that the operation of the memory becomes unstable, as shown in FIG. 5, the lower electrode of the upper electrode and the lower electrode installed so as to sandwich the resistance change layer is eliminated, A structure in which the plug p2 substantially doubles as a lower electrode has been proposed (see Samsung, IEDM2005, 31.4). FIG. 5 is a diagram showing an example of a structure in which the lower electrode is omitted in the resistance change memory element and the plug is connected to the resistance change layer.

  Referring to FIG. 5, in the resistance change memory element 30B including the resistance change layer 31B and the upper electrode 33B formed on the resistance change layer 31B, the plug p3 is connected to the upper electrode, and the plug p2 is connected to the resistance change layer 31B. Are connected to each other.

  In the above structure, the plug p2 also functions as the lower electrode. That is, the area of the resistance change layer 31B that substantially contributes to the operation of the memory is an area corresponding to the plug p2. Therefore, in the above structure, the area of the formed resistance change layer 31B is maintained as large as the conventional one, and the area of the effective resistance change layer contributing to the operation of the resistance change memory is reduced. Can do.

  However, in the structure in which the plug p2 is directly connected to the resistance change layer 31B as described above, there arises a structural problem that electric field concentration is likely to occur at a predetermined position of the resistance change layer 31B.

  For example, the plug p2 may protrude from the upper end surface of the insulating layer (interlayer insulating layer) d2, or may be formed to be recessed from the upper end surface of the insulating layer d2. For example, the plug p2 made of W is formed by, for example, a CVD method so that a via hole is formed in the insulating layer d2, and then the via hole is buried. Further, after the above film formation, W formed on the insulating layer d2 is removed by CMP (Chemical Mechanical Polishing) or the like. In addition, various post-treatments (for example, reduction of oxidized W and etch-back treatment) may be performed after CMP. In such various processes, a step is often generated between the insulating layer d2 and the plug p2 having different hardnesses and etching rates with respect to chemicals.

  6A and 6B are diagrams illustrating examples of the shape of the plug p2 connected to the resistance change memory element 30B. For example, as shown in FIG. 6A, the upper end surface of the plug p2 is recessed with respect to the upper end surface of the insulating layer d2, or the upper end surface of the plug p2 is opposite to the upper end surface of the insulating layer d2 as shown in FIG. 6B. May protrude.

  As described above, when the plug p2 has irregularities, electric field concentration may occur between the end of the plug p2 and the resistance change layer 31B, which may reduce the reliability of the memory element. In addition, the uneven shape of the plug p2 may deteriorate the flatness of the upper end side of the resistance change layer 31B to cause unevenness. Such a change in the shape of the upper end side of the resistance change layer 31B may cause the electric field concentration. May be encouraged.

  Further, depending on CMP or surface treatment after CMP, for example, as shown in FIG. 7, unevenness may occur on the surface of the plug p2, and in this case, electric field concentration may occur due to the unevenness shape. It was.

  Therefore, in the present invention, as described below, a convex portion is formed on the side facing the resistance change layer of at least one of the upper electrode and the lower electrode formed so as to sandwich the resistance change layer. Forming. For example, by replacing the resistance change memory element 30 shown in FIG. 2 with the resistance change memory element shown below, a semiconductor device including the resistance change memory element having stable operation and good reliability is configured. Can do.

  FIG. 8 is a cross-sectional view schematically showing a resistance change memory element 40 in which convex portions are formed on the upper electrode. Referring to FIG. 8, the resistance change memory element 40 shown in this figure includes a lower electrode 42, a resistance change layer 41 formed on the lower electrode 42, and an upper electrode 43 formed on the resistance change layer 41. And have. That is, the resistance change layer 41 has a structure sandwiched between two electrodes (the lower electrode 42 and the upper electrode 43).

  On the side of the upper electrode 43 facing the resistance change layer 41, a convex portion 43A that is convex toward the resistance change layer 41 is formed. Further, the resistance change layer 41 is formed with a concave portion 41A corresponding to the convex portion 43A. That is, the resistance change layer 41 and the upper electrode 43 are laminated such that the convex portion 43A formed on the upper electrode is combined with the concave portion 41 formed on the resistance change layer 41A.

  In the resistance change memory element 40, the area of the resistance change layer 41 that substantially contributes to the operation of the memory is an area corresponding to the convex portion 43A (the concave portion 43B). This is because the resistance change layer 41 (transition metal oxide, for example, nickel oxide film) is thin in the portion corresponding to the recess 41A, and the resistance value is significantly reduced with respect to the periphery of the recess 41A. Therefore, in the above structure, the area of the resistance change layer 41 formed by patterning by etching is made as large as the conventional one (for example, about 70% to 80% of the cell size), and the resistance change memory The area of the effective variable resistance layer that contributes to the operation can be reduced.

  For this reason, when the above-described resistance change memory element 40 (resistance change layer 41) is subjected to pattern etching, the contact area of the resist is increased. Therefore, while suppressing the occurrence of resist peeling and improving the reliability of the memory, further increasing the reset current and the variation in the reset current when the area of the resistance change layer is increased, the operation of the memory is suppressed. It can be stable.

  Moreover, although said convex part may be formed in any of an upper electrode and a lower electrode, it is more preferable to be formed in an upper electrode. For example, when the convex portion is formed on the upper electrode, the effect of the electrode step shape (convex portion) on the flatness of the variable resistance layer is reduced when the resistance change memory element is formed. The influence of is suppressed.

  In addition, the above-mentioned convex portion can be formed at various locations on the upper electrode or the lower electrode, but is shifted from the position corresponding to the plug connected to at least one of the upper electrode or the lower electrode. More preferably, they are formed at different positions. In this case, it is possible to separate the portion of the resistance change layer 41 that substantially contributes to the operation of the memory (the recess 41A) from the top of the plug p2 where the step shape is highly likely to be formed. It is possible to suppress the influence of the electric field concentration described above, which is preferable.

  For example, the resistance change memory element 40 may be configured with the following size as an example. The following numerical values are examples when a resistance change memory element is configured, and the present invention is not limited to this. For example, when the width of the cell size is 100 nm to 700 nm, the width W3 of the resistance change memory element 40 (resistance change layer 41) is 70% to 80% of the width of the cell size, and the thickness of the resistance change layer 41 is 20 nm to The thickness of the recess 41A of the resistance change layer 41 is 10 nm to 20 nm, the width L1 of the recess 41A (projection 43A) is 30 nm to 200 nm, and the diameters of the plugs p2 and p3 are 30 nm to 200 nm.

  Further, for example, the structure shown in FIG. 8 can be changed as shown in FIG. 9 below. FIG. 9 is a diagram showing a resistance change memory element 50 which is a modification of the resistance change memory element 40 shown in FIG.

  Referring to FIG. 9, the resistance change memory element 50 shown in the figure includes a lower electrode 52, a resistance change layer 51, a resistance change layer 51, and a lower electrode 42, a resistance change layer 41, and an upper electrode 43 of the resistance change memory element 40, respectively. And an upper electrode 53. In the case shown in this figure, the resistance change layer 51 is not formed with a recess, and further, an insulating layer 54 is formed between the resistance change layer 51 and the upper electrode 53, which is different from the case of FIG. To do.

  Further, the insulating layer 54 is formed with a through hole 54A through which the convex portion 53A formed in the upper electrode 53 passes, and the convex portion 53A passes through the through hole 54A and comes into contact with the resistance change layer 51. It is configured.

  The resistance change memory element 50 has the same effect as that of the resistance change memory element 40 shown in FIG. 8 and further has an insulating layer 54. Therefore, the resistance change memory element 50 extends from the lower electrode 52 to the upper electrode 53. The formation of a leak path is suppressed, and the reliability of the memory can be improved. Moreover, since it is not necessary to form a recessed part in a resistance change layer when forming a convex part in an upper electrode, the risk that the singular point of electric field concentration may be formed in a resistance change layer can be further reduced.

For example, the insulating layer 54 can be formed of a silicon oxide film (SiO ₂ film), but may be formed using other insulating materials (for example, SiN film, SiC film, etc.). Further, an adhesion layer for improving the adhesion between the insulating layer 54 and the upper electrode 53 may be added between the insulating layer 54 and the upper electrode 53. For example, when the insulating layer 54 is made of a silicon oxide film and the upper electrode 53 is made of Pt, the adhesion layer is a metal material (alloy material) different from that of the upper electrode, and has adhesion with both the insulation layer 54 and the upper electrode 53. It can be formed of Ti which is good. In addition, when an adhesion layer is added, a through-hole through which the convex portion 53A passes is formed in the adhesion layer (this structure will be described later in FIG. 13A and later).

  Moreover, the convex part which contact | connects a resistance change layer may be formed in the lower electrode, for example as shown in the following FIG. 10, FIG.

  FIG. 10 is a diagram showing a resistance change memory element 60 having a lower electrode 62, a resistance change layer 61, and an upper electrode 63. In the case shown in the figure, a convex portion 62 </ b> A is formed on the lower electrode 62. In addition, the resistance change layer 61 has a recess 61A corresponding to the protrusion 62A. FIG. 11 is a view showing a resistance change memory element 70 having a lower electrode 72, a resistance change layer 71, an upper electrode 73, and an insulating layer 74 formed between the resistance change layer 71 and the lower electrode 72. In the case shown in the figure, a convex portion 72A is formed on the lower electrode 72, an insulating layer 74 is further formed between the resistance change layer 71 and the lower electrode 72, and the convex portion 72A is a through hole 74A formed in the insulating layer 74. It is comprised so that it may penetrate.

  Thus, the convex part may be formed on either the lower electrode or the upper electrode, or may be formed on both the lower electrode and the upper electrode.

  Next, an example of a method for manufacturing a semiconductor device provided with the resistance change memory element will be described with reference to the drawings. First, an example of a method for manufacturing a semiconductor device in which the resistance change memory element 30 is replaced with the resistance change memory element 40 shown in FIG. 8 in the semiconductor device 10 shown in FIG. 2 will be described step by step based on FIGS. 12A to 12M. (Example 1) Furthermore, in the semiconductor device 10 shown in FIG. 2, an example of a method of manufacturing a semiconductor device in which the resistance change memory element 30 is replaced with the resistance change memory element 50 shown in FIG. A procedure will be described based on 13J (Example 2).

  First, in the step shown in FIG. 12A, the MOS transistor 20 is formed in the element formation region defined by the element isolation layer 12 and the element isolation insulating film 12 on the substrate 11 by a known method. The MOS transistor 20 has a channel 21 formed in the element formation region, a gate insulating film 22 formed on the channel 21, and a gate electrode 23 formed on the gate insulating film 22. A sidewall insulating film 24 is formed on the sidewall of the gate electrode 23. Further, impurity regions 25 and 26 (source region or drain region) having a conductivity type different from that of the substrate 11 (channel 21) are formed on the substrate 11 on both sides of the gate electrode 23.

  Further, an insulating layer d1 covering the MOS transistor 20 is formed, and a plug p1 connected to the impurity region of the MOS transistor is formed so as to penetrate the insulating layer d1. Next, a pattern wiring m1 made of, for example, Al is formed on the insulating layer d1. The pattern wiring m1 may be formed of Cu. Next, an insulating layer (interlayer insulating layer) d2 that covers the pattern wiring m1 is formed.

  Next, in the step shown in FIG. 12B, a contact hole H1 is opened in the insulating layer (interlayer insulating layer) d2 by pattern etching using a resist mask (not shown).

  Next, in the step shown in FIG. 12C, a plug p2 made of W for burying the contact hole H1 is formed by, eg, CVD. For example, when depositing W by CVD, the contact hole H1 is buried by W, and a W film is also formed on the insulating layer d2. For this reason, excess W formed on the insulating layer d2 is deleted by, for example, CMP. Further, if necessary, after the CMP treatment, cleaning or reduction of oxidized W or an etch back treatment is performed. In this case, as described above with reference to FIGS. 6 to 7, the upper end of the plug p2 may be recessed or protrude from the upper end surface of the insulating layer d2.

  Next, in a step shown in 12D, a lower electrode layer 42F made of a Pt / Ti film (a laminated structure of Pt and Ti, where Ti is the insulating layer d2 side) is formed by, for example, a sputtering method.

  Next, in the step shown in FIG. 12E, a resistance change layer 41F made of a nickel oxide film (NiO film) is formed to a thickness of 50 nm. In this case, in order to form a recess in the resistance change layer 41F in a later step, it is preferable to form the resistance change layer thick. The nickel oxide film can be formed, for example, by reactive sputtering using a nickel (Ni) target, or by oxidizing the nickel film after forming the nickel film by sputtering.

  Next, in a step shown in FIG. 12F, a resist pattern (not shown) is formed on the resistance change layer 41F, and a recess 41A is formed in the resistance change layer 41F by etching using the resist pattern as a mask. In this case, the thickness of the resistance change layer at the bottom of the recess 41A is set to 20 nm.

  Next, in the step shown in FIG. 12G, an upper electrode layer 43F made of Pt is formed by, for example, a sputtering method. In this case, the upper electrode layer 43F is formed to have a convex portion 43A in which the concave portion 41A is embedded.

  Next, in the step shown in FIG. 12H, a resist pattern (not shown) is formed on the upper electrode layer 43F, and the upper electrode 43F, the resistance change layer 41F, and the lower electrode layer 42F are formed by etching using the resist pattern as a mask. Etch. As a result, the resistance change memory element 40 configured by sandwiching the resistance change layer 41 between the lower electrode 42 and the upper electrode 43 having the protrusion 43A is formed.

  Further, in the step shown in FIG. 12I, an insulating layer (interlayer insulating layer) d3 is formed so as to cover the resistance change memory element 40, and in the step shown in FIG. 12J, a resist mask (not shown) is formed on the insulating layer d3. A contact hole H2 reaching the upper electrode 43 is formed by the used pattern etching.

  Next, in the step shown in FIG. 12K, a plug p3 for burying the contact hole H2 is formed in the same manner as in the step of FIG. 12C.

  Further, it is preferable that the convex portion 43A is formed at a position shifted from a position corresponding to the plug p3 (upper plug) connected to the upper electrode 43. By disposing the convex portion 43A and the plug p3 in a shifted manner, it becomes possible to separate the concave portion of the resistance change layer that contributes to the operation of the memory and the portion to which the plug is connected. It is possible to reduce the risk of electric field concentration due to deformation and alteration of the resistance change layer.

  Similarly, the convex portion 43A is preferably formed at a position shifted from a position corresponding to the plug p2 (lower plug) connected to the lower electrode. By disposing the protrusion 43A and the plug p2 in a shifted manner, the recess of the resistance change layer contributing to the operation of the memory can be separated from the portion to which the plug is connected. It is possible to reduce the risk of electric field concentration due to deformation and alteration of the resistance change layer.

  Next, in a step shown in FIG. 12L, a pattern wiring connected to the plug p3 is formed on the insulating layer d3, and further, an insulating layer d4 is formed on the pattern wiring m2 in the step shown in FIG. 12M. The semiconductor device 100 can be manufactured.

  In the above manufacturing method, by forming the convex portion 43A on the upper electrode 43, the area of the resistance change layer 41 that substantially contributes to the operation of the memory is set to an area corresponding to the convex portion 43A (the concave portion 43B). The increase in the reset current of the memory and the occurrence of variations in the reset current are suppressed. For this reason, in the etching of the resistance change layer 41F (upper electrode layer 43F, lower electrode layer 42F) in FIG. 12H, the area of the resist pattern formed on the upper electrode layer 43F is increased to prevent peeling of the resist pattern. The reliability of the memory can be improved.

  Further, in the case where the convex portion is formed on the lower electrode 42, the resistance change layer may be formed after the convex portion is formed by pattern etching of the lower electrode layer. In addition, after the resistance change layer is formed, a step of planarizing the resistance change layer by CMP may be added.

  Next, an example of a semiconductor device manufacturing method in which the resistance change memory element 30 in the semiconductor device 10 shown in FIG. 2 is replaced with the resistance change memory element 50 shown in FIG. 9 will be described.

  First, steps similar to those shown in FIGS. 12A to 12D shown in the first embodiment are performed. Note that the lower electrode layer 42F of Example 1 corresponds to the lower electrode layer 52F in this example.

  Next, in the step shown in FIG. 13A, a resistance change layer 51F made of a nickel oxide film (NiO film) is formed to a thickness of 20 nm in the same manner as in the step of FIG. 12E of Example 1. In the case of the present embodiment, since the concave portion is not formed in the resistance change layer 51F in the subsequent process, the resistance change layer may be thinner than in the case of the first embodiment.

Next, in the step shown in FIG. 13B, an insulating layer 54F made of a silicon oxide film (SiO ₂ film) is formed on the resistance change layer 51F by sputtering, for example, so as to have a thickness of 100 nm. An adhesion layer 55F made of Ti is laminated on 54F so as to have a thickness of 20 nm, for example, by sputtering.

  Next, in the step shown in FIG. 13C, a resist pattern (not shown) is formed on the adhesion layer 55F, and the through hole 55A is formed in the adhesion layer 55F and the through hole is formed in the insulating layer 54F using the resist pattern as a mask. 54A is formed in order, and the resistance change layer 51F is exposed.

  Next, in the step shown in FIG. 13D, an upper electrode layer 53F made of Pt is formed by, for example, a sputtering method. In this case, the upper electrode layer 53F is formed to have a convex portion 53A that penetrates the through holes 55A and 54A and reaches the resistance change layer 51F.

  Next, in the step shown in FIG. 13E, a resist pattern (not shown) is formed on the upper electrode layer 53F, and the upper electrode layer 53F, the adhesion layer 55F, the insulating layer 54F, The resistance change layer 51F and the lower electrode layer 52F are etched. As a result, the resistance change memory element 50 is formed.

  Next, the semiconductor device 200 shown in FIG. 13F can be manufactured by performing the same processes as those in FIGS. 12I to 12M of the first embodiment.

  In addition to the same effects as the manufacturing method shown in the first embodiment, the manufacturing method shown in this embodiment further forms a leak path from the lower electrode 52 to the upper electrode 53 in order to form the insulating layer 54. This is suppressed, and the reliability of the memory can be improved. Moreover, since it is not necessary to form a recessed part in a resistance change layer when forming a convex part in an upper electrode, the risk that the singular point of electric field concentration may be formed in a resistance change layer can be further reduced.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the specific embodiments described above, and various modifications and changes can be made within the scope described in the claims.

  For example, the number of layers of the multilayer wiring structure connected to the resistance change memory element can be variously modified and changed. The plugs p1, p2, and p3 are formed of W, for example, but may be formed of Cu. The pattern wirings m1 and m2 are made of, for example, Al, but may be made of Cu.

According to the present invention, it is possible to provide a semiconductor device including a resistance change memory element that has stable operation and good reliability.
(Appendix 1)
A semiconductor device including a resistance change memory element having a structure in which a resistance change layer is sandwiched between two electrodes,
A semiconductor device, wherein a convex portion is formed on the side facing the resistance change layer of at least one of the two electrodes.
(Appendix 2)
The resistance change memory element is formed on a semiconductor substrate, and the two electrodes include a lower electrode formed on a side close to the semiconductor substrate and an upper electrode formed on the resistance change layer on the lower electrode. The semiconductor device according to appendix 1, wherein the convex portion is formed on the upper electrode.
(Appendix 3)
3. The semiconductor device according to claim 1, wherein the convex portion is formed at a position shifted from a position corresponding to a plug connected to at least one of the two electrodes.
(Appendix 4)
4. The semiconductor device according to claim 1, wherein a concave portion corresponding to the convex portion is formed in the resistance change layer.
(Appendix 5)
Additional notes 1 to 3, wherein an insulating layer is formed between the electrode on which the convex portion is formed and the variable resistance layer, and the convex portion is formed so as to penetrate the insulating layer. The semiconductor device according to claim 1.
(Appendix 6)
An adhesion layer between the electrode and the insulating layer is formed between the insulating layer and the electrode on which the protrusion is formed, and the protrusion is formed so as to penetrate the adhesion layer and the insulating layer. The semiconductor device according to appendix 5, wherein:
(Appendix 7)
7. The semiconductor device according to any one of appendices 1 to 6, wherein the variable resistance layer is made of an oxide of a transition metal.
(Appendix 8)
8. The semiconductor device according to any one of appendices 1 to 7, wherein the variable resistance layer is made of a nickel oxide film.
(Appendix 9)
A method of manufacturing a semiconductor device including a resistance change memory element,
Forming a lower electrode of the resistance change memory element;
A second step of forming a variable resistance layer on the lower electrode;
A third step of forming an upper electrode of the resistance change memory element on the resistance change layer,
A method of manufacturing a semiconductor device, wherein a convex portion is formed on a side facing the resistance change layer of at least one of the upper electrode and the lower electrode.
(Appendix 10)
In the second step, a recess is formed in the resistance change layer,
10. The method of manufacturing a semiconductor device according to appendix 9, wherein in the third step, the upper electrode is formed so as to have the convex portion burying the concave portion.
(Appendix 11)
Forming an insulating layer on the variable resistance layer after the second step;
Etching the insulating layer to form a through hole exposing the resistance change layer, and
The method of manufacturing a semiconductor device according to appendix 9, wherein, in the third step, the upper electrode is formed so as to have the convex portion burying the through hole.
(Appendix 12)
12. The semiconductor according to claim 11, wherein an adhesion layer between the insulation layer and the upper electrode is further formed on the insulation layer, and the convex portion is formed so as to penetrate the insulation layer and the adhesion layer. Device manufacturing method.
(Appendix 13)
13. The method of manufacturing a semiconductor device according to appendix 12, wherein the adhesion layer includes a metal material different from a metal material constituting the upper electrode.
(Appendix 14)
The lower electrode is formed on a lower plug electrically connected to the lower electrode,
14. The method of manufacturing a semiconductor device according to any one of appendices 9 to 13, wherein the convex portion is formed at a position shifted from a position corresponding to the lower plug.
(Appendix 15)
Forming a top plug connected to the top electrode;
15. The method of manufacturing a semiconductor device according to claim 9, wherein the convex portion is formed at a position shifted from a position corresponding to the upper plug.

It is a figure which shows the principle of a resistance change memory element. It is a figure which shows the semiconductor device which has a resistance change memory element. It is FIG. (1) which shows the problem of a resistance change memory element. It is FIG. (2) which shows the problem of a resistance change memory element. FIG. 10 is a diagram (part 3) illustrating a problem of the resistance change memory element; It is FIG. (4) which shows the problem of a resistance change memory element. FIG. 9 is a diagram (No. 5) illustrating a problem of the resistance change memory element; FIG. 6 is a diagram (No. 6) illustrating a problem of the resistance change memory element; BRIEF DESCRIPTION OF THE DRAWINGS It is FIG. (1) which shows the outline | summary of the resistance change memory element by this invention. FIG. 5 is a second diagram illustrating an overview of a resistance change memory element according to the present invention; FIG. 3 is a third diagram illustrating an overview of a resistance change memory element according to the present invention; It is FIG. (4) which shows the outline | summary of the resistance change memory element by this invention. FIG. 3 is a diagram (No. 1) for illustrating a method for manufacturing a semiconductor device according to Example 1; FIG. 6 is a second diagram illustrating the method for fabricating the semiconductor device according to the first embodiment. FIG. 6 is a diagram (No. 3) for illustrating the method for manufacturing the semiconductor device according to Example 1; FIG. 7 is a diagram (No. 4) for illustrating a method for manufacturing a semiconductor device according to Example 1; FIG. 5 is a diagram (No. 5) for illustrating a method for manufacturing a semiconductor device according to Example 1; FIG. 6 is a sixth diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 7 is a diagram (No. 7) for illustrating a method for manufacturing a semiconductor device according to Example 1; FIG. 8 is a view (No. 8) for illustrating a method for manufacturing a semiconductor device according to Example 1; FIG. 9 is a diagram (No. 9) for illustrating a method for manufacturing a semiconductor device according to Example 1; FIG. 10 is a diagram (No. 10) for illustrating the method of manufacturing the semiconductor device according to Example 1; FIG. 11 is a diagram (No. 11) illustrating the method for manufacturing the semiconductor device according to Example 1; FIG. 12 is a view (No. 12) illustrating the method for manufacturing the semiconductor device according to Example 1; FIG. 13 is a view (No. 13) illustrating the method for manufacturing the semiconductor device according to Embodiment 1; FIG. 6A is a diagram (No. 1) illustrating a method for manufacturing a semiconductor device according to Example 2; FIG. 10 is a second diagram illustrating the method for fabricating the semiconductor device according to the second embodiment. FIG. 11 is a diagram (No. 3) for illustrating a method for manufacturing a semiconductor device according to Example 2; FIG. 10 is a diagram (No. 4) for illustrating a method for manufacturing a semiconductor device according to Example 2; FIG. 10 is a diagram (No. 5) for illustrating a method for manufacturing a semiconductor device according to Example 2; FIG. 6 is a diagram (No. 6) illustrating a method for manufacturing a semiconductor device according to Example 2;

Explanation of symbols

10, 100, 200 Semiconductor device 11 Substrate 12 Element isolation insulating film 20 MOS transistor 21 Channel 22 Gate insulating film 23 Gate electrode 24 Side wall insulating film 25, 26 Impurity region 30, 40, 50, 60, 70 Resistance change memory element 31, 41, 51, 61, 71 Resistance change layer 41A, 61A Recess 32, 42, 52, 62, 72 Lower electrode 33, 43, 53, 63, 73 Upper electrode 43A, 53A, 63A, 73A Protrusion 54 Insulating layer 55 Adhesion Layer d1, d2, d3, d4 Insulating layer m1, m2 Pattern wiring

Claims (6)

A semiconductor device including a resistance change memory element having a structure in which a resistance change layer is sandwiched between two electrodes,
A semiconductor device, wherein a convex portion is formed on the side facing the resistance change layer of at least one of the two electrodes.   The resistance change memory element is formed on a semiconductor substrate, and the two electrodes include a lower electrode formed on a side close to the semiconductor substrate and an upper electrode formed on the resistance change layer on the lower electrode. The semiconductor device according to claim 1, wherein the convex portion is formed on the upper electrode.   The semiconductor device according to claim 1, wherein the convex portion is formed at a position shifted from a position corresponding to a plug connected to at least one of the two electrodes.   The insulating layer is formed between the electrode in which the said convex part is formed, and the said resistance change layer, The said convex part is formed so that the said insulating layer may be penetrated. The semiconductor device according to any one of the above. A method of manufacturing a semiconductor device including a resistance change memory element,
Forming a lower electrode of the resistance change memory element;
A second step of forming a variable resistance layer on the lower electrode;
A third step of forming an upper electrode of the resistance change memory element on the resistance change layer,
A method of manufacturing a semiconductor device, wherein a convex portion is formed on a side facing the resistance change layer of at least one of the upper electrode and the lower electrode. Forming an insulating layer on the variable resistance layer after the second step;
Etching the insulating layer to form a through hole exposing the resistance change layer, and
6. The method of manufacturing a semiconductor device according to claim 5, wherein, in the third step, the upper electrode is formed so as to have the convex portion burying the through hole.

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