JP2008193389A - Synchronized sweep synthesizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronized sweep frequency synthesizer capable of quickly changing a frequency in a stepwise pattern from a start frequency to a stop frequency, and outputting a synchronization pulse synchronized with a sweep timing. <P>SOLUTION: The synchronized sweep frequency synthesizer includes a voltage controlled oscillator 11 and a phase comparison control part. The voltage controlled oscillator 11 provides the specified start frequency till the phase comparison control part detects a lock, and provides a sweep frequency having a stepwise waveform after the lock is detected, the phase comparison control part outputs a sweep synchronization pulse synchronized with the sweep timing. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a frequency synthesizer, and more particularly, to a synchronous sweep synthesizer that can rapidly sweep an output frequency and output a pulse synchronized with the sweep.

[Description of Prior Art]
A conventional frequency synthesizer will be described with reference to FIG. FIG. 8 is a configuration block diagram of a conventional frequency synthesizer.
As shown in FIG. 8, the conventional frequency synthesizer includes a VCO (Voltage Controlled Oscillator) 1, a frequency divider 2, a phase comparator 3, and a loop filter 4.

The VCO 1 is a voltage controlled oscillator that oscillates at a desired frequency Fout using the input from the loop filter 4 as a control voltage.
The frequency divider 2 divides the oscillation frequency Fout generated by the VCO 1 by 1 / N.

The phase comparator 3 compares the phase of the frequency output from the frequency divider 2 with the reference signal (Fref) provided from a reference oscillation circuit (not shown), and outputs a phase difference signal.
The loop filter 4 is a loop filter that outputs a control voltage to the VCO 1 based on the phase difference signal from the phase comparator 3.

  In the conventional frequency synthesizer, the frequency oscillated by the VCO 1 is frequency-divided by 1 / N by the frequency divider 2, and the phase difference from the reference signal Fref is detected by the phase comparator 3 to output a phase difference signal. Then, a control signal corresponding to the phase difference signal is output from the loop filter 4 to control the oscillation frequency of the VCO 1. In this way, a desired output frequency Fout can be obtained.

Conventionally, there has been a sweep generator as a device for sequentially changing the frequency for output.
In such a sweep generator, it was possible to change linearly from a start frequency to a stop frequency using a sawtooth wave. FIG. 9 is a schematic explanatory diagram showing sweeping by a sawtooth wave.
As shown in FIG. 9, when the frequency is changed using the linear portion of the sawtooth wave, the frequency changes with a constant slope with respect to time.
In such a waveform, for example, when detecting a resonance frequency, it is difficult to detect which frequency is optimal.

[Prior art documents]
In addition, as a prior art regarding the frequency synthesizer which sweeps at high speed, Unexamined-Japanese-Patent No. 2005-265484 (patent document 1), Unexamined-Japanese-Patent No. 5-60809 (patent document 2), and Unexamined-Japanese-Patent No. 10-160771 (patent) Document 3) and Japanese Patent Laid-Open No. 11-308287 (Patent Document 4).

Patent Document 1 describes a configuration in which an oscillator sweeps a predetermined frequency range with a predetermined sweep time and synchronizes the sweep timing.
Patent Document 2 describes a structure in which a synchronized sweep signal is applied to a sweep generator and a gated sweep mode is operated in a spectrum analyzer.

Patent Document 3 describes a structure that sweeps at a high speed in a frequency synthesizer.
Patent Document 4 describes a structure in which a frequency synthesizer sweeps while performing a synchronous pull-in operation.

JP 2005-265484 A Japanese Patent Laid-Open No. 5-60809 Japanese Patent Laid-Open No. 10-160771 Japanese Patent Laid-Open No. 11-308287

  However, the above conventional frequency synthesizer and sweep generator do not change the frequency at high speed stepwise from the start frequency to the stop frequency, but obtain a synchronous pulse synchronized with the frequency and sweep timing that change at high speed in the step shape. There was a problem that could not.

FIG. 10 shows an example of a staircase waveform. FIG. 10 is a schematic explanatory diagram of sweeping by a staircase waveform.
As shown in FIG. 10, the staircase waveform changes the frequency by a certain value every certain time. Since the certain frequency is held for a certain time, it is convenient for detecting the resonance frequency, for example. . The sweep is performed in synchronization with the synchronization pulse.

  The above-mentioned Patent Document 1 describes that a repetition frequency signal whose frequency changes in steps like f1, f2, f3, and f4 in synchronism with a predetermined sweep timing is described. It is not intended to sweep in detail.

  The present invention has been made in view of the above circumstances, and provides a synchronous sweep frequency synthesizer capable of changing a frequency in a stepwise manner from a start frequency to a stop frequency and outputting a synchronous pulse synchronized with a sweep timing. The purpose is to do.

  The present invention for solving the problems of the above-described conventional example includes a voltage-controlled oscillator that oscillates a frequency signal in accordance with an input control voltage, a frequency divider that divides the oscillation frequency signal, and the frequency divider. An AD converter that performs analog / digital conversion on the received signal, a phase comparison unit that compares the phase of the analog / digital converted signal and a desired frequency signal, and outputs a phase difference signal corresponding to the phase difference; A loop filter that outputs a control signal for controlling the voltage controlled oscillator based on the phase difference signal and a DA converter that performs digital / analog conversion of the control signal. The voltage controlled oscillator detects a lock in the phase comparison unit. Provides a specific start frequency, and after a lock is detected, provides a sweep frequency that is a staircase waveform, and the phase comparison unit is a sweep sync pulse that is synchronized to the sweep timing. It is characterized by outputting.

  In the synchronous sweep synthesizer, the present invention is characterized in that the sweep frequency is formed by increasing a specific frequency at a constant time interval.

  In the synchronous sweep synthesizer, the present invention is characterized in that the sweep frequency is changed by changing a predetermined time interval or a specific frequency.

  In the synchronous sweep synthesizer, the present invention provides a voltage-controlled oscillator that oscillates a frequency signal in accordance with an input control voltage, a frequency divider that divides the oscillation frequency signal, and analog-converts the divided signal An A / D converter that performs digital / digital conversion, a phase comparison unit that compares the phase of the analog / digital converted signal and a desired frequency signal, and outputs a phase difference signal corresponding to the phase difference, and the phase difference signal A loop filter that outputs a control signal for controlling the voltage controlled oscillator based on the D / A converter that performs digital / analog conversion of the control signal, and the phase comparison unit outputs a phase difference based on the input frequency setting information. A parameter output unit for calculating a frequency-divided value necessary for generating a signal, and a predetermined time interval value and a specific frequency value when a sweep start trigger is detected A sweep frequency counter that outputs a sweep sync pulse at regular time intervals based on the sweep condition, and outputs a frequency value obtained by adding a specific frequency to the held frequency value in sync with the sweep sync pulse, and start When the first switching signal input by the lock detection at the frequency is detected, the frequency setting information output to the parameter output unit is switched from the specific start frequency value to the frequency value from the sweep frequency counter and output. And a first switch.

  Further, according to the present invention, in the synchronous sweep synthesizer, the parameter output unit calculates the first divided value based on the frequency setting information input from the first switch, while based on the value of the center frequency of the sweep. A phase output unit that calculates and holds the second frequency division value, and when the phase comparison unit detects the second switching signal input at the start of the sweep, the phase output unit outputs the frequency division value output from the parameter output unit. The second switch for switching from the first frequency division value to the second frequency division value and outputting a fixed value during the sweep period is provided.

  In the synchronous sweep synthesizer, the present invention is characterized in that the slope of the sweep is changed by changing a value of a certain time interval or a value of a specific frequency included in the sweep condition.

  According to the present invention, the phase comparison unit provides a specific start frequency until the voltage controlled oscillator detects the lock by the phase comparison unit, and after the lock is detected, the sweep frequency becomes a staircase waveform. Since the phase comparison unit is a synchronous sweep synthesizer that outputs a sweep synchronization pulse synchronized with the sweep timing, it locks at the start frequency, starts the sweep, performs a stable sweep, and synchronizes with the sweep. This has the effect of outputting a pulse.

  Further, according to the present invention, the phase comparison unit detects a parameter output unit that calculates a division value necessary for generating a phase difference signal based on the input frequency setting information, and detects a sweep start trigger. Then, based on a sweep condition including a predetermined time interval value and a specific frequency value, a sweep synchronization pulse is output at a predetermined time interval, and the specific frequency is added to the held frequency value. When the sweep frequency counter that outputs the frequency value in synchronization with the sweep synchronization pulse and the first switching signal that is input by lock detection at the start frequency are detected, the frequency setting information that is output to the parameter output unit is specified. A synchronous sweep synthesizer comprising a first switch that switches from a start frequency value to a frequency value from a sweep frequency counter for output. Therefore, while stabilizing the output from the AD converter, lock at the start frequency and then start sweeping under specified conditions, perform stable high-speed sweep with a stepped waveform, and synchronize with the sweep Can be output.

  Further, according to the present invention, the parameter output unit calculates the first divided value based on the frequency setting information input from the first switch, while the second output based on the value of the center frequency of the sweep. When the second switching signal input by the start of sweep is detected in the phase comparison unit, the frequency division value output from the parameter output unit is calculated from the first frequency division value. Since it is a synchronous sweep synthesizer with a second switch that switches to a divided value of 2 and outputs a fixed value during the sweep period, it is calculated based on the value of the start frequency from the first switch before the start of the sweep. After the sweep starts, the second divided value corresponding to the center frequency of the sweep can be output, and the divided value during the sweep period is fixed and stable sweep is performed. be able to There is a result.

  In addition, according to the present invention, since it is a synchronous sweep synthesizer that changes the slope of the sweep by changing the value of the fixed time interval or the value of the specific frequency included in the sweep condition, according to the user's request and application There is an effect that the inclination can be arbitrarily set.

[Summary of Invention]
Embodiments of the present invention will be described with reference to the drawings.
The synchronous sweep synthesizer according to the embodiment of the present invention is provided with a sweep condition that defines a frequency change amount and a time interval (step frequency / time) of the change, and when a sweep start instruction is input, It has a sweep frequency counter that outputs a sweep sync pulse at time intervals and outputs a frequency value that is added by the step frequency in synchronization with the sweep sync pulse. Based on the frequency value output from the sweep frequency counter, the phase The configuration is such that the parameters are output to the comparator and the digital filter to control the VCO, and the frequency can be changed at a high speed with a staircase waveform and a synchronizing pulse synchronized with the sweep timing can be output.

  In addition, the synchronous sweep synthesizer according to the embodiment of the present invention outputs a start frequency value until the synthesizer is locked, and outputs a sweep frequency value that becomes a staircase waveform after being locked. The VCO is controlled based on the frequency value output from the switch, and the sweep is started after the synthesizer is locked, so that a stable sweep can be performed. .

  Furthermore, the synchronous sweep synthesizer according to the embodiment of the present invention is provided with a division ratio fixing switch that fixes the division ratio in accordance with the center frequency of the sweep, and the division ratio is set so that the division ratio does not change during the sweep. Is fixed so that stable sweeping can be performed.

[Configuration of Embodiment: FIG. 1]
The configuration of the synchronous sweep synthesizer according to the embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration block diagram showing a configuration of a synchronous sweep synthesizer according to an embodiment of the present invention.
As shown in FIG. 1, a synchronous sweep synthesizer (present synthesizer) according to an embodiment of the present invention includes a VCO 11, a frequency divider (NN) 12, an LPF (Low Pass Filter) 13, and an AD converter (A / D) 14, a reference clock generator 15, a DA converter (D / A) 22, a voltage output unit 23, an adder 24, and a field programmable gate array (FPGA). A remove 16, a reverse rotation vector multiplication unit 17, a phase time difference detection unit 18, an adder 19, a phase difference cumulative addition unit 20, a loop filter 21, and a parameter output unit 25 are provided. As characteristic features of the synthesizer, a frequency division ratio fixed switch (frequency division ratio fixed SW) 41, a start / sweep frequency change switch (start / sweep frequency change SW) 42, and a sweep frequency cap. It is equipped with a printer 43.

The VCO 11 is a voltage controlled oscillator that oscillates at a desired frequency (450 MHz to 1000 MHz) using the input from the adder 24 as a control voltage.
The frequency divider (NN) 12 divides the output of the VCO 11 into 1 / NN based on the frequency division value (NN) input from the outside, and outputs it to the LPF 13.

The LPF 13 is a filter that allows a low frequency to pass through the signal divided by the frequency divider 12.
The AD converter 14 samples the signal from the LPF 13 with a 40 MHz (fs) clock from the reference clock generation unit 15 to convert the signal from analog to digital, and outputs the signal to the carrier remove 16 of the FPGA.

  The DA converter 22 converts the control signal adjusted and controlled by the FPGA from digital to analog. The signal voltage from the DA converter 22 is 0 to 0.85V.

The voltage output unit 23 outputs a voltage based on the voltage value from the parameter output unit 25, and is configured such that the output voltage rises linearly to a predetermined voltage over time, for example.
The adder 24 corrects the voltage output from the voltage output unit 23 with the control signal output from the DA converter 22 and outputs the corrected voltage as a control voltage to the VCO 11.

  The basic function of the FPGA is to detect a phase difference by comparing a rotation vector at a desired output frequency (set frequency) with a rotation vector of a signal from the AD converter 14, and based on the phase difference, the VCO 11 A control signal for controlling the oscillation frequency is generated.

  The carrier remove 16 performs quadrature detection using a 4 MHz sine wave signal on the sine wave signal specified by the digital signal from the AD converter 14, and generates a frequency signal specified by the digital signal of the AD converter 14. This is means for extracting a rotation vector V that rotates at a frequency that is the difference between the frequency and the frequency of the sine wave signal used for detection.

The reverse rotation vector multiplication unit 17 multiplies the rotation vector V by the reverse rotation vector V ′ output from the parameter output unit 25.
The phase time difference detector 18 detects a phase difference for each sampling time based on the rotation vector V decelerated in the reverse rotation vector multiplier 17. This phase difference becomes a value corresponding to the frequency of the decelerated rotation vector V. The phase time difference detector 18 outputs a lock detection signal to the outside when detecting a lock in the PLL.

The adder 19 subtracts the value of the fine adjustment frequency for approaching the desired oscillation frequency obtained in advance from the output of the phase time difference detector 18 and outputs the phase difference.
The phase difference accumulator 20 accumulates and outputs the output from the adder 19 for a predetermined time. The phase difference accumulating unit 20 includes a filter, and sets damping to an optimum value.
The carrier remove 16, the reverse rotation vector multiplication unit 17, the phase time difference detection unit 18, the adder 19, the phase difference cumulative addition unit 20, and the parameter output unit 25 correspond to the phase comparison unit described in the claims. Yes.

  The loop filter 21 generates data for controlling the VCO based on the cumulative addition value from the phase difference cumulative addition unit 20 and outputs the data as a control signal. The reason why the loop filter 21 is controlled based on the cumulative addition value is to stabilize the output of the loop filter 21.

Based on the input frequency setting information (information on the desired oscillation frequency), the parameter output unit 25 uses the first frequency to the frequency division ratio fixed switch 41 as a frequency parameter so that the frequency is obtained as the output of the VCO 11. Frequency division value (NN (1), not shown), second frequency division value (NN (2), not shown), reverse rotation vector V ′ to the reverse rotation vector multiplier 17 and fine adjustment to the adder 19 The frequency and the voltage value to the voltage output unit 23 are calculated, and the above parameters and the like are output at the calculated timing. The reverse rotation vector V ′ is calculated based on the rotation vector V and frequency setting information. The parameter output unit 25 may read various parameters in advance in a table or the like.
As a feature of the parameter output unit 25 of the synthesizer, the frequency setting information is input via the start / sweep frequency changeover switch 42.

  The frequency division ratio fixing switch 41 corresponds to a second switch recited in the claims, and switches the frequency division value output to the frequency divider 12 in accordance with the switching signal 2 from the outside. Here, a first frequency division value (NN (1)) corresponding to a linear sweep similar to the conventional one and a second frequency division value (NN (1) corresponding to the center frequency of the sweep range, which is a feature of this synthesizer, are used. 2)) is switched and one of them is output. The switching signal 2 is a control signal input from a control device such as a personal computer connected to the outside, and corresponds to the second switching signal recited in the claims.

The start / sweep frequency switching switch 42 corresponds to the first switch recited in the claims, and switches between the output of the sweep frequency counter 43 and the value of the start frequency input from the outside according to the switching signal 1; Either one is output to the parameter output unit 25 as frequency setting information.
The switching signal 1 is a control signal input from a control device such as a personal computer connected to the outside, and corresponds to the first switching signal recited in the claims.

  The sweep frequency counter 43 outputs a sweep synchronization pulse according to a sweep condition input from an external control device, changes the value of the held frequency with a certain frequency width, and sequentially synchronizes with the pulse. Output.

[Configuration of features of this synthesizer; Fig. 2]
Next, the structure of the characteristic part of this synthesizer and the operation of each part will be described with reference to FIG. FIG. 2 is a schematic block diagram of the frequency division ratio fixed switch 41, the start / sweep frequency changeover switch 42, and the sweep frequency counter 43.
As shown in FIG. 2, the start / sweep frequency changeover switch 42 outputs a start frequency value given from an external control device or a frequency value from the sweep frequency counter 43 to the parameter output unit 25 as frequency setting information. .

  The start / sweep frequency switching switch 42 is initially switched to the start frequency side by a switching signal 1 input from the control device. When the switching signal 1 for instructing switching to the sweep frequency counter 43 side is input from the control device, the start / sweep frequency switching switch 42 is switched to the sweep frequency counter 43 side.

  That is, when the lock detection signal from the phase time difference detector 18 is input to the control device in a state where the start / sweep frequency changeover switch 42 is switched to the start frequency side, the switching signal 1 is output from the control device, The start / sweep frequency switching switch 42 is switched to the sweep frequency counter 43 side.

  Thus, until the synthesizer locks, stable sweeping can be performed by controlling the VCO 11 at a given start frequency and starting a sweep after detecting the lock.

  The sweep frequency counter 43 receives a sweep condition (step frequency / time) and a sweep start trigger from an external control device, and outputs a stepped frequency value. The sweep start trigger corresponds to the “trigger for start of sweep” recited in the claims.

The sweep condition defines a time interval at which the frequency is updated and a frequency (step frequency) value to be changed at one time in a frequency changing stepwise, and represents a slope of the sweep.
Here, the sweep condition will be described with reference to FIG. FIG. 3 is a schematic explanatory view showing a sweep condition.
As shown in FIG. 3, for example, if the sweep condition is 100 Hz / 10 μsec, it indicates that the frequency value is added by 100 Hz in accordance with the synchronization pulse every 10 μsec and output. That is, the frequency value increases stepwise by 100 Hz every 10 μsec.
Note that the sweep condition includes information on a sweep start frequency for starting the sweep and a stop frequency for stopping the sweep.

  The sweep start trigger is used to specify the timing for starting the sweep. The sweep start trigger is input from an external control device. It may be a signal or may be manually input after that.

  When a sweep start trigger is input, the sweep frequency counter 43 starts counting, outputs a sweep synchronization pulse at a specific time according to a given sweep condition, and holds it in synchronization with the sweep synchronization pulse. The frequency value is updated by adding the step frequency to the existing frequency value, and the updated frequency value is sequentially output.

  That is, when the sweep frequency counter 43 starts sweeping, since the start / sweep frequency changeover switch 42 has already been switched to the sweep frequency counter 43 side, the frequency value counted up by the sweep frequency counter 43 remains unchanged. It is output to the parameter output unit 25 as frequency setting information.

Based on the frequency setting information input from the start / sweep frequency changeover switch 42, the parameter output unit 25 has a first divided value (NN (1)), a second divided value (NN (2)), and Calculate and output various other frequency parameters.
Here, a method of setting the frequency division value (NN) in the synthesizer will be described.
The parameter output unit 25 outputs a frequency division value to the frequency division ratio fixed switch 41. Normally, the frequency output value is calculated and output as NN (1) every time frequency setting information is input. NN (1) is a frequency division value corresponding to the case of performing a linear sweep as in the prior art.

  Furthermore, as a feature of the synthesizer, the parameter output unit 25 calculates and holds the sweep center frequency based on the values of the sweep start frequency and the stop frequency input from an external control device, although not shown. The frequency division value calculated based on the sweep center frequency is output as NN (2). NN (2) is a frequency division value used during the high-speed sweep, and is a value for performing a stable sweep so that the frequency division ratio does not change during the sweep.

The frequency division ratio fixed switch 41 switches between NN (1) and NN (2) based on the switching signal 2 from the external control device, and outputs either one to the frequency divider 12.
The switching signal 2 from the control device is switched to the NN (1) side before the start of the sweep and is switched to the NN (2) side at the start of the sweep. The signal to be switched to the NN (2) side may be the same signal as the sweep start trigger input to the sweep frequency counter 43.

  That is, when the value of the start frequency immediately after the start of the operation is set, the frequency division ratio fixed switch 41 is switched to the NN (1) side, and the parameter output unit 25 calculates based on the value of the start frequency. When the lock is detected at the start frequency, a switching signal 2 is output from the control device, the frequency division ratio fixed switch is switched to the NN (2) side, and the parameter is output. The output unit 25 outputs the second divided value calculated and held based on the sweep center frequency.

[Operation of features of this synthesizer; Fig. 2]
Next, the operation of the characteristic part of the synthesizer will be described with reference to FIG.
Before the operation starts, the start frequency value is given to the start / sweep frequency changeover switch 42 from the external control device, and the sweep frequency counter 43 has the sweep frequency as a step frequency / holding time, sweep start frequency, and stop frequency. And a sweep start frequency and a stop frequency are set in the parameter output unit 25.

The parameter output unit 25 calculates the sweep center frequency, calculates the frequency division value NN (2) based on the frequency, and holds it.
Further, the start frequency is set as an initial value of the frequency value output by the sweep frequency counter 43.

  At the start of operation, the frequency division ratio fixed switch 41 is switched to the NN (1) side by the switching signal 2, and the start / sweep frequency switching switch 42 is switched to the start frequency side by the switching signal 1.

  In this state, the start / sweep frequency changeover switch 42 outputs the value of the start frequency as frequency setting information to the parameter output unit 25. The parameter output unit 25 uses the frequency division value NN (1) based on the value of the start frequency. ) And various parameters are calculated and output. Since the frequency division ratio fixing switch 41 is switched to the NN (1) side, the frequency division value NN (1) based on the start frequency is output as it is, and the VCO 11 is controlled.

  When the lock detection signal is output from the phase time difference detection unit 18, the control device outputs the switching signal 1 and switches the start / sweep frequency switching switch 42 to the sweep frequency counter 43 side.

  In addition, the control device outputs a sweep start trigger to the sweep frequency counter 43, and further, the control device outputs a switching signal 2 to switch the frequency division ratio fixed switch 41 to the frequency division value NN (2) side.

  When the sweep frequency counter 43 detects the sweep start trigger, the sweep frequency counter 43 starts counting, outputs a synchronous sweep pulse based on the sweep condition, adds the step frequency to the currently set frequency value, and then synchronizes the sweep pulse. The next frequency value is output according to.

  Since the start / sweep frequency changeover switch 42 is switched to the sweep frequency counter 43 side, the frequency setting information counted up every time interval specified by the sweep condition is sequentially input to the parameter output unit 25, The parameter output unit 25 calculates and outputs various parameters accordingly. The parameter output unit 25 may calculate the frequency division value NN (1) according to the frequency setting information, but corresponds to the sweep center frequency via the frequency division ratio fixing switch 41 during the sweep. The frequency division value NN (2) is output in a fixed manner.

  As a result, in this apparatus, frequency setting information that changes in a stepwise manner at high speed is given to the parameter output unit 25. The parameter output unit 25 calculates and outputs various parameters according to the frequency setting information, and also divides the frequency. The value can be fixed to the frequency division value NN (2) corresponding to the sweep center frequency, and a high-speed and stable stepwise sweep can be performed.

  Further, by providing the start / sweep frequency changeover switch 42, the sweep can be started from a state locked at the start frequency, and a stable sweep can be performed.

[Sweep actual measurement waveform; FIGS. 4 to 7]
Next, an actual sweep measurement waveform will be described with reference to FIG. FIG. 4 is a waveform diagram showing an example of the actually measured sweep waveform.
In FIG. 4, the sweep center frequency is 413,663,232 Hz, the sweep frequency (difference between the sweep start frequency and the stop frequency) is 8,800,000 Hz, and the sweep condition (sweep slope) is 440 Hz / 100 μsec. The case is shown as an example.
As shown in FIG. 4, a staircase waveform is realized in which 440 Hz is added every 100 μsec.

Next, another example of the actually measured sweep waveform will be described with reference to FIGS. 5 is a waveform diagram showing another example of the actually measured sweep waveform, FIG. 6 is an enlarged view of the portion (1) in FIG. 5, and FIG. 7 is an enlarged view of the portion (2) in FIG. is there.
FIG. 5 shows a waveform when sweeping while changing the slope of the sweep by combining a plurality of sweep conditions.

  When changing the slope, for example, the first frequency to the second frequency are operated with the first slope (frequency / time), and the second slope to the third frequency is the second slope. Such a sweep condition may be given to the sweep frequency counter 43 from the control device.

  In the example of FIG. 5, the sweep center frequency is 439,500,000 Hz, the sweep frequency is 15,000,000 Hz, and the slope of the gentle slope (sweep slope (1)) is 7500 Hz / 500 μsec, The slope of the steep part (sweep slope (2)) is 7500 Hz / 100 μsec.

  As shown in FIG. 6, in the case of the sweep slope (1), it is recognized that a substantially step-like waveform added by 7500 Hz every 500 μsec is realized on the left side of the screen.

  On the other hand, as shown in FIG. 7, in the case of the sweep slope (2), since the addition is 7500 Hz every 100 μsec, the slope is too steep and does not form a stepped waveform.

  In other words, depending on the user's purpose and application, in the part where you want to change the frequency quickly, even if it does not become a staircase waveform, as a sweep condition with a large slope, change the frequency greatly in a short time, and in the part you want to change gradually By setting the sweep condition with a small slope, a highly accurate staircase waveform can be output, and the sweep condition can be arbitrarily set according to the user's convenience.

[Effect of the embodiment]
According to the synchronous sweep synthesizer according to the embodiment of the present invention, the sweep frequency counter 43 is given a sweep condition that defines the frequency change amount and the time interval (step frequency / time) of the change, and the sweep start trigger. Is input, the sweep synchronization pulse is output at the time interval, the frequency value counted up by the step frequency is output in synchronization with the pulse, and the parameter output unit 25 outputs the frequency of the frequency from the sweep frequency counter 43. Since various parameters are calculated and output based on the values, the synthesizer output can be swept at a high speed with a staircase waveform, and a synchronization pulse synchronized with the sweep timing can be output. .

  Further, according to the synthesizer, start / sweep frequency switching for outputting either the value of the start frequency given from the outside or the value of the frequency outputted from the sweep frequency counter 43 to the parameter output unit 25 as frequency setting information. A switch 42 is provided, and the start / sweep frequency changeover switch 42 outputs the value of the start frequency given from the outside until the lock is detected, and switches based on the switching signal 1 inputted when the lock is detected, Since the frequency value from the sweep frequency counter 43 is output, the start frequency is output until the lock is detected, and the stepped sweep frequency can be output after the lock is detected. There is an effect that can be performed.

  Further, according to the synthesizer, the parameter output unit 25 uses the frequency division value NN (1) calculated based on the frequency setting information or the frequency division value NN (2) calculated based on the center frequency of the sweep. The frequency division ratio fixed switch 41 that switches and outputs one as a frequency division value from the parameter output unit 35 outputs NN (1) until the sweep is started, and when the sweep is started, the switching signal 2 is output. Since NN (2) is output on the basis of the frequency, the frequency division value can be fixed at a value corresponding to the center frequency of the sweep during the sweep, and stable without being changed in the middle. There is an effect that sweeping can be performed.

  The present invention is particularly suitable for a synchronous sweep synthesizer that can sweep the output frequency at a high speed and can output a pulse synchronized with the sweep.

It is a block diagram which shows the structure of the synchronous sweep synthesizer which concerns on embodiment of this invention. 3 is a schematic block diagram of a frequency division ratio fixing switch 41, a start / sweep frequency changeover switch 42, and a sweep frequency counter 43. FIG. It is a schematic explanatory view showing a sweep condition. It is a wave form diagram which shows the example of a sweep measurement waveform. It is a wave form diagram which shows the example of another sweep measurement waveform. It is an enlarged view of the (1) part of FIG. It is an enlarged view of the (2) part of FIG. It is a block diagram of a conventional frequency synthesizer. It is model explanatory drawing which shows the sweep by a sawtooth wave. It is a schematic explanatory drawing of the sweep by a staircase waveform.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... VCO, 2 ... Frequency divider, 3 ... Phase comparator, 4 ... Loop filter, 11 ... VCO, 12 ... Frequency divider, 13 ... LPF, 14 ... AD converter, 15 ... Reference clock generation part, 16 ... Carrier remove, 17 ... Reverse rotation vector multiplication unit, 18 ... Phase time difference detection unit, 19 ... Adder, 20 ... Phase difference cumulative addition unit, 21 ... Loop filter, 22 ... DA converter, 23 ... Voltage output unit, 24 ... adder, 25 ... parameter output unit, 41 ... frequency division ratio fixed switch, 42 ... start / sweep frequency changeover switch, 43 ... sweep frequency counter

Claims (6)

A voltage-controlled oscillator that oscillates a frequency signal according to an input control voltage; a frequency divider that divides the oscillation frequency signal; an AD converter that performs analog / digital conversion on the frequency-divided signal; and the analog A phase comparison unit that compares the phase of a digital-converted signal and a desired frequency signal and outputs a phase difference signal corresponding to the phase difference, and a control signal that controls the voltage controlled oscillator based on the phase difference signal And a DA converter for digital / analog conversion of the control signal,
The voltage-controlled oscillator provides a specific start frequency until lock is detected by the phase comparison unit, and after the lock is detected, provides a sweep frequency that becomes a staircase waveform,
The synchronous sweep synthesizer, wherein the phase comparison unit outputs a sweep synchronous pulse synchronized with the timing of the sweep.   2. The synchronous sweep synthesizer according to claim 1, wherein the sweep frequency is formed by increasing a specific frequency at regular time intervals.   3. The synchronous sweep synthesizer according to claim 2, wherein the sweep frequency is changed by changing a predetermined time interval or a specific frequency. A voltage-controlled oscillator that oscillates a frequency signal according to an input control voltage; a frequency divider that divides the oscillation frequency signal; an AD converter that performs analog / digital conversion on the frequency-divided signal; and the analog A phase comparison unit that compares the phase of a digital-converted signal and a desired frequency signal and outputs a phase difference signal corresponding to the phase difference, and a control signal that controls the voltage controlled oscillator based on the phase difference signal And a DA converter for digital / analog conversion of the control signal,
The phase comparison unit, based on the input frequency setting information, a parameter output unit that calculates a frequency division value necessary to generate a phase difference signal;
When a sweep start trigger is detected, a sweep synchronization pulse is output at the predetermined time interval based on a sweep condition including a predetermined constant time interval value and a specific frequency value, and the held frequency is A sweep frequency counter that outputs a frequency value obtained by adding the specific frequency to the value in synchronization with the sweep synchronization pulse;
When the first switching signal input by lock detection at the start frequency is detected, the frequency setting information output to the parameter output unit is switched from a specific start frequency value to a frequency value from the sweep frequency counter. A synchronous sweep synthesizer comprising: a first switch that outputs the first switch; The parameter output unit calculates the first divided value based on the frequency setting information input from the first switch, and calculates and holds the second divided value based on the value of the center frequency of the sweep. Parameter output unit
The phase comparator
When the second switching signal input at the start of the sweep is detected, the frequency division value output from the parameter output unit is switched from the first frequency division value to the second frequency division value, and is fixed during the sweep period. 5. The synchronous sweep synthesizer according to claim 4, further comprising a second switch for outputting.   The synchronous sweep synthesizer according to claim 4 or 5, wherein a slope of the sweep is changed by changing a value of a certain time interval or a value of a specific frequency included in the sweep condition.

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