JP2008187193A - Wiring board - Google Patents

Wiring board Download PDF

Info

Publication number
JP2008187193A
JP2008187193A JP2008073872A JP2008073872A JP2008187193A JP 2008187193 A JP2008187193 A JP 2008187193A JP 2008073872 A JP2008073872 A JP 2008073872A JP 2008073872 A JP2008073872 A JP 2008073872A JP 2008187193 A JP2008187193 A JP 2008187193A
Authority
JP
Japan
Prior art keywords
thick film
resistor
film resistor
insulating
wiring conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008073872A
Other languages
Japanese (ja)
Other versions
JP4741624B2 (en
Inventor
Akira Takeo
明 竹尾
Masato Hiwatari
正人 日渡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2008073872A priority Critical patent/JP4741624B2/en
Publication of JP2008187193A publication Critical patent/JP2008187193A/en
Application granted granted Critical
Publication of JP4741624B2 publication Critical patent/JP4741624B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve trim accuracy of a thick-film resistor. <P>SOLUTION: A wiring board has an insulation substrate 1, a wiring conductor 2 and a thick-film resistor 3. The wiring board also has an insulation film 4, a plated metal film and a dummy resistor 8. The thick-film resistor 3 is electrically connected to the wiring conductor 2, and is disposed on the insulation substrate 1. The thick-film resistor 3 is partially covered with the insulation film 4. A part not covered with the insulation film 4 of the thick-film resistor 3 is covered with the plated metal film. The dummy resistor 8 is electrically independent from the thick-film resistor 3, is arranged adjacent to the thick-film resistor 3, and is disposed on the insulation substrate 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、厚膜抵抗体を具備する配線基板に関するものである。   The present invention relates to a wiring board having a thick film resistor.

従来、例えば半導体集積回路素子等の電子素子を搭載するための配線基板として、酸化アルミニウム質焼結体等の電気絶縁材料から成る絶縁基体の表面にタングステンやモリブデン等の金属メタライズから成る配線導体と、この配線導体に電気的に接続されたタングステン−レニウム合金等の抵抗体メタライズから成る厚膜抵抗体とを被着させて成る配線基板が知られている。   Conventionally, as a wiring board for mounting an electronic element such as a semiconductor integrated circuit element, a wiring conductor made of a metal metallization such as tungsten or molybdenum on the surface of an insulating base made of an electrically insulating material such as an aluminum oxide sintered body There is known a wiring board formed by depositing a thick film resistor made of a resistor metallization such as a tungsten-rhenium alloy electrically connected to the wiring conductor.

このような配線基板は、一般的にはセラミックグリーンシート積層法によって製作され、具体的には、例えばドクタブレード法等のシート成形技術により形成された複数枚のセラミックグリーンシートを準備し、次いでこれらのセラミックグリーンシートに適当な打ち抜き加工を施すとともに配線導体用の金属ペーストおよび厚膜抵抗体用の抵抗体ペーストを必要なパターンに印刷塗布し、次いでこれらのセラミックグリーンシートを上下に積層するとともに適当な大きさ・形状に切断して配線基板用の生セラミック成形体を得て、最後にこの生セラミック成形体を高温で焼成することによって製作されている。   Such a wiring board is generally manufactured by a ceramic green sheet laminating method. Specifically, for example, a plurality of ceramic green sheets formed by a sheet forming technique such as a doctor blade method are prepared, and then these are prepared. Appropriate punching processing is applied to the ceramic green sheets of the above, and a metal paste for wiring conductors and a resistor paste for thick film resistors are printed and applied in a required pattern, and then these ceramic green sheets are laminated on top and bottom The raw ceramic molded body for a wiring board is obtained by cutting into a large size and shape, and finally the raw ceramic molded body is fired at a high temperature.

なお、このような配線基板においては、一般的には、配線導体はその露出表面がニッケルめっき膜および金メッキ膜から成るめっき金属膜により順次被覆されており、厚膜抵抗体は絶縁基体と実質的に同一の材料から成る絶縁膜でその全体が覆われている。配線導体はめっき金属膜で被覆されることにより、その酸化腐食が有効に防止されるとともに電子素子や外部電気回路基板等との接続が容易かつ強固なものとなる。また、厚膜抵抗体は絶縁基体と実質的に同一材料の絶縁膜で覆われることにより、その電気抵抗値に影響を受けることなくその酸化腐食が防止される。このように配線導体の露出表面をめっき金属膜で被覆するには、無電解めっき法や電解めっき法が採用される。また、厚膜抵抗体を絶縁膜で覆うには、絶縁基体用のセラミックグリーンシートに厚膜抵抗体用の抵抗体ペーストを印刷塗布した後、このセラミックグリーンシート上に抵抗体ペーストを覆うようにしてセラミックグリーンシートと実質的に同一のセラミック粉末を含有するセラミックペーストを印刷塗布し、これを配線基板用の生セラミック成形体とともに同時焼成する方法が採用される。この場合、絶縁膜は絶縁基体と実質的に同一の材料から成り、絶縁基体と同時焼成により形成されることから、絶縁基体に極めて強固に接合するとともにその形成が極めて容易である。   In such a wiring board, generally, the exposed surface of the wiring conductor is sequentially covered with a plated metal film made of a nickel plating film and a gold plating film, and the thick film resistor is substantially the same as the insulating substrate. The whole is covered with an insulating film made of the same material. By covering the wiring conductor with the plated metal film, the oxidative corrosion is effectively prevented, and the connection with the electronic element, the external electric circuit board, and the like becomes easy and strong. Further, the thick film resistor is covered with an insulating film made of substantially the same material as that of the insulating base, so that the oxidative corrosion is prevented without being affected by the electric resistance value. Thus, in order to coat the exposed surface of the wiring conductor with the plated metal film, an electroless plating method or an electrolytic plating method is employed. Also, in order to cover the thick film resistor with an insulating film, the resistor paste for the thick film resistor is printed on the ceramic green sheet for the insulating substrate, and then the resistor paste is covered on the ceramic green sheet. In this method, a ceramic paste containing ceramic powder substantially the same as the ceramic green sheet is printed and applied, and this is simultaneously fired together with a green ceramic molded body for a wiring board. In this case, since the insulating film is made of substantially the same material as the insulating base and is formed by simultaneous firing with the insulating base, the insulating film is extremely strongly bonded to the insulating base and is very easy to form.

しかしながら、この従来の配線基板によると、厚膜抵抗体は絶縁基体用のセラミックグリーンシートに厚膜抵抗体用の抵抗体ペーストをスクリーン印刷法により所定のパターンに印刷塗布しておき、これを配線基板用の生セラミック成形体と同時に焼成することによって形成されており、印刷時のばらつきによりその厚みに２〜３μｍ程度のばらつきが発生しやすい。このような厚みのばらつきは厚膜抵抗体の電気抵抗値にばらつきを発生させ、抵抗体としての機能を十分に発揮することができない場合がある。そこで、厚膜抵抗体を絶縁膜上からレーザトリミングして厚膜抵抗体の抵抗値を調整し、抵抗体としての機能を正常に発揮できるようにすることが考えられる。ところが、厚膜抵抗体を覆う絶縁膜は不透明であるため厚膜抵抗体を絶縁膜上から直接見ることができず、したがって厚膜抵抗体を絶縁膜上から正確にレーザトリミングすることが困難であるという問題点を有していた。   However, according to this conventional wiring board, the thick film resistor is printed on the ceramic green sheet for the insulating substrate by applying the resistor paste for the thick film resistor in a predetermined pattern by the screen printing method. It is formed by firing at the same time as the green ceramic molded body for the substrate, and due to variations during printing, variations in thickness of about 2 to 3 μm are likely to occur. Such a variation in thickness causes a variation in the electric resistance value of the thick film resistor, and the function as the resistor may not be sufficiently exhibited. Therefore, it is conceivable to perform laser trimming of the thick film resistor from above the insulating film to adjust the resistance value of the thick film resistor so that the function as the resistor can be exhibited normally. However, since the insulating film covering the thick film resistor is opaque, the thick film resistor cannot be seen directly from above the insulating film. Therefore, it is difficult to accurately laser-trim the thick film resistor from above the insulating film. There was a problem that there was.

本発明は、かかる従来の問題点に鑑み案出されたものであり、その目的は厚膜抵抗体を絶縁膜上から正確にレーザトリミングすることが可能な配線基板を提供することにある。   The present invention has been devised in view of such conventional problems, and an object thereof is to provide a wiring board capable of accurately laser-trimming a thick film resistor from an insulating film.

本発明の一つの態様によれば、配線基板は、絶縁基体、配線導体および厚膜抵抗体を有している。配線基板は、絶縁膜、めっき金属膜およびダミー抵抗体をさらに有している。配線導体は、絶縁基体に設けられている。厚膜抵抗体は、配線導体に電気的に接続されており、絶縁基体に設けられている。絶縁膜は、厚膜抵抗体を部分的に被覆している。めっき金属膜は、厚膜抵抗体の絶縁膜によって被覆されていない部分を覆っている。ダミー抵抗体は、厚膜抵抗体とは電気的に独立しており、厚膜抵抗体に近接して配置されており、絶縁基体に設けられている。   According to one aspect of the present invention, the wiring board includes an insulating base, a wiring conductor, and a thick film resistor. The wiring board further includes an insulating film, a plated metal film, and a dummy resistor. The wiring conductor is provided on the insulating base. The thick film resistor is electrically connected to the wiring conductor and is provided on the insulating base. The insulating film partially covers the thick film resistor. The plated metal film covers a portion of the thick film resistor that is not covered with the insulating film. The dummy resistor is electrically independent of the thick film resistor, is disposed in proximity to the thick film resistor, and is provided on the insulating substrate.

本発明の配線基板によれば、厚膜抵抗体はその一部が絶縁膜から露出しているので、この露出部を厚膜抵抗体の位置の目安とすることにより、厚膜抵抗体を絶縁膜上から正確にレーザトリミングすることができる。また、この露出部はめっき金属膜で被覆されていることから、めっき金属膜によりその酸化腐食が有効に防止されるとともにその認識性が良好となる。   According to the wiring board of the present invention, since the thick film resistor is partially exposed from the insulating film, the thick film resistor is insulated by using the exposed portion as a guide for the position of the thick film resistor. Laser trimming can be accurately performed from above the film. Moreover, since this exposed part is coat | covered with the plating metal film, the oxidation corrosion is effectively prevented by the plating metal film, and the recognition property is improved.

次に、本発明を添付の図面に基づき詳細に説明する。   Next, the present invention will be described in detail with reference to the accompanying drawings.

図１は、本発明を半導体集積回路素子搭載用の配線基板に適用した場合の実施の形態の一例を示す断面図であり、図２は図１に示す配線基板の上面図、図３は図１に示す配線基板の要部拡大断面図である。これらの図中、１は絶縁基体、２は配線導体、３は厚膜抵抗体、４は絶縁膜である。   FIG. 1 is a cross-sectional view showing an example of an embodiment when the present invention is applied to a wiring board for mounting a semiconductor integrated circuit element, FIG. 2 is a top view of the wiring board shown in FIG. 1, and FIG. 2 is an enlarged cross-sectional view of a main part of the wiring board shown in FIG. In these drawings, 1 is an insulating substrate, 2 is a wiring conductor, 3 is a thick film resistor, and 4 is an insulating film.

絶縁基体１は、図１および図２に示すように、その上面中央部に半導体集積回路素子５を収容するための段状の凹部１ａを有する略四角平板状であり、その凹部１ａの底面には半導体集積回路素子５がろう材やガラス・樹脂等の接着剤を介して取着固定される。なお、絶縁基体１は、酸化アルミニウム質焼結体や窒化アルミニウム質焼結体・ムライト質焼結体・炭化珪素質焼結体・窒化珪素質焼結体・ガラスセラミックス等の電気絶縁材料から成り、例えば酸化アルミニウム質焼結体から成る場合であれば、酸化アルミニウム・酸化珪素・酸化マグネシウム・酸化カルシウム等のセラミック原料粉末に適当な有機バインダ・溶剤を添加混合して得たセラミックスラリを従来周知のドクタブレード法によりシート状となすとともに、これに適当な打ち抜き加工を施すことにより絶縁基体１用の複数枚のセラミックグリーンシートを得、次いでこれらのセラミックグリーンシートを上下に積層するとともに適当な形状・大きさに切断して絶縁基体１用の生セラミック成形体となし、しかる後、この成形体を還元雰囲気中約1600℃の温度で焼成することによって製作される。   As shown in FIGS. 1 and 2, the insulating substrate 1 has a substantially square plate shape having a stepped recess 1a for accommodating the semiconductor integrated circuit element 5 at the center of the upper surface, and is formed on the bottom surface of the recess 1a. The semiconductor integrated circuit element 5 is attached and fixed via an adhesive such as a brazing material, glass or resin. The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, a silicon carbide sintered body, a silicon nitride sintered body, or a glass ceramic. For example, in the case of an aluminum oxide sintered body, a ceramic slurry obtained by adding and mixing an appropriate organic binder and solvent to ceramic raw material powders such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide has been well known. A plurality of ceramic green sheets for the insulating substrate 1 are obtained by applying an appropriate punching process to the sheet by the doctor blade method of the above, and then laminating these ceramic green sheets vertically and in an appropriate shape. -Cut into a size to form a green ceramic molded body for the insulating substrate 1, and then form the molded body. It is manufactured by firing at a temperature of about 1600 ° C. in the original atmosphere.

また、絶縁基体１にはその凹部１ａ内の段上から下面に導出する複数のメタライズ配線導体２が被着形成されている。このメタライズ配線導体２は、絶縁基体１に搭載される半導体集積回路素子５を外部電気回路に接続するための導電路として機能し、例えば信号用のメタライズ配線導体２ａと接地用のメタライズ配線導体２ｂとを含んでいる。そして、メタライズ配線導体２の凹部１ａ部位には半導体集積回路素子５の対応する各電極（信号用電極・接地用電極等）がボンディングワイヤ６を介して電気的に接続され、メタライズ配線導体２の絶縁基体１下面に導出した部位は外部電気回路基板の配線導体に半田等を介して電気的に接続される。   In addition, a plurality of metallized wiring conductors 2 are formed on the insulating substrate 1 so as to be led out from the top to the bottom in the recess 1a. The metallized wiring conductor 2 functions as a conductive path for connecting the semiconductor integrated circuit element 5 mounted on the insulating substrate 1 to an external electric circuit. For example, the metallized wiring conductor 2a for signal and the metallized wiring conductor 2b for grounding are used. Including. Then, corresponding electrodes (signal electrodes, grounding electrodes, etc.) of the semiconductor integrated circuit element 5 are electrically connected to the concave portion 1a portion of the metallized wiring conductor 2 through bonding wires 6. The part led out to the lower surface of the insulating substrate 1 is electrically connected to the wiring conductor of the external electric circuit board via solder or the like.

なお、メタライズ配線導体２は、タングステンやモリブデン・銅・銀等の金属粉末メタライズから成り、タングステン等の金属粉末に適当な有機バインダ・溶剤を添加混合して得た金属ペーストを絶縁基体１用のセラミックグリーンシートに従来周知のスクリーン印刷法により所定のパターンに印刷塗布し、これを絶縁基体１用の生セラミック成形体とともに同時焼成することによって絶縁基体１の凹部１ａ内の段上から下面にかけて導出するように被着形成される。   The metallized wiring conductor 2 is made of metal powder metallization such as tungsten, molybdenum, copper, or silver, and a metal paste obtained by adding and mixing an appropriate organic binder / solvent to metal powder such as tungsten is used for the insulating substrate 1. The ceramic green sheet is printed and applied in a predetermined pattern by a conventionally known screen printing method, and this is co-fired together with a green ceramic molded body for the insulating base 1 to derive from the step to the bottom in the recess 1a of the insulating base 1. It is formed to adhere.

またさらに図３に示すように、メタライズ配線導体２の露出表面には通常であれば１〜10μｍ程度の厚みのニッケルめっき膜と0.1 〜３μｍ程度の厚みの金めっき膜とから成るめっき金属膜７ａが従来周知の電解めっき法や無電解めっき法により被着されており、これによってメタライズ配線導体２の酸化腐食を防止するとともにメタライズ配線導体２とボンディングワイヤ６および半田等との接続を容易かつ強固なものとしている。   Furthermore, as shown in FIG. 3, the exposed surface of the metallized wiring conductor 2 is usually a plated metal film 7a comprising a nickel plating film having a thickness of about 1 to 10 μm and a gold plating film having a thickness of about 0.1 to 3 μm. Is deposited by a well-known electrolytic plating method or electroless plating method, thereby preventing oxidative corrosion of the metallized wiring conductor 2 and easily and firmly connecting the metallized wiring conductor 2 to the bonding wire 6 and solder. It is supposed to be.

また、絶縁基体１には凹部１ａの段上に、信号用のメタライズ配線導体２ａと接地用のメタライズ配線導体２ｂとの間を電気的に接続するようにして厚膜抵抗体３が被着形成されている。厚膜抵抗体３は、信号用のメタライズ配線導体２ａと接地用のメタライズ配線導体２ｂとの間を電気的に接続することにより信号用のメタライズ配線導体２ａを電気的に終端させてインピーダンス整合を行う終端抵抗として機能し、これにより信号用のメタライズ配線導体２ａに伝播する信号の反射が低減され、半導体集積回路素子５を正常に作動させることを可能としている。   Further, a thick film resistor 3 is formed on the insulating substrate 1 so as to be electrically connected between the metallized wiring conductor 2a for signal and the metallized wiring conductor 2b for grounding on the step of the recess 1a. Has been. The thick film resistor 3 electrically terminates the signal metallization wiring conductor 2a by electrically connecting the signal metallization wiring conductor 2a and the grounding metallization wiring conductor 2b to perform impedance matching. It functions as a terminating resistor to be performed, whereby the reflection of the signal propagating to the signal metallized wiring conductor 2a is reduced, and the semiconductor integrated circuit element 5 can be normally operated.

このような厚膜抵抗体３は、例えばタングステン−レニウム合金等の抵抗体粉末メタライズから成り、タングステン−レニウム合金から成る場合であれば、タングステン粉末およびレニウム粉末に適当な有機バインダ・溶剤を添加混合して得た抵抗体ペーストをメタライズ配線導体２用の金属ペーストが印刷塗布された絶縁基体１用のセラミックグリーンシートに従来周知のスクリーン印刷法により所定のパターンに印刷塗布し、これを絶縁基体１用の生セラミック成形体とともに同時焼成することによって絶縁基体１の凹部１ａ段上に信号用のメタライズ配線導体２ａと接地用のメタライズ配線導体２ｂとの間を電気的に接続するようにして被着形成される。   Such a thick film resistor 3 is made of, for example, a resistor powder metallization such as a tungsten-rhenium alloy, and if it is made of a tungsten-rhenium alloy, an appropriate organic binder / solvent is added to the tungsten powder and the rhenium powder. The resistor paste obtained in this manner is printed and applied in a predetermined pattern on the ceramic green sheet for the insulating substrate 1 on which the metal paste for the metallized wiring conductor 2 is printed and applied by a conventionally known screen printing method. By simultaneously firing together with the green ceramic molded body, the metallized wiring conductor 2a for signal and the metallized wiring conductor 2b for grounding are deposited on the stepped portion 1a of the insulating base 1 so as to be electrically connected. It is formed.

なお、厚膜抵抗体３はトリミング後の抵抗値が所定の抵抗値となるようにその厚み・幅・長さが選定され、例えば終端抵抗として使用される場合であれば、一般的にはトリミング後の抵抗値が約50Ωとなるように設定される。このような厚膜抵抗体３はその厚みが５μｍ未満であると、厚膜抵抗体３に断線が発生しやすくなり、他方、50μｍを超えると、絶縁基体１から剥離しやすくなる。従って、厚膜抵抗体３の厚みは５〜50μｍの範囲が好ましい。また厚膜抵抗体３はその幅が0.05ｍｍ未満であると、厚膜抵抗体３に断線が発生しやすくなり、他方、１ｍｍを超えると、絶縁基体１上に厚膜抵抗体３を効率よく配置することが困難となる傾向にある。従って、厚膜抵抗体３の幅は0.05〜１ｍｍの範囲が好ましい。さらに、厚膜抵抗体３はその長さが0.1 ｍｍ未満であると、抵抗体としての所定の抵抗値を得ることが困難であるとともに厚膜抵抗体３のトリミングが困難となる傾向にあり、他方、100 ｍｍを超えると、絶縁基体１上に厚膜抵抗体３を効率よく配置することが困難となる傾向にある。したがって、厚膜抵抗体３の長さは0.1 〜100 ｍｍの範囲が好ましい。   The thickness, width and length of the thick film resistor 3 are selected so that the resistance value after trimming becomes a predetermined resistance value. It is set so that the later resistance value is about 50Ω. When such a thick film resistor 3 has a thickness of less than 5 μm, disconnection of the thick film resistor 3 tends to occur. On the other hand, when the thickness exceeds 50 μm, the thick film resistor 3 easily peels from the insulating substrate 1. Therefore, the thickness of the thick film resistor 3 is preferably in the range of 5 to 50 μm. Further, if the width of the thick film resistor 3 is less than 0.05 mm, the thick film resistor 3 is likely to be disconnected. On the other hand, if the width exceeds 1 mm, the thick film resistor 3 is efficiently disposed on the insulating substrate 1. It tends to be difficult to place. Therefore, the width of the thick film resistor 3 is preferably in the range of 0.05 to 1 mm. Furthermore, when the thickness of the thick film resistor 3 is less than 0.1 mm, it is difficult to obtain a predetermined resistance value as the resistor and it is difficult to trim the thick film resistor 3. On the other hand, when it exceeds 100 mm, it tends to be difficult to efficiently dispose the thick film resistor 3 on the insulating substrate 1. Therefore, the length of the thick film resistor 3 is preferably in the range of 0.1 to 100 mm.

なお、絶縁基体１には図２に示すように、これらの厚膜抵抗体３に近接して電気的に独立したダミー抵抗体８を各厚膜抵抗体３およびダミー抵抗体８の隣接間隔が略均等となるように厚膜抵抗体３と同じ材料で同時に被着形成しておくと、スクリーン印刷に起因する厚膜抵抗体３の厚みばらつきが小さいものとなるとともに、焼成時における厚膜抵抗体３からの抵抗体成分の不均一な拡散が抑制され、厚膜抵抗体３の電気抵抗値が安定したものとなる。したがって、絶縁基体１には、厚膜抵抗体３に近接して電気的に独立したダミー抵抗体８を各厚膜抵抗体３およびダミー抵抗体８の隣接間隔が略均等となるように厚膜抵抗体３と同じ材料で同時に被着形成しておくことが好ましい。   As shown in FIG. 2, the insulating base 1 has dummy resistors 8 that are electrically isolated from each other in the vicinity of the thick film resistors 3, and the adjacent distances between the thick film resistors 3 and the dummy resistors 8 are different from each other. If the same material as that of the thick film resistor 3 is deposited simultaneously so as to be substantially uniform, the thickness variation of the thick film resistor 3 due to screen printing becomes small, and the thick film resistance during firing is reduced. The uneven diffusion of the resistor component from the body 3 is suppressed, and the electric resistance value of the thick film resistor 3 becomes stable. Accordingly, the insulating base 1 is provided with a dummy resistor 8 which is electrically isolated and close to the thick film resistor 3 so that the adjacent distances between the thick film resistors 3 and the dummy resistors 8 are substantially equal. It is preferable to deposit and form the same material as the resistor 3 at the same time.

また、絶縁基体１には凹部１ａの段上に各厚膜抵抗体３の例えば長さ方向の中央部を部分的に露出させるようにして厚膜抵抗体３を覆う絶縁膜４が被着されている。   Further, an insulating film 4 covering the thick film resistor 3 is deposited on the insulating substrate 1 so as to partially expose, for example, the central portion of each thick film resistor 3 in the longitudinal direction on the step of the recess 1a. ing.

絶縁膜４は、絶縁基体１と実質的に同じ材料から形成されており、絶縁基体１用のセラミックグリーンシートに含有されるセラミック原料粉末に適当な有機バインダ・溶剤を添加混合して得たセラミックペーストを厚膜抵抗体３用の抵抗体ペーストが印刷塗布された絶縁基体１用のセラミックグリーンシートに従来周知のスクリーン印刷法により所定パターンに印刷塗布し、これを絶縁基体１用の生セラミック成形体とともに同時焼成することによって絶縁基体１の凹部１ａ段上に厚膜抵抗体３の長さ方向の中央部を部分的に露出させるようにして被着形成される。この場合、絶縁膜４は絶縁基体１と実質的に同一の材料から成り、絶縁基体と同時焼成により形成されることから、絶縁基体１に極めて強固に接合され、熱膨張係数の相違等に起因して剥離が発生するようなことはない。また、絶縁膜４は絶縁基体１と同時焼成により形成されるので、その形成が極めて容易である。   The insulating film 4 is formed of substantially the same material as that of the insulating substrate 1, and is a ceramic obtained by adding and mixing an appropriate organic binder and solvent to the ceramic raw material powder contained in the ceramic green sheet for the insulating substrate 1. The paste is printed and applied in a predetermined pattern on the ceramic green sheet for the insulating substrate 1 on which the resistor paste for the thick film resistor 3 is printed and applied by a conventionally known screen printing method, and this is formed into a green ceramic for the insulating substrate 1. By co-firing with the body, the thick film resistor 3 is deposited on the stepped portion 1a of the insulating substrate 1 so that the central portion in the length direction is partially exposed. In this case, the insulating film 4 is made of substantially the same material as that of the insulating base 1 and is formed by simultaneous firing with the insulating base 1. Therefore, the insulating film 4 is extremely strongly bonded to the insulating base 1 and is caused by a difference in thermal expansion coefficient. As a result, peeling does not occur. In addition, since the insulating film 4 is formed by simultaneous firing with the insulating substrate 1, its formation is very easy.

このように絶縁膜４は、厚膜抵抗体３の中央部等の一部を部分的に露出させるようにして厚膜抵抗体３を覆うことにより、絶縁膜４で覆われた部分の厚膜抵抗体３が酸化腐食するのを有効に防止するとともに、厚膜抵抗体３の露出部をレーザトリミングの位置決めの目安とすることにより厚膜抵抗体３を絶縁膜４上から正確にレーザトリミングすることを可能としている。   As described above, the insulating film 4 covers the thick film resistor 3 so as to partially expose a central portion or the like of the thick film resistor 3, so that the thick film of the portion covered with the insulating film 4 is covered. The resistor 3 is effectively prevented from being oxidatively corroded, and the exposed portion of the thick film resistor 3 is used as a guide for positioning for laser trimming, so that the thick film resistor 3 is accurately laser trimmed from above the insulating film 4. Making it possible.

なお、絶縁膜４はその厚みが５μｍ未満では、絶縁膜４中にピンホール等の欠陥が発生して厚膜抵抗体３を良好に保護することができなくなる危険性が大きくなり、他方、50μｍを超えると、絶縁膜４が厚くなりすぎるため絶縁膜４の上から厚膜抵抗体３をレーザトリミングすることが困難となる傾向にある。従って、絶縁膜５の厚みは５〜50μｍの範囲が好ましい。   If the thickness of the insulating film 4 is less than 5 μm, there is a high risk that defects such as pinholes will occur in the insulating film 4 and the thick film resistor 3 cannot be well protected, while the thickness of the insulating film 4 is 50 μm. If the thickness exceeds 1, the insulating film 4 becomes too thick, and it tends to be difficult to laser trim the thick film resistor 3 from above the insulating film 4. Therefore, the thickness of the insulating film 5 is preferably in the range of 5 to 50 μm.

また、厚膜抵抗体３は、図３に要部拡大断面図で示すように、その露出部がニッケルめっき膜および金めっき膜から成るめっき金属膜７ｂで被覆されている。   The thick film resistor 3 is covered with a plated metal film 7b made of a nickel plating film and a gold plating film, as shown in an enlarged cross-sectional view of the main part in FIG.

厚膜抵抗体３はその露出部がめっき金属膜７ｂで被覆されていることから、めっき金属膜７ｂによって露出部の酸化腐食が有効に防止されるとともに絶縁基体１および絶縁膜４に対する露出部のコントラスト比が大きくなり露出部の認識性が良好なものとなる。そして、厚膜抵抗体３は、その中央部が露出していることから、この露出部を例えば画像認識装置により確認させることにより厚膜抵抗体３の位置を正確に把握することができ、その結果、厚膜抵抗体３を正確にレーザトリミングすることができる。   Since the exposed portion of the thick film resistor 3 is coated with the plated metal film 7b, the exposed portion of the exposed portion with respect to the insulating base 1 and the insulating film 4 is effectively prevented by the plated metal film 7b. The contrast ratio is increased and the recognizability of the exposed part is improved. Since the thick film resistor 3 is exposed at the center, the position of the thick film resistor 3 can be accurately grasped by checking the exposed portion with, for example, an image recognition device. As a result, the thick film resistor 3 can be laser trimmed accurately.

なお、厚膜抵抗体３は絶縁膜４からの露出面積が厚膜抵抗体３の面積の50％を超えると、厚膜抵抗体３の露出部に被着させるめっき金属膜７ｂによって厚膜抵抗体３の電気抵抗値が低くなりすぎ、そのため所定の抵抗値を得ることが困難となる傾向にある。したがって、厚膜抵抗体３の絶縁膜４からの露出面積は厚膜抵抗体３の面積の50％以下であることが好ましい。また、厚膜抵抗体３の露出部を被覆するめっき金属膜７ｂは、メタライズ配線導体２の露出表面にめっき金属膜７ａを被着させる際に、これと同時に被着させればよい。   When the exposed area from the insulating film 4 exceeds 50% of the area of the thick film resistor 3, the thick film resistor 3 is thickened by the plated metal film 7b to be deposited on the exposed portion of the thick film resistor 3. The electric resistance value of the body 3 becomes too low, and it tends to be difficult to obtain a predetermined resistance value. Therefore, the exposed area of the thick film resistor 3 from the insulating film 4 is preferably 50% or less of the area of the thick film resistor 3. Further, the plated metal film 7b covering the exposed portion of the thick film resistor 3 may be deposited simultaneously with the deposition of the plated metal film 7a on the exposed surface of the metallized wiring conductor 2.

かくして、本発明の配線基板によれば、厚膜抵抗体３の露出部をめっき金属膜７ｂで被覆させた後、厚膜抵抗体３の露出部を目安として絶縁膜４の上から厚膜抵抗体３をレーザトリミングして抵抗値を調整し、しかる後、凹部１ａ底面に半導体集積回路素子５を取着固定するとともに、この半導体集積回路素子５の各電極をボンディングワイヤ６を介して対応するメタライズ配線導体２に電気的に接続し、最後に絶縁基体１の上面に凹部１ａを覆うようにして蓋体を取着することによって製品としての半導体装置となる。   Thus, according to the wiring board of the present invention, after the exposed portion of the thick film resistor 3 is coated with the plated metal film 7b, the thick film resistor is applied from above the insulating film 4 using the exposed portion of the thick film resistor 3 as a guide. The body 3 is laser trimmed to adjust the resistance value, and then the semiconductor integrated circuit element 5 is attached and fixed to the bottom surface of the recess 1a, and each electrode of the semiconductor integrated circuit element 5 is associated via the bonding wire 6. A semiconductor device as a product is obtained by electrically connecting to the metallized wiring conductor 2 and finally attaching a lid to the upper surface of the insulating base 1 so as to cover the recess 1a.

なお、本発明はかかる上述の実施の形態例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。例えば、上述の実施の形態の一例では厚膜抵抗体３はその中央部が絶縁膜４から露出していたが、厚膜抵抗体３は、図４に要部拡大上面図で示すように、その端部が絶縁膜４から露出していてもよい。また、上述の実施の形態例では、厚膜抵抗体３は信号用メタライズ配線導体２ａと接地用メタライズ配線導体２ｂとの間に接続される終端抵抗であったが、厚膜抵抗体３は信号用メタライズ配線導体２ａの途中に直列に接続されるダンピング抵抗等の他の用途の抵抗体であってもよい。さらに、上述の実施の形態の一例では、本発明の配線基板を半導体集積回路素子搭載用の配線基板に適用したが、本発明の配線基板は他の用途の配線基板に適用されても構わない。   Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, in the example of the embodiment described above, the thick film resistor 3 has its central portion exposed from the insulating film 4, but the thick film resistor 3 is shown in FIG. The end portion may be exposed from the insulating film 4. In the above-described embodiment, the thick film resistor 3 is a terminal resistor connected between the signal metallized wiring conductor 2a and the ground metallized wiring conductor 2b. It may be a resistor for other uses such as a damping resistor connected in series in the middle of the metallized wiring conductor 2a. Furthermore, in the above-described embodiment, the wiring board of the present invention is applied to a wiring board for mounting a semiconductor integrated circuit element. However, the wiring board of the present invention may be applied to wiring boards for other uses. .

本発明の配線基板を半導体集積回路素子搭載用の配線基板に適用した場合の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment at the time of applying the wiring board of this invention to the wiring board for semiconductor integrated circuit element mounting. 図１に示す配線基板の上面図である。It is a top view of the wiring board shown in FIG. 図１に示す配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the wiring board shown in FIG. 本発明の配線基板の実施形態の他の例を示す要部拡大上面図である。It is a principal part enlarged top view which shows the other example of embodiment of the wiring board of this invention.

符号の説明Explanation of symbols

１・・・・・・絶縁基体
２・・・・・・配線導体
３・・・・・・厚膜抵抗体
４・・・・・・絶縁膜
７ｂ・・・・・めっき金属膜 DESCRIPTION OF SYMBOLS 1 .... Insulation base | substrate 2 ... Wiring conductor 3 ... Thick film resistor 4 ... Insulation film 7b ... Metal plating film

Claims (2)

絶縁基体と、
前記絶縁基体に設けられた配線導体と、
前記配線導体に電気的に接続されており、前記絶縁基体に設けられた厚膜抵抗体と、
前記厚膜抵抗体を部分的に被覆している絶縁膜と、
前記厚膜抵抗体の前記絶縁膜によって被覆されていない部分を覆っているめっき金属膜と、
前記厚膜抵抗体とは電気的に独立しており、前記厚膜抵抗体に近接して配置されており、前記絶縁基体に設けられたダミー抵抗体と、
を備えた配線基板。 An insulating substrate;
A wiring conductor provided on the insulating substrate;
A thick film resistor electrically connected to the wiring conductor and provided on the insulating substrate;
An insulating film partially covering the thick film resistor;
A plated metal film covering a portion of the thick film resistor that is not covered by the insulating film;
The thick film resistor is electrically independent, and is disposed in proximity to the thick film resistor, a dummy resistor provided on the insulating base,
Wiring board equipped with. 前記配線導体が、信号用配線導体および接地用配線導体を含んでおり、
前記厚膜抵抗体が、前記信号用配線導体および前記接地用配線導体の間に電気的に接続されていることを特徴とする請求項１記載の配線基板。 The wiring conductor includes a signal wiring conductor and a ground wiring conductor;
The wiring board according to claim 1, wherein the thick film resistor is electrically connected between the signal wiring conductor and the ground wiring conductor.
JP2008073872A 2008-03-21 2008-03-21 Wiring board Expired - Fee Related JP4741624B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008073872A JP4741624B2 (en) 2008-03-21 2008-03-21 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008073872A JP4741624B2 (en) 2008-03-21 2008-03-21 Wiring board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP33176699A Division JP4395227B2 (en) 1999-11-22 1999-11-22 Wiring board

Publications (2)

Publication Number Publication Date
JP2008187193A true JP2008187193A (en) 2008-08-14
JP4741624B2 JP4741624B2 (en) 2011-08-03

Family

ID=39729978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008073872A Expired - Fee Related JP4741624B2 (en) 2008-03-21 2008-03-21 Wiring board

Country Status (1)

Country Link
JP (1) JP4741624B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013041844A (en) * 2012-10-18 2013-02-28 Toshiba Corp Active material for battery, nonaqueous electrolyte battery and battery pack
CN109872853A (en) * 2019-02-22 2019-06-11 西安微电子技术研究所 A kind of CrSi2Film resistor and its laser trimming method

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6041073Y2 (en) * 1981-04-01 1985-12-12 山田機械工業株式会社 backpack for work
JPS61229302A (en) * 1985-04-03 1986-10-13 日本電気株式会社 Parallel type resistor unit
JPH0231493A (en) * 1988-07-21 1990-02-01 Alps Electric Co Ltd Circuit board
JPH0319302A (en) * 1989-06-16 1991-01-28 Hitachi Ltd Thin film resistor and manufacture thereof
JPH03124684A (en) * 1989-10-05 1991-05-28 Mitsubishi Electric Corp Jack mounting method of hydraulic elevator
JPH06244363A (en) * 1992-12-22 1994-09-02 Nippondenso Co Ltd Manufacture of thick film multilayer substrate
JPH06326246A (en) * 1993-05-13 1994-11-25 Mitsubishi Electric Corp Thick film circuit board and production thereof
JPH0722221A (en) * 1993-06-29 1995-01-24 Kyocera Corp Production of fixed resistor
JPH07202375A (en) * 1993-12-28 1995-08-04 Kyocera Corp Manufacture of thick-film circuit board
JPH07297515A (en) * 1994-04-27 1995-11-10 Kyocera Corp Wiring board
JPH0888449A (en) * 1994-09-19 1996-04-02 Kyocera Corp Ceramic interconnection board
JPH09223755A (en) * 1996-02-14 1997-08-26 Kyocera Corp Package for storing semiconductor element

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03124684U (en) * 1990-03-28 1991-12-17

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6041073Y2 (en) * 1981-04-01 1985-12-12 山田機械工業株式会社 backpack for work
JPS61229302A (en) * 1985-04-03 1986-10-13 日本電気株式会社 Parallel type resistor unit
JPH0231493A (en) * 1988-07-21 1990-02-01 Alps Electric Co Ltd Circuit board
JPH0319302A (en) * 1989-06-16 1991-01-28 Hitachi Ltd Thin film resistor and manufacture thereof
JPH03124684A (en) * 1989-10-05 1991-05-28 Mitsubishi Electric Corp Jack mounting method of hydraulic elevator
JPH06244363A (en) * 1992-12-22 1994-09-02 Nippondenso Co Ltd Manufacture of thick film multilayer substrate
JPH06326246A (en) * 1993-05-13 1994-11-25 Mitsubishi Electric Corp Thick film circuit board and production thereof
JPH0722221A (en) * 1993-06-29 1995-01-24 Kyocera Corp Production of fixed resistor
JPH07202375A (en) * 1993-12-28 1995-08-04 Kyocera Corp Manufacture of thick-film circuit board
JPH07297515A (en) * 1994-04-27 1995-11-10 Kyocera Corp Wiring board
JPH0888449A (en) * 1994-09-19 1996-04-02 Kyocera Corp Ceramic interconnection board
JPH09223755A (en) * 1996-02-14 1997-08-26 Kyocera Corp Package for storing semiconductor element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013041844A (en) * 2012-10-18 2013-02-28 Toshiba Corp Active material for battery, nonaqueous electrolyte battery and battery pack
CN109872853A (en) * 2019-02-22 2019-06-11 西安微电子技术研究所 A kind of CrSi2Film resistor and its laser trimming method
CN109872853B (en) * 2019-02-22 2020-10-02 西安微电子技术研究所 CrSi2Thin film resistor and laser trimming method thereof

Also Published As

Publication number Publication date
JP4741624B2 (en) 2011-08-03

Similar Documents

Publication Publication Date Title
JP4741624B2 (en) Wiring board
JP4395227B2 (en) Wiring board
JP6525563B2 (en) Wiring board
JP2005136232A (en) Wiring board
JP4535893B2 (en) Multiple wiring board
JP5334815B2 (en) Wiring board
JP4540223B2 (en) Electronic component mounting board
JP3716124B2 (en) Package for storing semiconductor elements
JP4593704B2 (en) Manufacturing method of ceramic substrate
JP4814750B2 (en) Multilayer wiring board, electronic device, and manufacturing method thereof
JP4570190B2 (en) Wiring board
JP2005072508A (en) Circuit board
JP4423181B2 (en) Multiple wiring board
JP3801935B2 (en) Electronic component mounting board
JP3080491B2 (en) Wiring pattern
JP3340610B2 (en) Electronic component package body and method of manufacturing the same
JPH09266124A (en) Mounting structure for capacitor elements
JP2008209237A (en) Probe card assembly substrate and probe card assembly
JP3981316B2 (en) Package for storing semiconductor elements
JP6042773B2 (en) INPUT / OUTPUT TERMINAL, INPUT / OUTPUT TERMINAL MANUFACTURING METHOD, SEMICONDUCTOR ELEMENT PACKAGE AND SEMICONDUCTOR DEVICE USING THE SAME
JP3631664B2 (en) Semiconductor element storage package and semiconductor device
JP2005019749A (en) Wiring board and multiple wiring board
JP2000286522A (en) Ceramic wiring board and its manufacture
JPH0888449A (en) Ceramic interconnection board
JP2003068932A (en) Wiring board

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110111

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110314

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110405

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110506

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140513

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees