JP2008186919A - Laminated ceramic wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated ceramic wiring board of which warpages are prevented, when baking. <P>SOLUTION: The laminated ceramic wiring board 1A comprises a multilayer ceramic board 2 in which a plurality of ceramic boards are stacked; one or more vias 5A formed in one layer or more layers of the ceramic board 2, in the multilayer ceramic board 2; and one or more deflection preventing vias 6A that have a volume similar to the via 5A and formed at the position symmetrically to the via 5A about the central surface in the thickness direction of the multilayer ceramic board 2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multilayer ceramic wiring board, and more particularly to a multilayer ceramic wiring board that can be suitably used for a multilayer LTCC (low temperature fired ceramic) wiring board having a plurality of vias.

  In general, a multilayer ceramic wiring board is formed by laminating and firing ceramic wiring boards before firing having electrodes and vias. The ceramic substrate of the ceramic wiring board shrinks when fired, but since the metal electrodes and vias show almost no shrinkage change compared to the ceramic substrate, the ceramic wiring board of each layer depends on the formation density of the electrodes and vias. The shrinkage rate is different and the laminated ceramic wiring board is warped. Therefore, in the conventional multilayer ceramic wiring board, in order to make the shrinkage rate of the ceramic wiring board of each layer uniform, the electrode for warpage prevention is formed in a flat plate shape at the symmetrical position of the electrode formed on the ceramic wiring board. (See Patent Document 1).

JP 2006-229093 A

  However, in the conventional multilayer ceramic wiring board 101, as shown in FIG. 5, the via 105 has a locally large volume as compared with the electrode 104 for preventing warpage at the symmetrical position of the electrode 103. Even if the electrode 104 for warpage prevention is provided at the symmetrical position, the warpage of the multilayer ceramic substrate 102 cannot be effectively prevented.

  Therefore, the present invention has been made in view of these points, and an object of the present invention is to provide a multilayer ceramic wiring board capable of preventing warpage during firing.

  In order to achieve the above-described object, a multilayer ceramic wiring board according to the present invention has, as a first aspect thereof, a multilayer ceramic substrate formed by laminating a plurality of ceramic substrates, and one or two of the multilayer ceramic substrates. Vias formed in the ceramic substrate as described above, and warpage formed with a volume similar to that of the vias in a symmetrical position with respect to the vias, with a center plane in the thickness direction of the multilayer ceramic substrate as a symmetry plane It features a prevention via.

  According to the multilayer ceramic wiring board of the first aspect, since the warpage preventing via having the same volume as the via is arranged at the symmetrical position of the via, the shrinkage rate of the multilayer ceramic substrate is reduced in the thickness direction of the multilayer ceramic substrate. It can be close to be symmetric.

  The multilayer ceramic wiring board according to a second aspect of the present invention is the multilayer ceramic wiring board according to the first aspect, wherein the shape of the warp preventing via is mirror-symmetrical with the shape of the via with the central plane as a symmetry plane. It is characterized by having.

  According to the multilayer ceramic wiring board of the second aspect, the shrinkage rate of the multilayer ceramic substrate can be made completely symmetrical with respect to the thickness direction of the multilayer ceramic substrate.

  The multilayer ceramic wiring board according to a third aspect of the present invention is characterized in that the warpage preventing via is formed lower than the height of the via in the multilayer ceramic wiring board according to the first aspect.

  According to the multilayer ceramic wiring board of the third aspect, the height of the via is normally equal to the thickness of the ceramic wiring board, but the height of the warpage preventing via is made lower than that of the via, so that the via is formed. Even if the formed ceramic substrate and the ceramic substrate on which the warp preventing via is formed are directly laminated, it is possible to prevent the via and the warp preventing via from being electrically connected.

  A multilayer ceramic wiring board according to a fourth aspect of the present invention is the multilayer ceramic wiring board according to the third aspect, wherein the via and the warp preventing via are formed in a truncated cone shape, and the via and the warp preventing via have a large bottom surface. It is characterized by being arranged with each other or small bottoms facing each other.

  According to the multilayer ceramic wiring board of the fourth aspect, the shrinkage rate of the multilayer ceramic substrate can be made closer to the thickness direction of the multilayer ceramic substrate more easily than when the large bottom surface and the small bottom surface are opposed to each other.

  The multilayer ceramic wiring board according to the fifth aspect of the present invention is the same as the multilayer ceramic wiring board according to the fourth aspect, wherein the height of the warp preventing via is about ½ times the height of the via. The large bottom surface and the small bottom surface of the via are characterized by having an area about twice that of the large bottom surface and the small bottom surface of the via.

  According to the multilayer ceramic wiring board of the fifth aspect, since the shape of the warp preventing via can be approximated to the shape of the via while maintaining the volume of the warp preventing via equal to the volume of the via, the height is made different. However, the shrinkage rate of the multilayer ceramic substrate can be made close to symmetry in the thickness direction of the multilayer ceramic substrate.

  A multilayer ceramic wiring board according to a sixth aspect of the present invention is formed on a multilayer ceramic substrate obtained by laminating a plurality of ceramic substrates and one or more ceramic substrates among the multilayer ceramic substrates. One or two or more vias and one or more vias arranged around a position symmetrical to the vias with a central plane in the thickness direction of the multilayer ceramic substrate as a symmetry plane, and a total volume of the vias And a warp prevention via formed so as to have the same volume as the above.

  According to the multilayer ceramic wiring board of the sixth aspect, since the warpage preventing via having a total volume equal to that of the via is arranged around the symmetrical position instead of the symmetrical position of the via, the warped ceramic board on which the via is formed is warped. Even if the ceramic substrate on which the prevention via is formed is directly laminated, the shrinkage rate of the multilayer ceramic substrate is made closer to the symmetry with respect to the thickness direction of the multilayer ceramic substrate without electrically connecting the via and the warp prevention via. be able to.

  A multilayer ceramic wiring board according to a seventh aspect of the present invention is the multilayer ceramic wiring board according to the sixth aspect, wherein the via and the warp preventing via are formed in a truncated cone shape and the large bottom surface of the via and the warp preventing via. It is characterized by being arranged with each other or small bottoms facing each other.

  According to the multilayer ceramic wiring board of the seventh aspect, the shrinkage rate of the multilayer ceramic substrate can be made closer to the thickness direction of the multilayer ceramic substrate more easily than when the large bottom surface and the small bottom surface are opposed to each other.

  The multilayer ceramic wiring board according to an eighth aspect of the present invention is the multilayer ceramic wiring board according to the seventh aspect, wherein the via and the warp preventing via are formed in the same shape or similar shapes.

  According to the multilayer ceramic wiring board of the eighth aspect, the shrinkage rate of the multilayer ceramic substrate can be made closer to the symmetry with respect to the thickness direction of the multilayer ceramic substrate without electrically connecting the via and the warp preventing via. it can.

  According to the multilayer ceramic wiring board of the present invention, since the shrinkage rate of the multilayer ceramic substrate is approximated or equivalent to the thickness direction of the multilayer ceramic substrate, warpage of the multilayer ceramic wiring board is prevented during sintering. There is an effect that can be.

  Hereinafter, the multilayer ceramic wiring board according to the present invention will be described with reference to the three embodiments with reference to the drawings.

  First, the multilayer ceramic wiring board 1A of the first embodiment will be described with reference to FIG.

  FIG. 1 shows a multilayer ceramic wiring board 1A according to the first embodiment. As shown in FIG. 1, the multilayer ceramic wiring board 1 </ b> A of the first embodiment includes a multilayer ceramic substrate 2, an electrode 3, a warp prevention electrode 4, a via 5 </ b> A and a warp prevention via 6 </ b> A, and is formed on the surface. A semiconductor chip 7 is mounted on the electrode 3.

  The multilayer ceramic substrate 2 is formed by laminating a plurality of ceramic substrates 2A to 2D. These ceramic substrates 2A to 2D are so-called LTCC substrates, and an organic binder and a solvent are added to a powder obtained by mixing glass powder with ceramic powder to form a slurry, and the slurry is formed into a plate shape. It is formed by sintering the obtained green sheet. The green sheet sintering step is performed after forming the electrode 3, the warp preventing electrode 4, the via 5A and the warp preventing via 6A on the green sheet and laminating the green sheets of the respective layers. The number of laminated layers varies depending on the specifications of the laminated ceramic wiring board 1A, but in the laminated ceramic wiring board 1A of the first embodiment, four ceramic substrates 2A to 2D are laminated.

  The electrode 3 and the warpage preventing electrode 4 are formed on the semiconductor chip 7 and the multilayer ceramic wiring board 1A using a metal having excellent conductivity such as Cu, Al, Ag, Au on the surface of the ceramic substrate 2A to 2D of each layer. The wiring pattern is adapted to the connection status of the external circuit (not shown) to be connected. In the multilayer ceramic wiring board 1A of the first embodiment, since four ceramic substrates 2A to 2D are laminated, the boundary surface between the second ceramic substrate 2B and the third ceramic substrate 2C ( That is, the electrode 3 and the warp prevention electrode 4 are arranged at symmetrical positions with the center plane) as the symmetry plane.

  The warpage preventing electrode 4 may be used in conduction with another electrode 3 or may be used as a dummy electrode. Therefore, as long as the warpage prevention electrode 4 is electrically connected to the other electrode 3, there is no distinction between the electrode 3 and the warpage prevention electrode 4 in a symmetrical position. In order to effectively prevent the warpage of the multilayer ceramic wiring board 1A, it is preferable that the electrode 3 and the warp prevention electrode 4 at the symmetrical positions are formed in a mirror symmetrical shape.

  The via 5A and the warp preventing via 6A are formed between the electrodes 3 or between the electrodes 3 and the warp preventing electrode 4 by using the same metal as the electrode 3 and the warp preventing electrode 4 inside the ceramic substrates 2A to 2D of the respective layers. A plurality are formed so as to connect each other. The vias 5A and the warp preventing vias 6A are symmetrically located (on the same axis) with the boundary surface (that is, the central surface) between the second-layer ceramic substrate 2B and the third-layer ceramic substrate 2C as the symmetry plane. Has been placed.

  The warp preventing via 5A may be used in conduction with the electrode 3 or the warp preventing electrode 4, or may be used as a dummy via 5A. Therefore, as long as the warpage prevention via 5A is electrically connected to the electrode 3 or the warpage prevention electrode 4 that is electrically connected to the electrode 3, there is no distinction between the via 5A and the warpage prevention via 6A in the symmetrical position.

  Further, in the first embodiment, the via 5A is formed in a truncated cone shape using a punch, and the warpage preventing via 6A is formed to have the same volume as the via 5A. As the shape of the warp preventing via 6A, a solid shape such as a cylindrical shape, a rectangular shape, a cone shape, a pyramid shape, a truncated cone shape, and a truncated pyramid shape can be selected. The shape is preferably a truncated cone. Since the height of the via 5A is equal to the thickness of one layer of the ceramic substrates 2A to 2D, the via 5A and the warp preventing via 6A are not formed on the ceramic substrates 2A to 2D of the same layer.

  Next, the operation of the multilayer ceramic wiring board 1A according to the first embodiment will be described with reference to FIG.

  The multilayer ceramic substrate 2 in the multilayer ceramic wiring board 1A has a different shrinkage rate and shrinkage position depending on the volume and formation position of the electrode 3, the warp prevention electrode 4, the via 5A, and the warp prevention via 6A. In the multilayer ceramic wiring board 1A according to the first embodiment, the via 5A is located at the symmetrical position of the via 5A with the boundary surface (that is, the center plane) between the second-layer ceramic substrate 2B and the third-layer ceramic substrate 2C as a symmetry plane. The warpage prevention via 6A having the same volume as that of the first embodiment is disposed. For this reason, the shrinkage rate of the multilayer ceramic substrate 2 can be made symmetric with respect to the thickness direction of the multilayer ceramic substrate 2, so that the warpage of the multilayer ceramic wiring board 1A can be suppressed during sintering. Further, the action by the arrangement of the warp prevention electrode 4 is the same as the action by the arrangement of the warp prevention via 6A.

  In particular, in the first embodiment, the shape of the warpage preventing via 6A is mirror-symmetric with respect to the via 5A with the boundary surface (that is, the center plane) between the second ceramic substrate 2B and the third ceramic substrate 2C as the symmetry plane. It is formed in a shape (both frustoconical). Therefore, the shrinkage rate of the multilayer ceramic substrate 2 can be made completely symmetrical with respect to the thickness direction of the multilayer ceramic substrate 2, so that the warpage of the multilayer ceramic wiring board 1A can be prevented during sintering.

  Next, the multilayer ceramic wiring board 1B of the second embodiment will be described with reference to FIG.

  FIG. 2 shows a multilayer ceramic wiring board 1B of the second embodiment. As shown in FIG. 2, the multilayer ceramic wiring board 1 </ b> B of the second embodiment includes a multilayer ceramic substrate 2, an electrode 3, a warp prevention electrode 4, a via 5 </ b> B, and a warp prevention via 6 </ b> B, and is formed on the surface. A semiconductor chip 7 is mounted on the electrode 3. Since the difference from the first embodiment is the shape of the warp prevention via 6B, only the warp prevention via 6B will be described.

  The warp preventing via 6B of the second embodiment is the same as the via 5B at the symmetrical position of the via 5B with the boundary surface (ie, the central surface) between the second layer ceramic substrate 2B and the third layer ceramic substrate 2C as a symmetry plane. It is formed with a certain volume. Further, the warpage preventing via 6B is formed in the same truncated cone shape as the via 5B, and is arranged so that the via 5B and the small bottom surfaces 5Ba and 6Ba of the warping preventing via 6B face each other. However, unlike the first embodiment, the height of the warp preventing via 6B is not equal to the height of the via 5B, and is lower than the height.

  The via 5B and the warp preventing via 6B have a truncated cone shape, the radius of the large bottom surfaces 5Bb and 6Bb of the truncated cone in the via 5B and the warp preventing via 6B is a, and the radius of the small bottom surfaces 5Ba and 6Ba is b. When the height is h, when the height of the warp prevention via 6B is different from the height of the via 5B, the volume of the warp prevention via 6B is made equal to the volume of the via 5B using the following formula.

V = (a ₂ + b ₂ + ab) × πh / 3 (Formula 1)
Further, when the area of the large bottom surfaces 5Bb and 6Bb in the truncated cone is S1, the area of the small bottom surfaces 5Ba and 6Ba is S2, and the height thereof is h, the height of the via 5B and the warp preventing via 6B is the same as described above. In this case, the volume of the warp preventing via 6B is made equal to the volume of the via 5B using the following formula.

V = {S1 + S2 + √ (S1 × S2)} × h / 3 (Expression 2)
For example, as shown in FIG. 2, when the height of the warp prevention via 6B is about ½ times the height of the via 5B, the large bottom surface 6Bb of the warp prevention via 6B is twice the large bottom surface 5Bb of the via 5B. The small bottom surface 6Ba of the warp preventing via 6B is about twice as large as the small bottom surface 5Ba of the via 5B. As shown in FIG. 2, the height of the via 5 </ b> B may be formed higher than the thickness of one ceramic substrate 2.

  Next, the operation of the multilayer ceramic wiring board 1B of the second embodiment will be described with reference to FIG.

  In the multilayer ceramic wiring board 1B of the second embodiment, as shown in FIG. 2, warpage prevention vias 6B having the same volume as the vias 5B are arranged at symmetrical positions of the vias 5B. Therefore, the shrinkage rate of the multilayer ceramic substrate 2 can be made closer to symmetry with respect to the thickness direction of the multilayer ceramic substrate 2. In addition, the via 5B and the warp preventing via 6B are formed in a truncated cone shape, and are disposed so that the small bottom surfaces 5Ba and 6Ba of the via 5B and the warp preventing via 6B are opposed to each other. Therefore, the inclination directions of the vias 5B and the warp preventing vias 6B are symmetric in the axial direction, and the shrinkage rate of the multilayer ceramic substrate 2 is made to be larger than that of the large bottom surface 5Bb of the vias 5B and the small bottom surface 6Ba of the warp preventing vias 6B. It is possible to make it easy to approach the symmetry in the thickness direction of the substrate 2.

  In particular, in the multilayer ceramic wiring board 1B of the second embodiment, the warpage preventing via 6B is formed lower than the height of the via 5B. When the height of the warp preventing via 6B is different from the height of the via 5B, the symmetry of the shape is lost. Therefore, compared with the first embodiment in which the height of the warp preventing via 6B is equal to the height of the via 5B, the shrinkage rate of the ceramic substrate (for example, the second layer ceramic substrate 2B) 2 around the via 5B and the via It becomes difficult to make the shrinkage rate of the ceramic substrate (for example, the third-layer ceramic substrate 2C) 2 close to 5B symmetrical.

  However, the height of the via 5B is usually equal to the thickness of the ceramic substrate 2 in many cases. In consideration of this, by making the height of the warp preventing via 6B lower than that of the via 5B, the ceramic substrate (for example, the second layer ceramic substrate 2B) on which the via 5B is formed and the warp preventing via 6B are formed. Even if the ceramic substrate (for example, the third ceramic substrate 2C) is directly laminated, it is possible to prevent the via 5B and the warpage preventing via 6B from being electrically connected. If the electrical connection between the via 5B and the warp preventing via 6B can be prevented, the degree of freedom in arranging the warp preventing via 6B is improved. Therefore, the via 5B, the electrode 3 and the warp preventing electrode 4 can be freely arranged. it can.

  In the second embodiment, the height of the warp preventing via 6B is about ½ times the height of the via 5B. The reason why the height of the warp prevention via 6B is about ½ times the height of the via 5B is that the multilayer ceramic wiring board 1B faces the via 5B and the warp prevention via 6B when the multilayer ceramic wiring board 1B is fired. This is to effectively prevent the via 5B and the warpage preventing via 6B from being electrically connected. Further, if the height of the warp preventing via 6B is set to at least about 1/2 times the height of the via 5B, the shrinkage rate of the ceramic substrate (for example, the second-layer ceramic substrate 2B) 2 around the via 5B can be reduced. This is because it has been experimentally revealed that it is not so difficult to make the shrinkage rate of the ceramic substrate (for example, the third-layer ceramic substrate 2C) 2 close to the via 5B symmetrical.

  When the height of the warp prevention via 6B is set to about ½ times the height of the via 5B, the large bottom surface 6Bb and the small bottom surface 6Ba of the warp prevention via 6B can be replaced with the via 5B by using the above formula 1 or 2. Each of the large bottom surface 5Bb and the small bottom surface 5Ba has an area about twice as large. Thereby, even if the height of the warp prevention via 6B is changed, the volume of the warp prevention via 6B becomes equal to the volume of the via 5B, and the shape of the warp prevention via 6B approaches the similar shape of the via 5B. It becomes easy to make the shrinkage rate of the multilayer ceramic substrate 2 symmetrical with respect to the thickness direction of the multilayer ceramic substrate 2.

  Even when two vias 5D having a height of one layer as shown in FIG. 4 are arranged coaxially instead of vias 5B having a height of two layers as shown in FIG. If the two coaxial vias 5D as shown in FIG. 2 are considered in the same way as the vias 5B having a height of two layers as shown in FIG. 2, the height is about ½. Therefore, the multilayer ceramic wiring shown in FIG. The plate 1D can obtain the same effect as that of the second embodiment. In this case, the radius of the bottom surface of the warp preventing via 6D is set to √2 times the radius of the bottom surface of the via 5D, and the radius of the large bottom surface of the warping preventing via 6D is set to √2 times the radius of the bottom surface of the via 5D. Thus, the volume of the warp preventing via 6D can be made the same as the volume of the via 5D.

  Next, the laminated ceramic wiring board 1C of the third embodiment will be described with reference to FIG.

  FIG. 3 shows a monolithic ceramic wiring board 1C of the third embodiment. As shown in FIG. 3, the multilayer ceramic wiring board 1 </ b> C of the third embodiment includes a multilayer ceramic substrate 2, an electrode 3, a warpage prevention electrode 4, a via 5 </ b> C, and a warpage prevention via 6 </ b> C, and is formed on the surface. A semiconductor chip 7 is mounted on the electrode 3. Since the difference from the first embodiment is the arrangement of the warp prevention via 6C, only the warp prevention via 6C will be described.

  The via 5C and the warp preventing via 6C are formed in a truncated cone shape, and are arranged with the small bottom surfaces 5Ca and 6Ca of the via 5C and the warp preventing via 6C facing each other. Unlike the first embodiment, the warp preventing via 6C of the third embodiment is arranged at a position symmetrical to the via 5C (in other words, on the same axis as the via 5C) in the ceramic substrate 2 where the via 5C is not formed. One or more are arranged around the symmetrical position (on the same axis as the via 5C). Further, the total volume of one or more warp preventing vias 6C is formed to be approximately the same as the volume of the vias 5C.

  The shape of the warp preventing via 6C is formed in the same shape as or similar to the via 5C as shown in FIG. For example, when two warp prevention vias 6C are arranged for two vias 5C arranged on the same axis, the two warp prevention vias 6C are formed in the same shape as the two vias 5C. ing. Although not shown, when the number of warpage prevention vias 6C other than two (one or three or more) is provided for the two vias 5C arranged on the same axis, the warpage prevention vias 6C are arranged. Is formed in a similar shape to the two vias 5C. Similarly, when two or more warp prevention vias 6C are arranged for one via 5C, two or more warp prevention vias 6C are formed in a similar shape to one via 5C.

  Next, the operation of the multilayer ceramic wiring board 1C of the third embodiment will be described with reference to FIG.

  In the multilayer ceramic wiring board 1C of the third embodiment, the warpage preventing via 6C having a total volume equivalent to that of the via 5C is arranged around the symmetrical position instead of the symmetrical position of the via 5C. Therefore, even if the ceramic substrate (2A to 2D) on which the via 5C is formed and the ceramic substrate (2A to 2D) on which the warpage preventing via 6C is directly stacked, the via 5C and the warpage preventing via 6C are electrically connected. There is no connection, and the degree of freedom of arrangement of the warp preventing via 6C is improved. As a result, the shrinkage rate of the multilayer ceramic substrate 2 can be made closer in the thickness direction of the multilayer ceramic substrate 2, and the vias 5C, the electrodes 3 and the warpage preventing electrodes 4 can be freely arranged.

  Further, in the multilayer ceramic wiring board 1C of the third embodiment, the via 5C and the warpage preventing via 6C are formed in a truncated cone shape, and the small bottom surfaces 5Ca and 6Ca of the via 5C and the warpage preventing via 6C are arranged to face each other. ing. Due to the symmetry of the shapes of the vias 5C and the warp prevention vias 6C, the shrinkage rate of the multilayer ceramic substrate 2 can be made closer to symmetry in the opposing direction (that is, the thickness direction) between the vias 5C and the warp prevention vias 6C.

  In order to improve the symmetry of the shapes of the via 5C and the warp preventing via 6C, the via 5C and the warp preventing via 6C are preferably formed in the same shape or similar shapes. Thereby, it becomes easy to equalize the shrinkage rate of the multilayer ceramic substrate 2 in the thickness direction of the multilayer ceramic substrate 2 without electrically connecting the via 5C and the warp preventing via 6C.

  That is, according to the multilayer ceramic wiring boards 1A to 1C of the first to third embodiments, the warpage preventing vias 6A to 6C having the same volume as the vias 5A to 5C are arranged in the symmetrical position with respect to the vias 5A to 5C or in the vicinity thereof. By doing so, the shrinkage rate of the multilayer ceramic wiring boards 1A to 1C can be made symmetric with respect to the thickness direction of the multilayer ceramic wiring boards 1A to 1C. There is an effect that it can be prevented.

  In addition, this invention is not limited to embodiment mentioned above, A various change is possible as needed.

  For example, as shown in FIGS. 1 to 4, in the multilayer ceramic wiring boards 1A to 1C of the first to third embodiments, the small bottom surfaces 5Aa to 5Ca and 6Aa of the vias 5A to 5C and the warp preventing vias 6A to 6C are provided. .About.6Ca are arranged facing each other. However, in other embodiments, the vias 5A to 5C and the large bottom surfaces 5Ab to 5Cb and 6Ab to 6Cb of the warp preventing vias 6A to 6C may be arranged to face each other.

1 is a longitudinal sectional view showing a multilayer ceramic wiring board according to a first embodiment. A longitudinal sectional view showing a multilayer ceramic wiring board according to a second embodiment A longitudinal sectional view showing a multilayer ceramic wiring board according to a third embodiment The longitudinal cross-sectional view which shows the laminated ceramic wiring board of the modification of 2nd Embodiment Longitudinal section showing a conventional multilayer ceramic wiring board

Explanation of symbols

1A to 1C Multilayer Ceramic Wiring Board 2, 2A to 2D Ceramic Substrate 3 Electrode 4 Warpage Prevention Electrode 5A to 5C Via 6A to 6C Warpage Prevention Via 7 Semiconductor Chip

Claims (8)

A multilayer ceramic substrate formed by laminating a plurality of ceramic substrates;
Vias formed in one or more ceramic substrates of the multilayer ceramic substrate;
And a warp preventing via formed at a position symmetrical to the via with a central plane in the thickness direction of the multilayer ceramic substrate having the same volume as the via. Multilayer ceramic wiring board. 2. The multilayer ceramic wiring board according to claim 1, wherein a shape of the warpage preventing via is mirror-symmetrical with the shape of the via with the central plane as a symmetry plane. 3. The multilayer ceramic wiring board according to claim 1, wherein the warpage preventing via is formed lower than a height of the via. 4. The via and the warp preventing via are formed in a truncated cone shape, and the vias and the warp preventing vias are arranged so that large bottom surfaces or small bottom surfaces thereof face each other. A multilayer ceramic wiring board according to 1. The height of the warp prevention via is about ½ times the height of the via,
5. The multilayer ceramic wiring board according to claim 4, wherein a large bottom surface and a small bottom surface of the warpage preventing via have an area approximately twice as large as each of the large bottom surface and the small bottom surface of the via. A multilayer ceramic substrate formed by laminating a plurality of ceramic substrates;
One or more vias formed in one or more ceramic substrates of the multilayer ceramic substrate;
One or more of the multilayer ceramic substrates are arranged around a position symmetrical to the via with a central plane in the thickness direction of the multilayer ceramic substrate as a symmetry plane, and the total volume is the same volume as the via. A multilayer ceramic wiring board comprising a warpage prevention via formed. The vias and the warp preventing vias are formed in a truncated cone shape, and are arranged such that the bottom surfaces of the vias and the warp preventing vias face each other. A multilayer ceramic wiring board according to 1. The multilayer ceramic wiring board according to claim 7, wherein the via and the warpage preventing via are formed in the same shape or a similar shape.

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