JP2008172434A - Solid-state imaging apparatus, driving method thereof, and camera system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus capable of achieving high-speed image outputting by performing collective transfer operation and read-out operation in parallel, and capable of providing a high quality image with reduced noise. <P>SOLUTION: The solid-state imaging apparatus comprises a pixel array region 101 in which a plurality of photoelectric conversion elements that convert light into electric signal are arrayed in two dimension, in row direction and column direction, a first holding part 102 which holds electric signals converted by photoelectric conversion elements in unit of row, a second holding part 202 which is so arranged to face the first holding means 102 as to sandwich the pixel array region 101 and holds electric signals converted by the photoelectric conversion elements in unit of column, an output part for outputting the electric signals held by the first holding part 102 to the outside, and a second output part for outputting the electric signals held by the second holding part 202 to the outside. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a driving method thereof, and more particularly to a solid-state imaging device including a plurality of holding units that hold pixel data in units of rows, a driving method thereof, and a camera system.

  Known solid-state imaging devices include a CCD solid-state imaging device (CCD image sensor) and a MOS solid-state imaging device (MOS image sensor). Since MOS solid-state imaging devices can output images at a higher speed than CCD solid-state imaging devices, MOS solid-state imaging devices have recently attracted attention.

A conventional MOS type solid-state imaging device will be described below.
9 and 10 are diagrams schematically illustrating a data output method of a conventional MOS type solid-state imaging device.

  The MOS type solid-state imaging device is common to the pixel array region 101 including a plurality of pixels arrayed two-dimensionally in the row direction and the column direction, and the pixels in each column, and holds pixel data for one row. A holding unit 102 and a horizontal signal line 311 for outputting data held by the holding unit 102 are provided.

  First, the signals of pixels for one row in the n (an integer greater than or equal to 1) row of the pixel array region 101 are collectively transferred to the holding unit 102 and held in the holding unit 102 (S101). This operation includes a so-called correlated double sampling operation (CDS) that takes a difference between a reset voltage that is an output voltage of a pixel in a reset state and a photoelectric conversion signal that is an electrical signal photoelectrically converted by the pixel. When the transfer of the signal to the holding unit 102 is completed, the data held in the holding unit 102 is read out to the horizontal signal line 311 pixel by pixel (S102). For example, when the time required for reading data of one pixel to the horizontal signal line 311 is T50 and the number of columns included in the pixel array region 101 is P_hori, the time for reading one row of pixels to the horizontal signal line 311 T_read = T50 × P_hori. When all the signals of the pixels of the nth row held in the holding unit 102 have been read, the signals of the pixels in the (n + 1) th row are transferred to the holding unit 102 at a time (S101), and the transferred n + 1 rows The pixel data of the eye is read (S102).

  By repeating the batch transfer operation (S101) and the readout operation (S102) for all the rows, signals of all the pixels are read out.

  Further, the time required to output the image of the pixels for one row is the sum of the time T_trans required for batch transfer (S101) and the time T_read required for reading.

Hereinafter, a conventional MOS solid-state imaging device will be described in detail.
FIG. 11 is a diagram showing a circuit configuration of a conventional MOS type solid-state imaging device.

  11 includes a pixel array region 101, a holding unit 102, a load transistor region 103, a batch transfer pulse generation unit 104, a read pulse generation unit 105, and a horizontal signal line 311. With.

  The pixel array region 101 includes a plurality of pixels 111, 112, 113, 121, 122, 123, 131, 132, and 133, and vertical signal lines 301, 302, and 303. Note that FIG. 11 shows an example in which pixels of 3 rows × 3 columns are arranged for simplification of description.

  The plurality of pixels 111, 112, 113, 121, 122, 123, 131, 132, and 133 are two-dimensionally arranged in the row direction and the column direction. Pixels in each column of the pixel array region 101 are connected to a plurality of vertical signal lines 301, 302, and 303, respectively. The plurality of pixels 111, 112, 113, 121, 122, 123, 131, 132, and 133 convert light into an electrical signal and output the electrical signal to the vertical signal lines 301, 302, and 303 to which the electrical signal is connected.

  The vertical signal lines 301, 302, and 303 respectively transmit electrical signals converted into a plurality of pixels in each column.

  The plurality of pixels 111, 112, 113, 121, 122, 123, 131, 132, and 133 have the same structure. Hereinafter, the structure of the pixel 111 will be described as an example.

  The pixel 111 includes a photodiode pd11, a transfer transistor m111, a reset transistor m112, and an amplification transistor m113.

  The photodiode pd11 converts light into signal charges and accumulates them. The transfer transistor m111 transfers the signal charge accumulated in the photodiode pd11 to a floating diffusion (hereinafter referred to as “FD”) that is the drain of the transfer transistor m111, and accumulates it. The reset transistor m112 resets the signal charge accumulated in the FD. The amplification transistor m113 amplifies the signal charge accumulated in the FD and outputs an electric signal to the vertical signal line 301.

  The holding unit 102 temporarily holds data corresponding to one row of pixels obtained by photoelectric conversion of a plurality of pixels. Specifically, the holding unit 102 holds, as data, the difference between the reset voltage of the pixel in each column and the electrical signal photoelectrically converted by the pixel. The electric signals for one row held by the holding unit 102 are connected to a common horizontal signal line 311.

  The holding unit 102 includes a plurality of holding circuits 114, 124, and 134 corresponding to each column. The holding circuits 114, 124, and 134 have the same configuration, and the holding circuit 114 will be described below.

  The holding circuit 114 includes a sample switch m015, a hold switch m016, a column selection switch m017, a sample capacitor c011, and a hold capacitor c012.

  The gate of the sample switch m015 is connected to the sample pulse line NCSH1, one of the source / drain is connected to the vertical signal line 301, and the other of the source / drain is connected to one end of the sample capacitor c011. The other end of the sample capacitor c011 is connected to the drain of the hold switch m016. The gate of the hold switch m016 is connected to the clamp pulse line NCCL1, and the source is connected to the hold voltage line CLDCNC1. The hold capacitor c012 is connected between the drain of the hold switch m016 and GND. The column selection switch m017 has a gate connected to the column selection line SL01, one source / drain connected to the drain of the sample switch m015, and the other source / drain connected to the horizontal signal line 311.

  The load transistor region 103 includes load transistors m014, m024, and m034 connected to the vertical signal lines 301, 302, and 303, respectively. The load transistors m014, m024, and m034 supply a constant current to the vertical signal lines 301, 302, and 303.

  The collective transfer pulse generator 104 outputs a control signal for driving the pixels in the row unit included in the pixel array region 101 to the vertical signal lines 301, 302, and 303.

  The read pulse generation unit 105 outputs a control signal for sequentially reading the data held by the holding unit 102 to the horizontal signal line 311 for each column.

Next, the operation of the conventional solid-state imaging device 500 will be described.
FIG. 12 is a timing chart of control signals in the conventional solid-state imaging device 500. In FIG. 12, an operation of reading data for one row of the pixels 111, 121, and 131 is shown. The operations of the pixels 111, 121, and 131 are the same, and the operation of the pixel 111 will be described below as an example.

  In the period T <b> 51, pixel data for one row is read and held in the holding unit 102. In the period T52, the data read in the period T51 is sequentially output to the horizontal signal line 311.

  In the period T51, first, the reset line RS1 becomes active, and the reset transistor m112 is turned on. Thereby, the signal charge accumulated in the FD is reset. At this time, the sample pulse line NCSH1 and the clamp pulse line NCCL1 become active, and the hold voltage cldcnc is applied to the hold voltage line CLDCNC1. As a result, the sample switch m015 and the hold switch m016 are turned on, the reset voltage vrst, which is the voltage of the vertical signal line 301 at the time of reset, is applied to the sample capacitor c011, and the hold voltage cldcnc is applied to the hold capacitor c012.

  Next, the reset transistor m112 is turned off and the transfer transistor m111 is turned on. Thereby, the signal charge accumulated in the photodiode pd11 is transferred to the FD. The amplification transistor m113 amplifies the transferred FD signal charge and outputs the photoelectric conversion signal vsig to the vertical signal line 301. At this time, the hold switch m016 is turned off, and a difference signal (cldcnc− (vrst−vsig)) between the reset voltage vrst and the photoelectric conversion signal vsig is held in the hold capacitor c012.

  Next, the sample switch m015 is turned off. Further, the reset transistor m112 is turned on, the FD is set to a low potential, and the amplification transistor m113 in the read row is not selected.

  Further, the same operation as that of the pixel 111 is performed on the pixels 121 and 131. Through the above operation, the data of the pixels 111, 121, and 131 are held in the holding unit 102.

  After the data of the pixels 111, 121, and 131 are held in the holding unit 102, the column selection switches m017, m027, and m037 are sequentially turned on. As a result, data held in the holding circuits 114, 124, and 134 is sequentially read out to the horizontal signal line 311.

  All pixel signals can be read by performing the above operation for all rows. Here, as the number of pixels increases, the time required to read data of all pixels also increases. In addition, since the number of pixels to be driven at the time of batch transfer increases, the resistance and capacitance parasitic on the row selection lines TX1, TX2, TX3 and the reset lines RS1, RS2, and RS3 also increase. As a result, T_trans also increases. Further, if the time T_trans required for batch transfer is forcibly shortened, fixed pattern noise between columns increases, so that the image quality required for the image sensor cannot be satisfied.

  Here, T_trans is a time required to collectively transfer pixel data of one row to the holding unit 102, T_read is a time required to read data from the holding unit 102 to the horizontal signal line 311, and the pixel array region 101 Assuming that the number of rows of pixels included in P_vert is P_vert, the time required to read data of all pixels included in the pixel array region 101 is (T_trans + T_read) × P_vert. That is, as the number of pixels increases, the time for reading data of all pixels also increases.

On the other hand, a solid-state imaging device that performs two batch transfer operations and readout operations in parallel by providing two holding units 102 is known (see, for example, Patent Document 1). The solid-state imaging device described in Patent Document 1 realizes high-speed image output by reading data held by the other holding unit 102 while transferring a pixel signal to one holding unit 102. .
JP 2006-93816 A

  However, in the conventional solid-state imaging device described in Patent Document 1, the batch transfer operation affects the read operation by simultaneously performing the batch transfer operation and the data read operation. In addition, the read operation affects the batch transfer operation. As a result, there is a problem that noise is added to the signal and the image quality is deteriorated.

  In view of the above problems, the present invention provides a solid-state imaging device capable of achieving high-speed image output and obtaining high-quality images with reduced noise by performing batch transfer operations and read operations in parallel. The purpose is to do.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a pixel array region in which a plurality of photoelectric conversion elements that convert light into electric signals are arranged in a two-dimensional manner in a row direction and a column direction, and a row. A first holding unit that holds an electric signal converted by a unit photoelectric conversion element, and the first holding unit so as to sandwich the pixel array region, and is converted by a row unit photoelectric conversion element; A second holding means for holding the electric signal, a first output means for outputting the electric signal held by the first holding means to the outside, and an electric signal held by the second holding means for the outside. Second output means.

  According to this configuration, by providing the first holding means and the second holding means, the operation of batch-transferring the electric signals in units of rows photoelectrically converted by the plurality of photoelectric conversion elements and holding the electric signals in the first holding means; 2 The operation of reading the electrical signal held in the holding means to the outside can be performed in parallel. In addition, the operation of transferring the electric signals in units of rows photoelectrically converted by the plurality of photoelectric conversion elements and holding the electric signals in the second holding unit and the operation of reading the electric signals held in the first holding unit to the outside are performed in parallel. It can be carried out. Therefore, the solid-state imaging device according to the present invention can realize high-speed image output.

  Further, the first holding unit and the second holding unit are arranged so as to sandwich the pixel array region. Thereby, an operation of collectively transferring the electrical signal photoelectrically converted by the photoelectric conversion element to one of the first holding unit and the second holding unit, and an operation of reading the electrical signal held by the other of the first holding unit and the second holding unit When the above and the like are performed in parallel, it is possible to suppress noise generated by affecting each other. Therefore, the solid-state imaging device according to the present invention can capture a high-quality image.

  In parallel with the operation in which the electric signal converted by the photoelectric conversion element in units of rows is transferred to the second holding means, the first output means sends the electric signal held in the first holding means to the outside. In parallel with the operation in which the electric signal output and converted by the photoelectric conversion element in units of rows is transferred to the first holding means, the second output means externally transmits the electric signal held in the second holding means. May be output.

  According to this configuration, the operation of batch-transferring the electric signals in units of rows photoelectrically converted by the plurality of photoelectric conversion elements and holding them in the first holding means, and the operation of reading out the electric signals held in the second holding means to the outside And in parallel. In addition, the operation of transferring the electric signals in units of rows photoelectrically converted by the plurality of photoelectric conversion elements and holding the electric signals in the second holding unit and the operation of reading the electric signals held in the first holding unit to the outside are performed in parallel. Do. Therefore, the solid-state imaging device according to the present invention can realize high-speed image output.

  Further, the solid-state imaging device is further connected to a plurality of vertical signal lines that respectively transmit electrical signals converted into a plurality of photoelectric conversion elements in each column, and one end of the plurality of vertical signal lines, A first switch element for selecting whether or not to hold the electric signal in units of rows transmitted to the vertical signal line in the first holding means, and the other end of the plurality of vertical signal lines connected to the plurality of vertical signal lines. A second switch element that selects whether or not to hold the electric signal in units of rows transmitted to the signal line in the second holding means may be provided.

  According to this configuration, since the first holding unit and the second holding unit are arranged so as to sandwich the pixel array region, for example, due to the high-speed pulse applied to the first output unit and the second output unit during the read operation Thus, the influence on the vertical signal line can be reduced. Thereby, the influence with respect to the electrical signal which a 1st holding means and a 2nd holding means hold | maintain can be reduced.

  The solid-state imaging device may further include a plurality of first horizontal signal lines that transmit the electrical signal output by the first output means and a plurality of first signals that transmit the electrical signal output by the second output means. Two horizontal signal lines may be provided.

  According to this configuration, the first output unit and the second output unit each output an electric signal in parallel to a plurality of horizontal signal lines, so that the data read time can be shortened.

  The first holding unit holds a plurality of row-unit electrical signals converted by the row-unit photoelectric conversion elements, and the second holding unit stores a plurality of rows converted by the row-unit photoelectric conversion elements. An electric signal of a unit is held, the first output unit mixes and outputs an electric signal of a plurality of row units held in the first holding unit, and the second output unit outputs the second holding unit A plurality of row-wise electrical signals held by the means may be mixed and output to the outside.

According to this configuration, a plurality of pixel signals can be mixed and output.
Further, in parallel with the operation of transferring the electrical signals converted by the plurality of row-unit photoelectric conversion elements to the second holding means, the first output means has a plurality of rows held by the first holding means. In parallel with the operation in which the electric signals of the unit are mixed and output to the outside, and the electric signals converted by the plurality of row photoelectric conversion elements are transferred to the first holding means, the second output means 2 A plurality of row-unit electrical signals held by the holding means may be output to the outside.

  According to this configuration, a plurality of row-unit electric signals photoelectrically converted by the plurality of photoelectric conversion elements are collectively transferred and held in the first holding unit, and a plurality of row-unit electric signals held in the second holding unit are stored. The operation of mixing electrical signals and reading them out is performed in parallel. Also, a plurality of row unit electrical signals photoelectrically converted by a plurality of photoelectric conversion elements are transferred together and held in the second holding unit, and a plurality of row unit electrical signals held in the first holding unit are mixed. Then, the reading operation to the outside is performed in parallel. Therefore, the solid-state imaging device according to the present invention can output an image signal subjected to pixel mixing at high speed.

  The first holding unit outputs a difference between a reset voltage, which is a potential corresponding to a reset state of the photoelectric conversion element transmitted through the vertical signal line, and an electric signal converted by the photoelectric conversion element. The first holding means holds a difference output from the first CDS circuit, and the second holding means has a potential corresponding to a reset state of the photoelectric conversion element transmitted through the vertical signal line. A second CDS circuit that outputs a difference between a certain reset voltage and an electric signal converted by the photoelectric conversion element may be provided, and the second holding unit may hold the difference output from the second CDS circuit.

  Further, the pixel array region, the first holding unit, and the second holding unit are formed on a semiconductor substrate, and in the semiconductor substrate, the pixel array region and a region where the first holding unit is formed; The region where the second holding means is formed may be electrically separated from each other.

  According to this configuration, it is possible to suppress the influence of the current flowing through the vertical signal line by the batch transfer operation on the horizontal signal line.

A camera system according to the present invention includes the solid-state imaging device.
According to this configuration, by providing the first holding means and the second holding means, the operation of batch-transferring the electric signals in units of rows photoelectrically converted by the plurality of photoelectric conversion elements and holding the electric signals in the first holding means; 2 The operation of reading the electrical signal held in the holding means to the outside can be performed in parallel. In addition, the operation of transferring the electric signals in units of rows photoelectrically converted by the plurality of photoelectric conversion elements and holding the electric signals in the second holding unit and the operation of reading the electric signals held in the first holding unit to the outside are performed in parallel. It can be carried out. Therefore, the camera system according to the present invention can realize high-speed image output.

  Further, the first holding unit and the second holding unit are arranged so as to sandwich the pixel array region. Thereby, an operation of collectively transferring the electrical signal photoelectrically converted by the photoelectric conversion element to one of the first holding unit and the second holding unit, and an operation of reading the electrical signal held by the other of the first holding unit and the second holding unit When the above and the like are performed in parallel, it is possible to suppress noise generated by affecting each other. Therefore, the camera system according to the present invention can capture a high-quality image.

  The solid-state imaging device driving method according to the present invention includes a pixel array region in which a plurality of photoelectric conversion elements that convert light into an electric signal are arranged two-dimensionally in a row direction and a column direction, and a photoelectric unit in a row unit. A first holding unit that holds an electric signal converted by the conversion element, and an electric signal that is arranged facing the first holding unit so as to sandwich the pixel array region and is converted by a photoelectric conversion element in units of rows. Second holding means for holding the output, first output means for outputting the electric signal held by the first holding means to the outside, and second output for outputting the electric signal held by the second holding means to the outside A solid-state image pickup device driving method comprising: an operation of transferring an electric signal converted by a photoelectric conversion element in a row unit to the second holding unit; and the first output unit serving as the first holding unit. External electrical signal to be retained A first step of performing an output operation in parallel; an operation of transferring an electric signal converted by a photoelectric conversion element in units of rows to the first holding unit; and the second output unit holding the second holding unit in the second holding unit And a second step of performing in parallel the operation of outputting the electrical signal to be output to the outside.

  According to this, the operation of batch-transferring the electric signals in units of rows photoelectrically converted by the plurality of photoelectric conversion elements and holding them in the first holding means, and the operation of reading out the electric signals held in the second holding means to the outside In parallel. In addition, the operation of transferring the electric signals in units of rows photoelectrically converted by the plurality of photoelectric conversion elements and holding the electric signals in the second holding unit and the operation of reading the electric signals held in the first holding unit to the outside are performed in parallel. Do. Therefore, the solid-state imaging device driving method according to the present invention can realize high-speed image output.

  Further, the first holding unit and the second holding unit are arranged so as to sandwich the pixel array region. Thereby, an operation of collectively transferring the electrical signal photoelectrically converted by the photoelectric conversion element to one of the first holding unit and the second holding unit, and an operation of reading the electrical signal held by the other of the first holding unit and the second holding unit When the above and the like are performed in parallel, it is possible to suppress noise generated by affecting each other. Therefore, the driving method of the solid-state imaging device according to the present invention can capture a high-quality image.

  The first holding unit holds a plurality of row-unit electrical signals converted by the row-unit photoelectric conversion elements, and the second holding unit stores a plurality of rows converted by the row-unit photoelectric conversion elements. The first output means mixes and outputs a plurality of row-unit electric signals held in the first holding means, and the second output means outputs the second holding means to the second holding means. A plurality of row-by-row electric signals are mixed and output, and in the first step, the electric signals converted by the plurality of row-unit photoelectric conversion elements are transferred to the second holding means; One output means performs a parallel operation of mixing a plurality of row-unit electric signals held in the first holding means and outputting them to the outside. In the second step, conversion is performed by a plurality of row-unit photoelectric conversion elements. The transferred electrical signal is transferred to the first holding means. An act of the operation and that the second output means for outputting an electric signal of a plurality of row units held by the second holding means to the outside may be performed in parallel.

  According to this, the operation of collectively transferring a plurality of row-unit electric signals photoelectrically converted by the plurality of photoelectric conversion elements and holding them in the first holding means, and the plurality of row-unit electric signals held in the second holding means. The operation of mixing the signals and reading them out is performed in parallel. Also, a plurality of row unit electrical signals photoelectrically converted by a plurality of photoelectric conversion elements are transferred together and held in the second holding unit, and a plurality of row unit electrical signals held in the first holding unit are mixed. Then, the reading operation to the outside is performed in parallel. Therefore, the driving method of the solid-state imaging device according to the present invention can output the image signal subjected to pixel mixing at high speed.

  The present invention realizes high-speed image output by performing a batch transfer operation and a read operation in parallel, and can obtain a high-quality image with reduced noise, a driving method thereof, and a camera system Can be provided.

  Embodiments of a solid-state imaging device according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
In the solid-state imaging device according to Embodiment 1 of the present invention, two holding units are arranged above and below the pixel array region. Thus, by performing the batch transfer operation and the read operation in parallel, high-speed image output can be realized, and a high-quality image with reduced noise can be obtained.

First, the configuration of the solid-state imaging device according to Embodiment 1 of the present invention will be described.
1 is a diagram illustrating a circuit configuration of a solid-state imaging device according to Embodiment 1 of the present invention. In addition, the same code | symbol is attached | subjected to the element similar to FIG.

  A solid-state imaging device 100 illustrated in FIG. 1 includes a pixel array region 101, holding units 102 and 202, load transistor regions 103 and 203, a collective transfer pulse generation unit 104, readout pulse generation units 105 and 205, and a horizontal signal. Lines 311 and 312.

  The pixel array region 101 includes a plurality of pixels 111, 112, 121, 122, 131 and 132 and a plurality of vertical signal lines 301, 302 and 303. Note that FIG. 1 shows an example in which pixels of 2 rows × 3 columns are arranged to simplify the description.

  The plurality of pixels 111, 112, 121, 122, 131, and 132 are two-dimensionally arranged in the row direction and the column direction. Pixels in each column of the pixel array region 101 are connected to a plurality of vertical signal lines 301, 302, and 303, respectively. The plurality of pixels 111, 112, 121, 122, 131, and 132 convert light into an electrical signal and output the electrical signal to the vertical signal lines 301, 302, and 303 connected thereto.

  The vertical signal lines 301, 302, and 303 respectively transmit electrical signals converted into a plurality of pixels in each column.

  The plurality of pixels 111, 112, 121, 122, 131, and 132 have the same structure, and the structure of the pixel 111 will be described below as an example. The pixel 111 includes a photodiode pd11, a transfer transistor m111, a reset transistor m112, and an amplification transistor m113.

  The photodiode pd11 converts light into signal charges and accumulates them. The photodiode pd11 has the anode side grounded and the cathode side connected to the source of the transfer transistor m111.

  The transfer transistor m111 transfers the signal charge accumulated in the photodiode pd11 to the FD (drain of the transfer transistor m111) and accumulates it. The gate of the transfer transistor m111 is connected to the row selection line TX1.

  The reset transistor m112 resets the signal charge accumulated in the FD. The gate of the reset transistor m112 is connected to the reset line RS1, the drain is connected to the drain of the transfer transistor m111, and the source is connected to the power supply.

  The amplification transistor m113 amplifies the signal charge accumulated in the FD and outputs an electric signal to the vertical signal line 301. The gate of the amplification transistor m113 is connected to the drain of the transfer transistor m111, the drain is connected to the vertical signal line 301, and the source is connected to the power supply.

  The transfer transistor m111, the reset transistor m112, and the amplification transistor m113 are, for example, MOS transistors.

  The holding unit 102 is disposed on one side of the pixel array region 101 (downward in FIG. 1). The holding unit 202 is disposed on the other side of the pixel array region 101 (upward in FIG. 1). That is, the holding unit 202 is disposed to face the holding unit 102 so as to sandwich the pixel array region 101.

  The holding units 102 and 202 temporarily hold an electric signal for one row obtained by photoelectric conversion of a plurality of pixels. Specifically, the holding units 102 and 202 correspond to each pixel a difference between a reset voltage that is a voltage output to the reset state of the pixels in each column and a photoelectric conversion signal that is an electrical signal photoelectrically converted by the pixels. Is retained as data to be processed.

  The holding unit 102 sequentially outputs the held data to the common horizontal signal line 311. The holding unit 202 sequentially outputs the held data to the common horizontal signal line 312.

  The holding unit 102 holds an electric signal for one row photoelectrically converted by a plurality of pixels in parallel with an operation in which the holding unit 202 outputs data for one row held in the holding unit 202 to the horizontal signal line 311. To do. The holding unit 202 holds an electric signal for one row photoelectrically converted by a plurality of pixels in parallel with an operation in which the holding unit 102 outputs data for one row held in the holding unit 102 to the outside.

  The holding unit 102 includes a plurality of holding circuits 114, 124, and 134 corresponding to each column. The holding unit 202 includes a plurality of holding circuits 214, 224, and 234 corresponding to each column. Since the holding circuits 114, 124, 134, 214, 224, and 234 have the same configuration, the holding circuit 114 will be described below.

  The holding circuit 114 holds data corresponding to the electrical signal photoelectrically converted by one pixel. The holding circuit 114 performs CDS that outputs a difference between a reset voltage that is a voltage corresponding to a reset state of a pixel transmitted through the vertical signal line 301 and a photoelectric conversion signal that is an electric signal converted by the pixel. Includes a CDS circuit. The holding circuit 114 holds the difference output from the CDS circuit as data corresponding to each pixel.

  The holding circuit 114 includes a sample switch m015, a hold switch m016, a column selection switch m017, a sample capacitor c011, and a hold capacitor c012. The sample switch m015, the hold switch m016, and the column selection switch m017 are, for example, MOS transistors.

  The sample switch m015 selects whether to hold the electric signal transmitted to the vertical signal line 301 in the holding circuit 114. The gate of the sample switch m015 is connected to the sample pulse line NCSH1, one of the source / drain is connected to the vertical signal line 301, and the other of the source / drain is connected to one end of the sample capacitor c011.

  The sample capacitor c011 and the hold switch m016 constitute a CDS circuit. The other end of the sample capacitor c011 is connected to the drain of the hold switch m016. The gate of the hold switch m016 is connected to the clamp pulse line NCCL1, and the source is connected to the hold voltage line CLDCNC1.

  The hold capacitor c012 is a capacitor for holding data corresponding to the electrical signal photoelectrically converted by one pixel. The hold capacitor c012 is connected between the drain of the hold switch m016 and GND.

  The column selection switch m017 is a switch for selecting whether or not the data held in the hold capacitor c012 is output to the horizontal signal line 311. The gate of the column selection switch m017 is connected to the column selection line SL01, one of the source / drain is connected to the drain of the hold switch m016, and the other of the source / drain is connected to the horizontal signal line 311.

  The load transistor region 103 is disposed on one side of the pixel array region 101 (downward in FIG. 1). The load transistor region 103 includes load transistors m014, m024, and m034 connected to one of the vertical signal lines 301, 302, and 303 (downward in FIG. 1), and a constant current transistor m004. The load transistors m014, m024, and m034 supply a constant current to the vertical signal lines 301, 302, and 303. Further, the load transistors m014, m024, and m034 all have a structure serving as a current mirror with the constant current transistor m004, and thus supply the same constant current to the vertical signal lines 301, 302, and 303.

  The load transistor region 203 is disposed on the other side of the pixel array region 101 (upward direction in FIG. 1). That is, the load transistor region 203 is disposed to face the load transistor region 103 so as to sandwich the pixel array region 101. The load transistor region 203 includes load transistors m114, m124, and m134 connected to the other of the vertical signal lines 301, 302, and 303 (upward in FIG. 1), and a constant current transistor m104. The load transistors m114, m124, and m134 supply a constant current to the vertical signal lines 301, 302, and 303. The load transistors m114, m124, and m134 all have a current mirror structure with the constant current transistor m104, so that the same constant current is supplied to the vertical signal lines 301, 302, and 303.

  The collective transfer pulse generator 104 outputs a control signal for driving the pixels in the row unit included in the pixel array region 101 to the vertical signal lines 301, 302, and 303. Specifically, the collective transfer pulse generator 104 outputs a row selection signal for selecting one row of pixels included in the pixel array region 101 to the row selection lines TX1 and TX2. The collective transfer pulse generator 104 outputs a reset signal for resetting pixels in one row included in the pixel array region 101 to the reset lines RS1 and RS2.

  The read pulse generator 105 outputs a control signal for sequentially reading data held by the holding unit 102 to the horizontal signal line 311 for each pixel. Specifically, column selection signals for selecting data to be read out to the horizontal signal line 311 among the data held in the holding unit 102 are output to the column selection lines SL01, SL02, and SL03.

  The read pulse generator 205 outputs a control signal for sequentially reading data held by the holding unit 202 to the horizontal signal line 312 for each pixel. Specifically, a column selection signal for selecting data to be read to the horizontal signal line 312 among the data held in the holding unit 202 is output to the column selection lines SL11, SL12, and SL13.

  The horizontal signal line 311 transmits data output from the holding unit 102. The horizontal signal line 312 transmits data output from the holding unit 202.

  Thus, in the solid-state imaging device 100 according to Embodiment 1 of the present invention, the two holding units 102 and 202 are arranged so as to sandwich the pixel array region 101 (up and down in FIG. 1). As a result, the operation of transferring the pixel signal to one of the holding units 102 and 202 at once and the operation of reading the data held by the other of the holding units 102 and 202 are affected in parallel. Generated noise can be suppressed. Thereby, a high quality image can be taken.

  FIG. 2 is a diagram schematically showing a cross-sectional structure of the solid-state imaging device 100 according to Embodiment 1 of the present invention.

  As shown in FIG. 2, the solid-state imaging device 100 includes a semiconductor substrate 400, a first conductive region 401, a second conductive region 402, and a third conductive region 403. The first conductive region 401, the second conductive region 402, and the third conductive region 403 are formed in the semiconductor substrate 400. In addition, the first conductive region 401, the second conductive region 402, and the third conductive region 403 are electrically separated. The pixel array region 101 and the load transistor regions 103 and 203 are formed in the first conductive region 401. The holding part 102 is formed in the second conductive region 402. The holding part 202 is formed in the third conductive region 403.

  Here, during the batch transfer operation, since the vertical signal lines 301, 302, and 303 are pulled to the output potential in a short time, a large current flows through the vertical signal lines 301, 302, and 303. In the conventional solid-state imaging device described in Patent Document 1, the current flowing through the vertical signal lines 301, 302, and 303 also affects the horizontal signal lines 311 and 312 that run nearby, and is output to the read horizontal signal lines 311 and 312. Noise occurs in recorded data.

  On the other hand, in the solid-state imaging device 100 according to Embodiment 1 of the present invention, the region of the semiconductor substrate in which the pixel array region 101 is formed, the region of the semiconductor substrate in which the holding unit 102 is formed, and the holding unit 202 are formed. The semiconductor substrate region is electrically isolated. As a result, the influence of the current flowing through the vertical signal lines 301, 302, and 303 by the batch transfer operation on the horizontal signal lines 311 and 312 can be suppressed.

Next, the operation of the solid-state imaging device 100 according to Embodiment 1 of the present invention will be described.
FIG. 3 is a timing chart showing the operation of the solid-state imaging device 100 according to Embodiment 1 of the present invention. In FIG. 3, the reset voltage corresponding to the pixel in the n-th row is represented as vrst (n), the photoelectric conversion signal of the pixel in the n-th row is represented as vsig (n), and the batch transfer operation of the pixels in the n-th row The hold voltage at the time is represented as cldcnc (n). Further, the pixel data of the n-th row and the m-th column read out to the horizontal signal lines 311 and 312 is represented as n_m.

  First, in a period T <b> 01, signals of pixels (pixels 111, 121, 131) for one row in the n-th row included in the pixel array region 101 are collectively transferred to the holding unit 102. Further, in the period T01, data held in the holding unit 202 (data corresponding to pixels in one row of the (n-1) th row) is read out to the horizontal signal line 312.

  Hereinafter, an operation of collectively transferring the signals of the pixels 111, 121, and 131 in the n-th row in the period T01 to the holding unit 102 will be described.

  First, the reset line RS1 becomes active, and the reset transistors m112, m212, and m312 are turned on. Thereby, the signal charge accumulated in the FD of the pixels 111, 121, and 131 is reset. At this time, the sample pulse line NCSH1 and the clamp pulse line NCCL1 become active, and the hold voltage cldcnc (n) is applied to the hold voltage line CLDCNC1. As a result, the sample switches m015, m025, m035, the hold switches m016, m026, and m036 are turned on, and the reset voltage vrst (n) that is the voltage of the vertical signal line 301 at the time of reset is applied to the sample capacitors c011, c021, and c031. The hold voltage cldcnc (n) is applied to the hold capacitors c012, c022, and c032.

  Next, the reset line RS1 becomes inactive, and the reset transistors m112, m212, and m312 are turned off. Thereafter, the row selection line TX1 becomes active, and the transfer transistors m111, m211 and m311 are turned on. Thereby, the signal charges accumulated in the photodiodes pd11, pd21, and pd31 are respectively transferred to the FD.

  The amplification transistors m113, m213, and m313 amplify the transferred FD signal charges, respectively, and output the photoelectric conversion signal vsig (n) to the vertical signal lines 301, 302, and 303. At this time, the hold switches m016, m026, and m036 are off, and the difference signal (cldcnc (n) − (vrst (n) −vsig (n)) between the reset voltage vrst (n) and the photoelectric conversion signal vsig (n). )) Is held in the hold capacitors c012, c022, and c032. Next, the sample switches m015, m025, and m035 are turned off. Thus, data corresponding to the signal photoelectrically converted by the pixel 111 is held in the holding circuit 114. Data corresponding to the signal photoelectrically converted by the pixel 121 is held in the holding circuit 124. Data corresponding to the signal photoelectrically converted by the pixel 131 is held in the holding circuit 134.

  Next, the reset transistors m112, m212, and 312 are turned on, the FD becomes a low potential, and the amplification transistors m113, m213, and m313 of the pixels in the row transferred in batch are deselected.

  Through the above operation, the data of the pixels 111, 121, and 131 in the n-th row are collectively transferred and held in the holding unit 102.

  Note that in the period T01, voltage is applied to the gates and drains of the load transistors m014, m024, and m034 in the load transistor region 103 that drives the vertical signal lines 301, 302, and 303. As a result, the load transistors m014, m024, and m034 supply a constant current to the vertical signal lines 301, 302, and 303. Further, no voltage is applied to the gates and drains of the load transistors m114, m124 and m134 in the load transistor region 203.

  Next, an operation of reading data held in the holding unit 202 in the period T01 is described.

  In the period T01, the column selection lines SL11, SL12, and SL13 are sequentially activated, and the column selection switches m117, m127, and m137 are sequentially turned on. As a result, the data n-1_1, n-1_2, and n-1_3 held in the holding circuits 214, 224, and 234 are sequentially read out to the horizontal signal line 312.

  As described above, in the period T <b> 01, batch transfer to the holding unit 102 of signals photoelectrically converted by pixels for one row in the nth row, and one row of n−1 rows held in the holding unit 202 are performed. The pixel data is read out in parallel.

  Next, in a period T <b> 02, data of pixels (pixels 112, 122, and 132) for one row of the (n + 1) th row included in the pixel array region 101 are collectively transferred to the holding unit 202. Further, in the period T02, the data (pixel data for one row in the nth row) that is collectively transferred and held in the holding unit 102 in the period T01 is read out to the horizontal signal line 311.

  Hereinafter, an operation of collectively transferring the signals of the pixels 112, 122, and 132 in the (n + 1) th row in the period T02 to the holding unit 202 will be described.

  First, the reset line RS2 becomes active, and the reset transistors m122, m222, and m322 are turned on. Thereby, the signal charge accumulated in the FD of the pixels 112, 122, and 132 is reset. At this time, the sample pulse line NCSH2 and the clamp pulse line NCCL2 become active, and the hold voltage cldcnc (n + 1) is applied to the hold voltage line CLDCNC2. As a result, the sample switches m115, m125, and m135, the hold switches m116, m126, and m136 are turned on, and the reset voltage vrst (n + 1) that is the voltage of the vertical signal line 301 at the time of reset is applied to the sample capacitors c111, c121, and c131. The hold voltage cldcnc (n + 1) is applied to the hold capacitors c112, c122, and c132.

  Next, the reset line RS2 becomes inactive, and the reset transistors m122, m222, and m322 are turned off. Thereafter, the row selection line TX2 becomes active, and the transfer transistors m121, m221, and m321 are turned on. Thereby, the signal charges accumulated in the photodiodes pd12, pd22, and pd32 are respectively transferred to the FD.

  The amplification transistors m123, m223, and m323 amplify the transferred signal charges of the FD, respectively, and output the photoelectric conversion signal vsig (n + 1) to the vertical signal lines 301, 302, and 303. At this time, the hold switches m116, m126, and m136 are OFF, and the difference signal (cldcnc (n + 1) − (vrst (n + 1) −vsig (n + 1)) between the reset voltage vrst (n + 1) and the photoelectric conversion signal vsig (n + 1). )) Is held in the hold capacitors c112, c122 and c132. Next, the sample switches m115, m125, and m135 are turned off. Accordingly, data corresponding to the signal photoelectrically converted by the pixel 112 is held in the holding circuit 214. Data corresponding to the signal photoelectrically converted by the pixel 122 is held in the holding circuit 224. Data corresponding to the signal photoelectrically converted by the pixel 132 is held in the holding circuit 234.

  Next, the reset transistors m122, m222, and 322 are turned on, the FD becomes a low potential, and the amplification transistors m123, m223, and m323 of the pixels in the row transferred in batch are deselected.

  Through the above operation, the data of the pixels 112, 122, and 132 in the (n + 1) th row are collectively transferred and held in the holding unit 202.

  In the period T02, voltage is applied to the gates and drains of the load transistors m114, m124, and m134 in the load transistor region 203 that drives the vertical signal lines 301, 302, and 303. Accordingly, the load transistors m114, m124, and m134 supply a constant current to the vertical signal lines 301, 302, and 303. Further, no voltage is applied to the gates and drains of the load transistors m014, m024, and m034 in the load transistor region 103.

  Next, an operation of reading data held in the holding unit 102 in the period T02 is described.

  In the period T02, the column selection lines SL01, SL02, and SL03 are sequentially activated, and the column selection switches m017, m027, and m037 are sequentially turned on. As a result, the data n_1, n_2, and n_3 that are collectively transferred in the period T01 and held in the holding circuits 114, 124, and 134 are sequentially read out to the horizontal signal line 311.

  As described above, in the period T <b> 02, batch transfer to the holding unit 202 of signals obtained by photoelectric conversion of pixels in the n + 1th row and pixels in the nth row held in the holding unit 102 are performed. The data reading is performed in parallel.

  Further, by repeating the operations in the period T01 and the period T02, signals of all the pixels included in the pixel array region 101 can be read out to the horizontal signal line 311 or 312.

  As described above, the solid-state imaging device 100 according to Embodiment 1 of the present invention includes the two holding units 102 and 202, the operation of collectively transferring pixel signals to one of the two holding units 102 and 202, and the holding unit. The data reading operation held by the other of 102 and 202 is performed in parallel. Accordingly, the time required for outputting an image for one row (the time required for batch transfer of pixel signals to the holding unit 102 or 202 and the reading of data held by the holding unit 102 or 202) is the time required for batch transfer. This is the longer of T_trans and time T_read required for reading. Normally, when the number of pixels is large, the time T_read required for reading is longer than the time T_trans required for batch transfer, so the length of the above-described period T01 and period T02 is the time T_trans required for batch transfer. That is, the time T_trans required for batch transfer can be made substantially zero. Therefore, the solid-state imaging device 100 according to Embodiment 1 of the present invention can realize high-speed image output.

  Furthermore, in the solid-state imaging device 100 according to Embodiment 1 of the present invention, the two holding units 102 and 202 are arranged so as to sandwich the pixel array region 101 (up and down in FIG. 1). As a result, the operation of transferring the pixel signal to one of the holding units 102 and 202 at once and the operation of reading the data held by the other of the holding units 102 and 202 are affected in parallel. Generated noise can be suppressed. Thereby, a high quality image can be taken.

  Further, in the conventional solid-state imaging device described in Patent Document 1, a high-speed pulse is input to the column selection switches m017, m027, and m037 at the time of data reading, which affects the vertical signal lines 301, 302, and 303 that run nearby. . As a result, there is a problem that noise is generated in the data held in the holding units 102 and 202. On the other hand, in the solid-state imaging device 100 according to Embodiment 1 of the present invention, the two holding units 102 and 202 are arranged above and below the pixel array region 101, so that the holding units 102 and 202 affect the data being held. Can be suppressed.

  In the solid-state imaging device 100 according to the first embodiment of the present invention, the semiconductor substrate region in which the pixel array region 101 is formed, the semiconductor substrate region in which the holding unit 102 is formed, and the holding unit 202 are formed. The semiconductor substrate region is electrically isolated. As a result, the influence of the current flowing through the vertical signal lines 301, 302, and 303 by the batch transfer operation on the horizontal signal lines 311 and 312 can be suppressed.

  In the above description, a pixel configuration of 2 rows × 3 columns is used for simplicity, but this does not limit the number of pixels, and the present invention can be applied to any number of pixels.

  In the above description, the pixel is composed of three transistors without a selection transistor, but may be composed of four transistors including the selection transistor. Furthermore, it may be configured by three transistors that do not include a transfer transistor and can perform nondestructive reading.

(Embodiment 2)
In the solid-state imaging device according to Embodiment 2 of the present invention, the two holding units each output data in parallel to a plurality of horizontal signal lines. Thereby, the read operation can be performed at high speed.

First, the configuration of the solid-state imaging device according to Embodiment 2 of the present invention will be described.
FIG. 4 is a diagram showing a circuit configuration of the solid-state imaging device according to Embodiment 2 of the present invention. Elements similar to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The solid-state imaging device 200 shown in FIG. 4 is shown in FIG. 1 in that the holding unit 102 is connected to the two horizontal signal lines 311 and 313 and the holding unit 202 is connected to the two horizontal signal lines 312 and 314. Different from the solid-state imaging device 100 according to the first embodiment. The remaining structure of the solid-state imaging device 200 is the same as that of the solid-state imaging device 100 shown in FIG.

  The horizontal signal lines 311 and 313 transmit data output from the holding unit 102. The horizontal signal lines 312 and 314 transmit data output from the holding unit 202.

  As shown in FIG. 4, for example, the column selection switches m017 and m037 corresponding to the odd-numbered columns of pixels of the holding unit 102 are connected to the horizontal signal line 311 and the column selection switch m027 corresponding to the even-numbered columns of pixels is connected to the horizontal signal line. 313 is connected. Column selection switches m117 and m137 corresponding to odd-numbered columns of pixels of the holding unit 202 are connected to the horizontal signal line 312, and column selection switches m127 corresponding to even-numbered columns of pixels are connected to the horizontal signal line 314.

  With the above configuration, the solid-state imaging device 200 according to Embodiment 2 of the present invention can simultaneously output two columns of data corresponding to one row of pixels held by the holding units 102 and 202. Therefore, the read operation can be performed at high speed.

  Note that the cross-sectional structure of the solid-state imaging device 200 according to Embodiment 2 of the present invention is the same as that of the solid-state imaging device 100 according to Embodiment 1 shown in FIG.

Next, the operation of the solid-state imaging device 200 according to Embodiment 2 of the present invention will be described.
FIG. 5 is a timing chart showing the operation of the solid-state imaging device 200 according to Embodiment 2 of the present invention. In FIG. 5, the reset voltage corresponding to the pixel in the n-th row is represented by vrst (n), the photoelectric conversion signal of the pixel in the n-th row is represented by vsig (n), and the n-th row pixel is transferred at once. Is represented as cldcnc (n). Further, the pixel data of the n-th row and the m-th column read out to the horizontal signal lines 311 and 312 is represented as n_m.

  First, in a period T <b> 11, data of pixels (pixels 111, 121, 131) for one row in the n-th row included in the pixel array region 101 are collectively transferred to the holding unit 102. In the period T <b> 11, data held in the holding unit 202 (pixel data for one row of the (n−1) th row) is read out to the horizontal signal lines 312 and 314.

  Note that the operation of collectively transferring the signals of the pixels 111, 121, and 131 to the holding unit 102 in the period T11 is the same as the operation in the period T01 illustrated in FIG.

  Hereinafter, a reading operation of data corresponding to the pixel on the (n−1) th row held in the holding unit 202 in the period T11 will be described.

  In the period T11, two column selection lines among the column selection lines SL11, SL12, and SL13 are sequentially activated. Specifically, first, the column selection lines SL11 and SL12 are activated, and then the column selection lines SL13 and SL14 (the column selection line SL14 is not shown) are activated. As a result, the column selection switches m117 and m127 are first turned on, and then the column selection switches m137 and m147 (the column selection switch m147 is not shown) are turned on. Therefore, the data n-1_1 held in the holding circuit 214 and the data n-1_2 held in the holding circuit 224 are read to the horizontal signal lines 312 and 314 in parallel. Thereafter, the data for every two columns are sequentially output to the horizontal signal lines 312 and 314.

  As described above, in the period T <b> 11, batch transfer to the holding unit 102 of the signal photoelectrically converted by the pixels for the first column of the nth column, and one column of the (n−1) th column held in the holding unit 202. The pixel data is read out in parallel.

  Next, in a period T <b> 12, data of pixels (pixels 112, 122, and 132) for one row of the (n + 1) th row included in the pixel array region 101 are collectively transferred to the holding unit 202. Further, in the period T12, the data (pixel data for one row in the n-th row) that are collectively transferred in the period T11 and held in the holding unit 102 are read out to the horizontal signal line 311.

  Note that the operation of collectively transferring the signals of the pixels 112, 122, and 132 to the holding unit 202 in the period T12 is the same as the operation in the period T02 illustrated in FIG.

  Hereinafter, a data read operation corresponding to the pixel in the nth row held in the holding unit 102 in the period T12 will be described.

  In the period T12, two column selection lines among the column selection lines SL01, SL02, and SL03 are sequentially activated. Specifically, first, the column selection lines SL01 and SL02 are activated, and then the column selection lines SL03 and SL04 (the column selection line SL04 is not shown) are activated. As a result, the column selection switches m017 and m027 are first turned on, and then the column selection switches m037 and m047 (the column selection switch m147 is not shown) are turned on. Therefore, the data n_1 held in the holding circuit 114 and the data n_2 held in the holding circuit 124 are read to the horizontal signal lines 311 and 313 in parallel. Thereafter, the data for every two columns are sequentially output to the horizontal signal lines 311 and 313.

  As described above, in the period T <b> 12, batch transfer to the holding unit 202 of signals obtained by photoelectric conversion of the pixels for one column in the (n + 1) th column, and pixels for one column in the nth column held in the holding unit 102 are performed. The data reading is performed in parallel.

  Further, by repeating the operations in the period T11 and the period T12, signals of all pixels included in the pixel array region 101 can be read out to the horizontal signal lines 311, 312, 313 and 314.

  As described above, the solid-state imaging device 200 according to Embodiment 2 of the present invention can achieve the same effects as the solid-state imaging device 100 according to Embodiment 1.

  Furthermore, in the solid-state imaging device 200 according to Embodiment 2 of the present invention, the two holding units 102 and 202 each output data in parallel to two horizontal signal lines, thereby reducing the data read time by half. Can be shortened. Here, normally, the data read time is longer than the batch transfer time. Therefore, the time required for image output of all pixels is shortened by shortening the data read time. That is, the solid-state imaging device 200 according to the embodiment of the present invention can realize higher-speed image output.

  In the above description, two horizontal signal lines are connected to the two holding units 102 and 202, respectively, but any number of lines can be connected as long as the area permits. By increasing the number of horizontal signal lines, the data read time can be further shortened.

(Embodiment 3)
In the solid-state imaging device 300 according to Embodiment 3 of the present invention, two holding units each hold pixel data for two rows. Furthermore, each holding unit mixes and outputs the data to be held.

First, the configuration of the solid-state imaging device according to Embodiment 3 of the present invention will be described.
FIG. 6 is a diagram showing a circuit configuration of the solid-state imaging device according to Embodiment 3 of the present invention. Elements similar to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The solid-state imaging device 300 shown in FIG. 6 is different from the solid-state imaging device 100 according to the first embodiment shown in FIG.

  The holding units 102 and 202 illustrated in FIG. 6 hold data corresponding to pixels for two rows converted by a plurality of pixels. In addition, the holding unit 102 mixes two rows of data held in the holding unit 102 and outputs the mixed data to the horizontal signal line 311. The holding unit 202 mixes two rows of data held in the holding unit 202 and outputs the mixed data to the horizontal signal line 312.

  The holding unit 102 includes a plurality of holding circuits 114, 124, and 134 corresponding to each column. The holding unit 202 includes a plurality of holding circuits 214, 224, and 234 corresponding to each column. Since the holding circuits 114, 124, 134, 214, 224, and 234 have the same configuration, the holding circuit 114 will be described below.

  The holding circuit 114 includes a sample switch m015, a hold switch m016, a column selection switch m017, a sample capacitance c011, hold capacitances c012 and c013, and hold capacitance selection switches m018 and m019. Note that the configurations of the sample switch m015, the hold switch m016, the column selection switch m017, and the sample capacitor c011 are the same as those in the first and second embodiments, and a description thereof will be omitted.

  The hold capacitance selection switches m018 and m019 are, for example, MOS transistors. The gate of the hold capacitance selection switch m018 is connected to the hold capacitance selection line SWA1, one of the source / drain is connected to one end of the hold capacitance c012, and the other of the source / drain is the other end of the sample capacitance c011 (the drain of the hold switch m016) ). The gate of the hold capacitance selection switch m019 is connected to the hold capacitance selection line SWB1, one of the source / drain is connected to one end of the hold capacitance c013, and the other of the source / drain is the other end of the sample capacitance c011 (the drain of the hold switch m016) ).

  The hold capacitor c012 is connected between one of the source / drain of the hold capacitor selection switch m018 and GND. The hold capacitor c013 is connected between one of the source / drain of the hold capacitor selection switch m019 and GND. Each of the hold capacitor c012 and the hold capacitor c013 is a capacitor for holding data corresponding to an electrical signal photoelectrically converted by one pixel.

  With the above configuration, the solid-state imaging device 300 according to the third embodiment of the present invention controls the hold capacitor selection switches m018 and m019, thereby causing the signals of the pixels in two different rows to be supplied to the two hold capacitors c012 and c013. Can be held.

  Furthermore, the output of the two pixels can be mixed by performing readout with both of the hold capacitance selection switches m018 and m019 turned on. Further, by simultaneously turning on the two column selection switches m017 and m037 and the two hold capacitance selection switches m018 and m019, the output of 4 pixels of 2 rows × 2 columns can be mixed.

  Note that the cross-sectional structure of the solid-state imaging device 300 according to Embodiment 3 of the present invention is the same as that of the solid-state imaging device 100 according to Embodiment 1 shown in FIG.

Next, the operation of the solid-state imaging device 300 according to Embodiment 3 of the present invention will be described.
FIG. 7 is a timing chart showing the operation of the solid-state imaging device 300 according to Embodiment 3 of the present invention. In FIG. 7, the reset voltage corresponding to the pixel in the nth row is represented as vrst (n), and the photoelectric conversion signal of the pixel in the nth row is represented as vsig (n). Further, data obtained by mixing four pixels in the first and third columns of the (n−1) th row and the (n−3) th row output to the horizontal signal line 312 is represented by v01, and the second and fourth columns. Data in which four pixels are mixed is represented as v02. The data obtained by mixing the 4th pixel in the 1st and 3rd columns of the nth row and the (n + 2) th row output to the horizontal signal line 311 is represented by v03, and the 4th pixel in the 2nd and 4th columns is mixed. Data is represented as v04.

  First, in a period T21, signals of pixels (111, 121, and 131) for one row in the n-th row included in the pixel array region 101 are collectively transferred to the holding unit 102, and corresponding data is stored in the hold capacitors c012, c022, and held at c032. Further, in the period T21, data held in the hold capacitors c112, c122, and c132 of the holding unit 202 (data corresponding to pixels for one row in the n-3th row) and held in the hold capacitors c113, c123, and c133. Data (data corresponding to an image for one row of the (n-1) th row) is mixed every four pixels, and the mixed data is read out to the horizontal signal line 312.

  Hereinafter, an operation of collectively transferring pixel data in the period T21 to the holding unit 102 will be described.

  Note that the operation until the photoelectric conversion signal vsig (n) is output from the pixels in the pixel array region 101 to the vertical signal lines 301, 302, and 303 is the same as that in Embodiment 1, and the description thereof is omitted.

  When the photoelectric conversion signal vsig (n) is output to the vertical signal lines 301, 302, and 303, the sample pulse line NCSH1 is active, and the sample switches m015, m025, and m035 are turned on. Further, since the hold capacitance selection line SWA1 is active and the hold capacitance selection line SWB1 is inactive, the hold capacitance selection switches m018, m028, and m038 are turned on, and the hold capacitance selection switches m019, m029, and m039 are turned off. . Thereby, the difference signal (cldcnc (n) −vrst (n) −vsig (n)) between the reset voltage vrst (n) and the photoelectric conversion signal vsig (n) is held in the hold capacitors c012, c022, and c032, respectively. . Next, the sample switches m015, m025 and m035 and the hold capacitor selection switches m018, m028 and m038 are turned off. As a result, data corresponding to signals photoelectrically converted by the pixels 111, 121, and 131 are held in the hold capacitor c012 of the holding circuit 114, the hold capacitor c022 of the holding circuit 124, and the hold capacitor c032 of the holding circuit 134.

  Through the above operation, the data of the pixels 111, 121, and 131 are collectively transferred and held in the hold capacitors c012, c022, and c032 of the holding unit 102.

  Next, an operation of reading data held in the holding unit 202 in the period T21 is described.

  In the period T21, the hold capacitance selection lines SWA2 and SWB2 are activated, and the hold capacitance selection switches m118, m119, m128, m129, m138, and m139 of the holding unit 202 are turned on.

  In the period T21, two column selection lines among the column selection lines SL11, SL12, and SL13 are sequentially activated. Specifically, first, the column selection lines SL11 and SL13 are activated, and then the column selection lines SL12 and SL14 (the column selection line SL14 is not shown) are activated. Thereby, first, the column selection switches m117 and m137 are turned on. Therefore, the data of 4 pixels of 2 rows × 2 columns held in the hold capacitors c112 and c113 of the holding circuit 214 and the hold capacitors c132 and c133 of the holding circuit 234 are mixed and output to the horizontal signal line 312. Next, the column selection switches m127 and m147 (the column selection switch m147 is not shown) are turned on. Therefore, 2 rows × 2 columns of 4 held in the holding capacitors c122 and c123 of the holding circuit 224 and the holding capacitors c142 and c143 of the holding circuit 244 (the holding circuit 244 and the holding capacitors c142 and c143 are not shown). Pixel data is mixed and output to the horizontal signal line 312.

  Thereafter, the column selection signals for two columns are sequentially activated, and the mixed 4-pixel data is sequentially output to the horizontal signal line 312.

  As described above, in the period T <b> 21, batch transfer to the holding unit 102 of a signal photoelectrically converted by pixels for one row in the nth row, and the n−1th row and n−3 held in the holding unit 202. Reading of data obtained by mixing pixel data of 2 rows × 2 columns of the row is performed in parallel.

  Next, in a period T22, signals of pixels for one row of the (n + 1) th row included in the pixel array region 101 are collectively transferred to the holding unit 202, and corresponding data is held in the hold capacitors c112, c122, and c132.

  Note that the operation until the photoelectric conversion signal vsig is output from the pixels in the pixel array region 101 to the vertical signal lines 301, 302, and 303 is the same as that in Embodiment 1, and the description thereof is omitted.

  When the photoelectric conversion signal vsig (n + 1) is output to the vertical signal lines 301, 302, and 303, the sample pulse line NCSH2 is active, and the sample switches m115, m125, and m135 are turned on. Further, since the hold capacitance selection line SWA2 is active and the hold capacitance selection line SWB2 is inactive, the hold capacitance selection switches m118, m128, and m138 are turned on, and the hold capacitance selection switches m119, m129, and m139 are turned off. . As a result, the difference signal (cldcnc (n + 1) −vrst (n + 1) −vsig (n + 1)) between the reset voltage vrst (n + 1) and the photoelectric conversion signal vsig (n + 1) is held in the hold capacitors c112, c122, and c132, respectively. . Next, the sample switches m115, m125, and m135 and the hold capacitance selection switches m118, m128, and m138 are turned off. As a result, data corresponding to a signal photoelectrically converted by the pixels for one row of the (n + 1) th row is held in the hold capacitor c112 of the holding circuit 214, the hold capacitor c122 of the holding circuit 224, and the hold capacitor c132 of the holding circuit 234. .

  Through the above operation, the pixel data of the (n + 1) th row is transferred at once and held in the hold capacitors c112, c122 and c132 of the holding unit 202.

  Next, in a period T23, signals of pixels for one row of the (n + 2) th row included in the pixel array region 101 are collectively transferred to the holding unit 102, and corresponding data is held in the hold capacitors c013, c023, and c033.

  Note that the operation until the photoelectric conversion signal vsig is output from the pixels in the pixel array region 101 to the vertical signal lines 301, 302, and 303 is the same as that in Embodiment 1, and the description thereof is omitted.

  When the photoelectric conversion signal vsig (n + 2) is output to the vertical signal lines 301, 302, and 303, the sample pulse line NCSH1 is active, and the sample switches m015, m025, and m035 are turned on. Furthermore, since the hold capacitance selection line SWA1 is inactive and the hold capacitance selection line SWB1 is active, the hold capacitance selection switches m018, m028, and m038 are turned off, and the hold capacitance selection switches m019, m029, and m039 are turned on. . As a result, the difference signal (cldcnc (n + 2) −vrst (n + 2) −vsig (n + 2)) between the reset voltage vrst (n + 2) and the photoelectric conversion signal vsig (n + 2) is held in the hold capacitors c013, c023, and c033, respectively. . Next, the sample switches m015, m025, and m035 and the hold capacitor selection switches m019, m029, and m039 are turned off. As a result, data corresponding to signals photoelectrically converted by the pixels for one row of the (n + 2) th row is held in the hold capacitor c013 of the holding circuit 114, the hold capacitor c023 of the holding circuit 124, and the hold capacitor c033 of the holding circuit 134. .

  Through the above operation, the pixel data of the (n + 2) th row is transferred in a lump and is held in the hold capacitors c013, c023, and c033 of the holding unit 102.

  Next, in a period T24, signals of pixels for one row of the (n + 3) th row included in the pixel array region 101 are collectively transferred to the holding unit 202, and corresponding data is held in the hold capacitors c113, c123, and c133. Further, in the period T24, the data held in the hold capacitors c012, c022, and c032 of the holding unit 102 (data corresponding to pixels for one row of the nth row) and the hold capacitors c013, c023, and c033 are held. Data (data corresponding to the image of one row of the (n + 2) th row) is mixed every four pixels, and the mixed data is read out to the horizontal signal line 311.

  Hereinafter, an operation of collectively transferring pixel data in the period T24 to the holding unit 202 will be described.

  Note that the operation until the photoelectric conversion signal vsig is output from the pixels in the pixel array region 101 to the vertical signal lines 301, 302, and 303 is the same as that in Embodiment 1, and the description thereof is omitted.

  When the photoelectric conversion signal vsig (n + 3) is output to the vertical signal lines 301, 302, and 303, the sample pulse line NCSH2 is active, and the sample switches m115, m125, and m135 are turned on. Further, since the hold capacitance selection line SWA2 is inactive and the hold capacitance selection line SWB2 is active, the hold capacitance selection switches m118, m128, and m138 are turned off, and the hold capacitance selection switches m119, m129, and m139 are turned on. . As a result, the difference signal (cldcnc (n + 3) −vrst (n + 3) −vsig (n + 3)) between the reset voltage vrst (n + 3) and the photoelectric conversion signal vsig (n + 3) is held in the hold capacitors c113, c122, and c032, respectively. . Next, the sample switches m015, m025 and m035 and the hold capacitor selection switches m018, m028 and m038 are turned off. As a result, data corresponding to signals photoelectrically converted by the pixels 111, 121, and 131 are held in the hold capacitor c012 of the holding circuit 114, the hold capacitor c022 of the holding circuit 124, and the hold capacitor c032 of the holding circuit 134.

  Through the above operation, the data of the pixels 111, 121, and 131 are collectively transferred and held in the hold capacitors c012, c022, and c032 of the holding unit 102.

  Next, an operation of reading data held in the holding unit 102 in the period T24 is described.

  In the period T24, the hold capacitance selection lines SWA1 and SWB1 are activated, and the hold capacitance selection switches m018, m019, m028, m029, m038, and m039 of the holding unit 102 are turned on.

  In the period T24, two column selection lines among the column selection lines SL01, SL02, and SL03 are sequentially activated. Specifically, first, the column selection lines SL01 and SL03 are activated, and then the column selection lines SL02 and SL04 (the column selection line SL14 is not shown) are activated. Thereby, first, the column selection switches m017 and m037 are turned on. Therefore, the data of 4 pixels of 2 rows × 2 columns held in the hold capacitors c012 and c013 of the holding circuit 114 and the hold capacitors c032 and c033 of the holding circuit 134 are mixed and output to the horizontal signal line 311. Next, column selection switches m027 and m047 (column selection switch m147 is not shown) are turned on. Therefore, 2 rows × 2 columns of 4 held in the holding capacitors c022 and c023 of the holding circuit 124 and the holding capacitors c042 and c043 of the holding circuit 144 (the holding circuit 144 and the holding capacitors c042 and c043 are not shown). Pixel data is mixed and output to the horizontal signal line 311.

  Thereafter, the column selection signals for two columns are sequentially activated, and the mixed 4-pixel data is sequentially output to the horizontal signal line 311.

  As described above, in the period T <b> 24, the batch transfer of the signals photoelectrically converted by the pixels of the n + 3th row of pixels to the holding unit 202 and the 2nd row of the nth row and the n + 2th row held in the holding unit 102 are performed. Reading of data obtained by mixing pixel data of rows × 2 columns is performed in parallel.

  As described above, in the solid-state imaging device 300 according to Embodiment 3 of the present invention, the signals of pixels for four rows from the n-th row to the (n + 3) -th row are held by the holding units 102 and 202 by the operations in the periods T21 to T24. The holding units 102 and 202 hold corresponding data. Furthermore, the solid-state imaging device 300 according to Embodiment 3 of the present invention obtains 2 rows × 2 columns of data of 4 rows held in the holding units 102 and 202 by the operations in the periods T21 to T24. Mix and output to horizontal signal lines 311 and 312.

  That is, the solid-state imaging device according to Embodiment 3 of the present invention transfers the data for four rows to the holding units 102 and 202 in a batch by the operations in the periods T21 to T24, and transfers the data for the four rows to the horizontal signal line. 311 and 312 can be read out.

  In the period T21 and the period T24, the batch transfer operation and the read operation are performed in parallel. Usually, since the time required for the read operation is longer than the time required for the batch transfer operation, the length of each of the period T21 and the period T24 is the time T_read required for the read operation. In addition, since only the batch transfer operation is performed in the period T22 and the period T23, the length of each of the period T22 and the period T23 becomes the time T_trans required for the batch transfer operation.

  That is, the time required for batch transfer of signals of pixels for four rows and reading of data for four rows (the total time of the periods T21 to T24) is (T_trans + T_read) × 2. Here, assuming that the number of rows of pixels included in the pixel array region 101 is P_vert, the time required for image output of all the pixels included in the pixel array region 101 is (T_trans + T_read) × P_vert / 2. Therefore, the solid-state imaging device 300 according to Embodiment 3 of the present invention can realize high-speed image output.

  In the above description, the holding units 102 and 202 hold data corresponding to two rows of pixels, but the holding units 102 and 202 hold data corresponding to pixels of three rows or more. Good. Further, in the case where the holding units 102 and 202 each hold data of pixels of three rows or more, data of pixels of three rows or more may be mixed with the horizontal signal lines 311 and 312 and output.

  Further, in the above description, data corresponding to two columns of images are mixed by simultaneously turning on two column selection signals. However, by turning on three or more column selection signals simultaneously, three or more columns are mixed. Data corresponding to the pixels may be mixed.

(Embodiment 4)
In the solid-state imaging device according to Embodiment 4 of the present invention, the holding unit 202 mixes two rows of data held in the holding unit 202 and outputs the data to the outside, and the holding unit 102 is converted by a plurality of pixels. The operation for holding the signals for two rows is performed in parallel. The holding unit 102 mixes two rows of data held in the holding unit 102 and outputs the data to the outside, and the holding unit 202 holds two rows of signals converted by a plurality of pixels. Do in parallel.

  The circuit configuration of the solid-state imaging device according to Embodiment 4 of the present invention is the same as that of the solid-state imaging device 300 shown in FIG. The cross-sectional structure of the solid-state imaging device according to Embodiment 4 of the present invention is the same as that of the solid-state imaging device 100 according to Embodiment 1 shown in FIG.

Hereinafter, the operation of the solid-state imaging device according to Embodiment 4 of the present invention will be described.
FIG. 8 is a timing chart showing the operation of the solid-state imaging device according to Embodiment 4 of the present invention. In FIG. 8, the reset voltage corresponding to the pixel in the nth row is represented as vrst (n), and the photoelectric conversion signal of the pixel in the nth row is represented as vsig (n). In addition, the data obtained by mixing the four pixels in the first and third columns of the (n−1) th row and the (n-3) th row output to the horizontal signal line 311 is represented by v11, and the second and fourth columns. Data in which four pixels are mixed is represented as v12. Data obtained by mixing the 4th pixel in the 1st and 3rd columns of the nth row and the (n + 2) th row output to the horizontal signal line 312 is represented by v13, and the 4th pixel in the 2nd and 4th columns is mixed. Data is represented as v14.

  First, in a period T31, signals of pixels for one row in the n-th row included in the pixel array region 101 are collectively transferred to the holding unit 102, and corresponding data is held in the hold capacitors c012, c022, and c032.

  Next, in a period T <b> 32, signals of pixels for one row of the (n + 2) th row included in the pixel array region 101 are collectively transferred to the holding unit 102, and corresponding data is held in the hold capacitors c013, c023, and c033.

  In the period T31 and the period T32, data held in the hold capacitors c112, c122, and c132 of the holding unit 202 (data corresponding to pixels for one row in the n-3th row) and the hold capacitors c113, c123, and The data held in c133 (data corresponding to the image for one row of the (n-1) th row) is read out to the horizontal signal line 312.

  Next, in a period T33, signals of pixels for one row of the (n + 1) th row included in the pixel array region 101 are collectively transferred to the holding unit 202, and corresponding data is held in the hold capacitors c112, c122, and c132.

  Next, in a period T34, signals of pixels for one row of the (n + 3) th row included in the pixel array region 101 are collectively transferred to the holding unit 202, and corresponding data is held in the hold capacitors c113, c123, and c133.

  Further, in the periods T33 and T34, the data held in the hold capacitors c012, c022, and c032 of the holding unit 102 (data corresponding to pixels for one row in the nth row) and the hold capacitors c013, c023, and c033 are stored. The held data (data corresponding to the image for the first row of n + 2) is read out to the horizontal signal line 311.

  Note that details of the batch transfer operation and the read operation in the period T31 to the period T34 are the same as those in Embodiment 3 described above, and a description thereof is omitted.

  As described above, in the solid-state imaging device according to Embodiment 4 of the present invention, the signals of pixels for four rows from the n-th row to the n + 3-th row are stored in the holding units 102 and 202 by the operations in the periods T31 to T34. The batch transfer is performed, and the holding units 102 and 202 hold corresponding data. Furthermore, the solid-state imaging device according to Embodiment 4 of the present invention mixes data of 2 rows × 2 columns of data for 4 rows held in the holding units 102 and 202 by the operations in the periods T31 to T34. And output to the horizontal signal lines 311 and 312.

  That is, the solid-state imaging device according to Embodiment 4 of the present invention transfers the data for four rows to the holding units 102 and 202 in a batch by the operations in the periods T31 to T34, and transfers the data for four rows to the horizontal signal line. 311 and 312 can be read out.

  Further, in the period T31 and the period T32, the batch transfer operation of the pixel data of the n-th row and the (n + 2) -th row to the holding unit 102 and the data reading operation held by the holding unit 202 are performed in parallel.

  Usually, the time required for the read operation is longer than the time required for the batch transfer operation. When the time T_read required for the read operation is longer than the time T_trans × 2 required for the batch transfer of the pixel data for two rows, the total length of the period T31 and the period T32 becomes the time T_read required for the read operation. .

  In the period T33 and the period T34, the batch transfer operation of the data of the pixels in the (n + 1) th row and the (n + 3) th row to the holding unit 102 and the read operation of the data held in the holding unit 102 are performed in parallel.

  When the time T_read required for the read operation is longer than the time T_trans × 2 required for batch transfer of the pixel data for two rows, the total length of the period T33 and the period T34 becomes the time T_read required for the read operation. .

  That is, the time required for the collective transfer of the signals of the pixels for four rows and the reading of the data for four rows (the total time of the periods T31 to T34) is T_read × 2. Here, if the number of rows of pixels included in the pixel array region 101 is P_vert, the time required to read data of all the pixels included in the pixel array region 101 is T_read × P_vert / 2. Therefore, in the solid-state imaging device according to Embodiment 4 of the present invention, when the time T_read required for the read operation is longer than the time T_trans × 2 required for batch transfer of pixel data for two rows, Embodiment 3 Compared with the solid-state imaging device 300 according to the above, image output can be performed at high speed.

  The present invention can be applied to a solid-state imaging device, and in particular to a CMOS image sensor. Furthermore, the present invention can be applied to a digital still camera, a digital video camera, a Web camera, a camera mounted on a mobile phone, and the like using a CMOS image sensor.

It is a figure which shows the circuit structure of the solid-state imaging device which concerns on Embodiment 1 of this invention. It is a figure which shows the cross-section of the solid-state imaging device which concerns on Embodiment 1 of this invention. 3 is a timing chart of control signals in a read operation of the solid-state imaging device according to Embodiment 1 of the present invention. It is a figure which shows the circuit structure of the solid-state imaging device which concerns on Embodiment 2 of this invention. 6 is a timing chart of control signals in a read operation of the solid-state imaging device according to Embodiment 2 of the present invention. It is a figure which shows the circuit structure of the solid-state imaging device which concerns on Embodiment 3 of this invention. 10 is a timing chart of control signals in a read operation of the solid-state imaging device according to Embodiment 3 of the present invention. It is a timing chart of the control signal in the read-out operation | movement of the solid-state imaging device which concerns on Embodiment 4 of this invention. It is a figure which shows the pixel signal output system of the conventional solid-state imaging device. It is a figure which shows the pixel signal output system of the conventional solid-state imaging device. It is a figure which shows the circuit structure of the conventional solid-state imaging device. It is a timing chart of the control signal in the read-out operation of the conventional solid-state imaging device.

Explanation of symbols

100, 200, 300, 500 Solid-state imaging device 101 Pixel array region 102, 202 Holding unit 103, 203 Load transistor region 104 Batch transfer pulse generation unit 105, 205 Read pulse generation unit 111, 112, 113, 121, 122, 123, 131, 132, 133 Pixels 114, 124, 134, 214, 224, 234 Holding circuits 301, 302, 303 Vertical signal lines 311, 312, 313, 314 Horizontal signal lines 400 Semiconductor substrate 401 First conductive region 402 Second conductive region 403 Third conductive region c011, c021, c031, c111, c121, c131 Sample capacity c012, c022, c032, c112, c122, c132, c013, c023, c033, c113, c123, c133 Hold capacity m111, m121, m131, m211, m221, m231, m311, m321, m331 Transfer transistors m112, m122, m132, m212, m222, m232, m312, m322, m332 Reset transistors m113, m123, m133, m213, m223, m233, m313, m323, m333 Amplifying transistors m014, m024, m034, m114, m124, m134 Load transistors m004, m104 Constant current transistors m015, m025, m035, m115, m125, m135 Sample switches m016, m026, m036, m116, m126, m136 Hold switch m017, m027, m037, m117, m127, m137 Column selection switch m01 , M019, m028, m029, m038, m039, m118, m119, m128, m129, m138, m139 Hold capacitance selection switch pd11, pd12, pd13, pd21, pd22, pd23, pd31, pd32, pd33 Photodiode cldcncst reset voltage Voltage vsig Photoelectric conversion signal CLDCNC1, CLDCNC2 Hold voltage line NCCL1, NCCL2 Clamp pulse line NCSH1, NCSH2 Sample pulse line RS1, RS2, RS3 Reset line SL01, SL02, SL03, SL11, SL12, SL13 Column selection line SWA1, SWA2, SWB1, SWB2 Hold capacitance selection line TX1, TX2, TX3 Row selection line

Claims (11)

A pixel array region in which a plurality of photoelectric conversion elements for converting light into electrical signals are arranged in a two-dimensional shape in a row direction and a column direction;
First holding means for holding an electrical signal converted by a photoelectric conversion element in units of rows;
Second holding means that is arranged to face the first holding means so as to sandwich the pixel array region and holds an electric signal converted by a photoelectric conversion element in units of rows;
First output means for outputting an electrical signal held by the first holding means to the outside;
A solid-state imaging device comprising: a second output unit that outputs an electrical signal held by the second holding unit to the outside. In parallel with the operation in which the electric signal converted by the photoelectric conversion element in units of rows is transferred to the second holding unit, the first output unit outputs the electric signal held in the first holding unit to the outside. ,
In parallel with the operation in which the electric signal converted by the photoelectric conversion element in units of rows is transferred to the first holding unit, the second output unit outputs the electric signal held in the second holding unit to the outside. The solid-state imaging device according to claim 1. The solid-state imaging device further includes:
A plurality of vertical signal lines respectively transmitting electrical signals converted to a plurality of photoelectric conversion elements in each column;
A first switch element that is connected to one end of the plurality of vertical signal lines and selects whether or not to hold the electric signal in units of rows transmitted to the plurality of vertical signal lines in the first holding unit;
A second switch element connected to the other end of the plurality of vertical signal lines and configured to select whether to hold the electric signal in units of rows transmitted to the plurality of vertical signal lines in the second holding unit; The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided. The solid-state imaging device further includes:
A plurality of first horizontal signal lines for transmitting electrical signals output by the first output means;
The solid-state imaging device according to claim 1, further comprising: a plurality of second horizontal signal lines that transmit the electrical signal output by the second output unit. The first holding unit holds a plurality of row-unit electric signals converted by the row-unit photoelectric conversion elements,
The second holding unit holds a plurality of row-unit electric signals converted by the row-unit photoelectric conversion elements,
The first output means mixes a plurality of row-unit electric signals held in the first holding means and outputs them to the outside.
5. The solid-state imaging according to claim 1, wherein the second output unit mixes a plurality of row-unit electrical signals held by the second holding unit and outputs the mixed signals to the outside. apparatus. In parallel with the operation in which the electrical signals converted by the plurality of row-unit photoelectric conversion elements are transferred to the second holding unit, the first output unit has a plurality of row-units held by the first holding unit. Mixing electrical signals and outputting them to the outside
In parallel with the operation in which the electrical signals converted by the plurality of row-unit photoelectric conversion elements are transferred to the first holding unit, the second output unit has a plurality of row-units held by the second holding unit. The solid-state imaging device according to claim 5, wherein an electrical signal is output to the outside. The first holding means is
A first CDS circuit that outputs a difference between a reset voltage that is a potential corresponding to a reset state of the photoelectric conversion element transmitted through the vertical signal line and an electric signal converted by the photoelectric conversion element;
The first holding unit holds a difference output from the first CDS circuit,
The second holding means is
A second CDS circuit that outputs a difference between a reset voltage, which is a potential corresponding to a reset state of the photoelectric conversion element transmitted through the vertical signal line, and an electric signal converted by the photoelectric conversion element;
The solid-state imaging device according to claim 1, wherein the second holding unit holds a difference output from the second CDS circuit. The pixel array region, the first holding unit, and the second holding unit are formed on a semiconductor substrate,
2. The semiconductor substrate according to claim 1, wherein the pixel array region, the region in which the first holding unit is formed, and the region in which the second holding unit are formed are electrically separated from each other. The solid-state imaging device according to any one of 1 to 7. A camera system comprising the solid-state imaging device according to claim 1. A pixel array region in which a plurality of photoelectric conversion elements for converting light into electrical signals are arranged in a two-dimensional shape in a row direction and a column direction;
First holding means for holding an electrical signal converted by a photoelectric conversion element in units of rows;
Second holding means that is arranged to face the first holding means so as to sandwich the pixel array region and holds an electric signal converted by a photoelectric conversion element in units of rows;
First output means for outputting an electrical signal held by the first holding means to the outside;
A solid-state imaging device driving method comprising: a second output unit that outputs an electrical signal held by the second holding unit to the outside,
The operation of transferring the electric signal converted by the photoelectric conversion element in units of rows to the second holding unit and the operation of the first output unit outputting the electric signal held by the first holding unit to the outside are performed in parallel. A first step to
The operation of transferring the electric signal converted by the photoelectric conversion element in units of rows to the first holding unit and the operation of the second output unit outputting the electric signal held by the second holding unit to the outside are performed in parallel. A solid-state imaging device driving method characterized by comprising: The first holding unit holds a plurality of row-unit electric signals converted by the row-unit photoelectric conversion elements,
The second holding unit holds a plurality of row-unit electric signals converted by the row-unit photoelectric conversion elements,
The first output means mixes and outputs a plurality of row-unit electrical signals held by the first holding means,
The second output means mixes and outputs a plurality of row-unit electric signals held by the second holding means,
In the first step, an operation of transferring electric signals converted by a plurality of row-unit photoelectric conversion elements to the second holding unit, and a plurality of rows in which the first output unit is held by the first holding unit. The unit's electrical signal is mixed and output to the outside in parallel.
In the second step, an operation of transferring electric signals converted by a plurality of row-unit photoelectric conversion elements to the first holding unit, and a plurality of rows in which the second output unit is held by the second holding unit. The method of driving a solid-state imaging device according to claim 10, wherein an operation of outputting an electrical signal of a unit to the outside is performed in parallel.

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