JP6747316B2 - Solid-state imaging device and imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device and an imaging device.

A CCD solid-state image pickup device and a CMOS solid-state image pickup device are known as solid-state image pickup devices having a pixel row in which a plurality of pixels are arranged in one direction, and for example, as solid-state image pickup devices mounted in an image pickup apparatus such as a copying machine. ing.

The CMOS solid-state image sensor is generally manufactured based on the CMOS LSI manufacturing process. Therefore, it has excellent features compared to CCD solid-state image pickup devices such as the ability to form a chip integrated with an image processing circuit (system-on-chip) and easy high-speed processing. ing.

Along with the demand for higher resolution, smaller size, and lower cost of solid-state imaging devices, reduction in pixel size has been required in recent years. When the pixel size is simply reduced, the photoelectric conversion element portion is reduced and the amount of incident light is reduced, so the sensitivity is lowered and the S/N characteristic is deteriorated.

On the other hand, a TDI (Time Delay Integration) type solid-state imaging device has been proposed as a technique for compensating for a decrease in sensitivity due to a reduction in pixel size.

Patent Document 1 discloses a CMOS solid-state imaging device (solid-state imaging device) that operates in the TDI system. According to the solid-state imaging device of Patent Document 1, the pixel signal of each frame is sequentially added to make the final pixel signal size N times the pixel signal size of one frame.

When imaging with the TDI method, a plurality of pixels aligned in the sub-scanning direction (vertical direction) need to be exposed when light from the same target position of the subject is incident. Since pixel signals of a plurality of pixels arranged in the sub-scanning direction and connected to a common signal line cannot be transferred at the same time, wait until the signal line and the memory in the subsequent stage are released before reading the pixel signal of a certain pixel. There is a need to. Due to this standby time, when exposing each pixel aligned in the sub-scanning direction, the relative position between the target position of the subject and the pixel (relative position when starting exposure and relative position when ending exposure) (Position) may shift.

According to Patent Document 1, in order to make the relative position between the target position of the subject and the pixel coincide with each other between the pixels, the arrangement interval of the pixel column group and the arrangement interval of the pixel column of each pixel column group are It is determined based on the number M of column groups, the number N of pixel columns of each pixel column group, and the waiting time described above. Therefore, the size and spacing of each pixel are strongly constrained.

Further, in order to reduce the deviation of the relative position between the target position of the subject and the pixel, it is conceivable to reduce the pixel interval. However, if the pixel interval is reduced, the pixel size is also reduced, and there is a problem that the sensitivity is reduced accordingly.

An object of the present invention is to make the relative position between the target position of the object and the pixel coincident with each other when exposing each pixel aligned in the sub-scanning direction without impairing the degree of freedom of the size and spacing of each pixel. Another object of the present invention is to provide a solid-state image sensor capable of performing the above.

According to the solid-state image sensor according to one aspect of the present invention,
A solid-state imaging device comprising a pixel array in which a plurality of pixels that respectively generate pixel signals according to incident light are two-dimensionally arranged in a main scanning direction and a sub scanning direction,
The pixel array includes a plurality of pixel sub-arrays arranged at predetermined intervals in the sub-scanning direction, and each one pixel sub-array among the plurality of pixel sub-arrays is a plurality of pixels in the main-scanning direction. And a plurality of pixels arranged two-dimensionally so as to form a plurality of rows and a plurality of columns along the sub-scanning direction,
The solid-state image sensor,
For each one pixel sub-array of the plurality of pixel sub-arrays, a plurality of signal lines individually connected to the plurality of pixels of each column in the pixel sub-array,
A memory for temporarily storing pixel signals read from the plurality of pixels via the plurality of signal lines;
An adder circuit that adds pixel signals read from a plurality of pixels in the same column to each other for each one pixel sub-array of the plurality of pixel sub-arrays,
The plurality of pixels in each column in one pixel sub-array of the plurality of pixel sub-arrays are arranged on a column-by-column basis in the sub-scanning direction along the sub-scanning direction. Aligned with multiple pixels in a row,
In the plurality of pixels aligned along the sub-scanning direction, at least one pixel in one pixel sub-array of the plurality of pixel sub-arrays is at least in another pixel sub-array of at least one of the plurality of pixel sub-arrays. It is connected to a signal line to which one pixel is connected.

According to the solid-state image sensor according to one aspect of the present invention, when the pixels aligned in the sub-scanning direction are exposed, the relative position between the target position of the subject and the pixels is exposed without impairing the degree of freedom of the size and the interval of each pixel. The positions can be matched to each other among the pixels.

1 is a block diagram showing an overall configuration of a solid-state image sensor according to Embodiment 1 of the present invention. 2 is a circuit diagram showing a detailed configuration of pixels B1, B2, G1, G2, R1, R2 in FIG. 1. FIG. 3 is a timing chart showing the operation of pixels B1, B2, G1, G2, R1, R2 in FIG. 1. 3 is a timing chart showing positions and exposure periods of pixels B1, B2, G1, G2, R1, R2 of FIG. FIG. 6 is a diagram showing a configuration of a pixel array 20A according to a modified example of Embodiment 1 of the present invention. It is a block diagram showing the whole solid-state image sensing device composition concerning Embodiment 2 of the present invention. 7 is a circuit diagram showing a detailed configuration of the pixel array 20B of FIG. It is a circuit diagram which shows the detailed structure of the pixel circuits 23a-23d of FIG. It is a block diagram showing the whole solid-state image sensing device composition concerning a modification of Embodiment 2 of the present invention. FIG. 10 is a circuit diagram showing a detailed configuration of the pixel array 20C of FIG. 9. It is a block diagram which shows the structure of the imaging device which concerns on Embodiment 3 of this invention.

Embodiments of the present invention will be described in detail with reference to the following drawings.

Embodiment 1.
FIG. 1 is a block diagram showing the overall configuration of a solid-state image sensor according to the first embodiment of the present invention. The solid-state image sensor of FIG. 1 includes a pixel control circuit 10, a pixel array 20, an output control circuit 30, and a readout circuit 40. These components of the solid-state image sensor are formed on, for example, a semiconductor substrate.

The pixel array 20 includes a plurality of pixels that respectively generate pixel signals according to incident light, and each pixel operates under the control of the pixel control circuit 10. The readout circuit 40 reads out and outputs a pixel signal from each pixel of the pixel array 20 under the control of the output control circuit 30.

Each pixel of the pixel array 20 is two-dimensionally arranged in the main scanning direction (X direction in FIG. 1) and the sub scanning direction (Y direction in FIG. 1). The pixel array 20 includes a plurality of pixel sub-arrays 21B, 21G, 21R arranged at a predetermined interval in the sub-scanning direction. The pixel sub-array 21B is two-dimensionally arranged so as to form a plurality of rows (two rows in FIG. 1) along the main scanning direction and a plurality of columns (six columns in FIG. 1) along the sub-scanning direction. Of pixels B1 and B2. The pixel sub-array 21G is two-dimensionally arranged so as to form a plurality of rows (two rows in FIG. 1) along the main scanning direction and a plurality of columns (six columns in FIG. 1) along the sub-scanning direction. Pixels G1 and G2 are included. The pixel sub-array 21R is two-dimensionally arranged so as to form a plurality of rows (two rows in FIG. 1) along the main scanning direction and a plurality of columns (six columns in FIG. 1) along the sub-scanning direction. Of pixels R1 and R2.

Each pixel B1, B2, G1, G2, R1, R2 has, for example, a square shape and the same size. In each of the pixel sub-arrays 21B, 21G, and 21R, the plurality of pixels are arranged, for example, at equal intervals in the main scanning direction, and are also arranged, for example, at equal intervals in the sub-scanning direction.

By a filter or the like, for example, the blue component of the light from the subject enters the pixel sub-array 21B, the green component of the light from the subject enters the pixel sub-array 21G, and the red component of the light from the subject enters the pixel sub-array 21R. Is incident.

The plurality of pixels in each column in one pixel sub-array of the pixel sub-arrays 21B, 21G, and 21R are arranged in the remaining pixel sub-arrays of the pixel sub-arrays 21B, 21G, and 21R along the sub-scanning direction for each column. Each of the plurality of pixels in each column is aligned. Therefore, for each column of the pixel array 20, the pixels B1 and B2 of the pixel sub-array 21B, the pixels G1 and G2 of the pixel sub-array 21G, and the pixels R1 and R2 of the pixel sub-array 21R are aligned in the sub-scanning direction.

In each column of the pixel array 20, an invalid area N1 that does not contribute to generation of a pixel signal is provided between two pixels B2 and G1 that face each other between two pixel sub arrays 21B and 21G that are adjacent to each other. In addition, in each column of the pixel array 20, an invalid region N2 that does not contribute to generation of a pixel signal is provided between two pixels G2 and R1 that face each other between two pixel sub arrays 21G and 21R that are adjacent to each other. The invalid areas N1 and N2 have a size of two-thirds of one side of each pixel in the sub-scanning direction.

In each column of the pixel sub-array 21B, the pixels B1 and B2 are connected to different signal lines 22a and 22b, respectively. In each column of the pixel sub-array 21G, the pixels G1 and G2 are connected to different signal lines 22a and 22b, respectively. In each column of the pixel sub-array 21R, the pixels R1 and R2 are connected to different signal lines 22a and 22b, respectively.

In the pixels B1, B2, G1, G2, R1 and R2 aligned along the sub-scanning direction, at least one pixel in one of the pixel sub-arrays 21B, 21G and 21R is the pixel sub-arrays 21B, 21G and 21R. At least one pixel in at least one other pixel sub-array is connected to the connected signal line. In the case of FIG. 1, in the pixels B1, B2, G1, G2, R1, R2 aligned along the sub-scanning direction, one pixel from each pixel sub-array 21B, 21G, 21R is connected to one signal line. .. Therefore, in each column of the pixel array 20, the pixel B1, the pixel G1, and the pixel R1 are connected to the signal line 22a, and the pixel B2, the pixel G2, and the pixel R2 are connected to the signal line 22b.

The read circuit 40 includes a plurality of amplifiers 41, a plurality of memory and adder circuits 42, a plurality of analog/digital converters (ADC) 43, a digital transfer circuit 44, and an amplifier 45. The amplifier 41 is provided for each of the signal lines 22a and 22b in each column of the pixel array 20. The memory and adder circuit 42 and the analog/digital converter 43 are provided for each column of the pixel array 20.

Each amplifier 41 amplifies the pixel signal read from each pixel B1, B2, G1, G2, R1, R2 and sends it to the memory and adder circuit 42 in the subsequent stage.

First, each memory and addition circuit 42 temporarily outputs the pixel signal read from each pixel B1, B2, G1, G2, R1, R2 via each signal line 22a, 22b in each column of the pixel array 20. Store. Each memory and addition circuit 42 further adds pixel signals read from a plurality of pixels in the same column to each other for each one pixel sub-array of the pixel sub-arrays 21B, 21G, and 21R. In other words, each memory and adder circuit 42 adds pixel signals read from a plurality of pixels of the same pixel sub-array in each column of the pixel array 20 to each other. In each column of the pixel array 20, each memory and addition circuit 42 adds the pixel signals read from the pixels B1 and B2 to each other, adds the pixel signals read from the pixels G1 and G2 to each other, and adds the pixel signals to the pixel R1. , R2 are added to each other. Each memory and addition circuit 42 sends the pixel signal of the addition result to the analog/digital converter 43 in the subsequent stage.

Each analog/digital converter 43 performs analog/digital conversion on the signal (analog signal) sent from the memory and adder circuit 42 and sends it to the digital transfer circuit 44 in the subsequent stage.

The digital transfer circuit 44 sends the signals sent from the plurality of analog/digital converters 43 to the amplifier 45 in a predetermined order.

The amplifier 45 amplifies the signal sent from the digital transfer circuit 44 and outputs it as an output signal of the solid-state image sensor.

The pixel control circuit 10 controls generation of pixel signals by the pixels B1, B2, G1, G2, R1 and R2 of the pixel array 20. Since the solid-state image sensor of FIG. 1 operates in the TDI method, it moves relative to the subject in the sub-scanning direction (for example, in the −Y direction of FIG. 1) at a predetermined speed. The moving time for one pixel is equal to the exposure period for one pixel, and this period is called a "frame". The pixel control circuit 10 selects one of the pixel sub-arrays 21B, 21G, and 21R in a predetermined order in synchronization with the relative movement speed of the pixel array 20 with respect to the subject, and further selects one of the selected pixel sub-arrays. Select one of the rows in a predetermined order. That is, the pixel control circuit 10 selects the pixels B1, B2, G1, G2, R1, R2 arranged in the sub-scanning direction in order from top to bottom in FIG. The pixel control circuit 10 exposes the selected pixel to generate a pixel signal, and transfers the generated image signal to the memory and addition circuit 42 via the signal lines 22a and 22b.

The pixel control circuit 10 controls the generation of pixel signals by the pixels B1, B2, G1, G2, R1 and R2 via a plurality of control lines. The control lines include control lines L11, L12, L21, L22, L31, and L32 that are connected to the transfer transistors of each pixel, respectively. Although omitted for simplification of illustration, the control lines include a reset transistor and an output transistor of each pixel. Includes other control lines that are each connected. The transfer transistor, the reset transistor, and the output transistor of each pixel will be described later with reference to FIG.

The output control circuit 30 controls the timing of processing the pixel signals read by the readout circuit 40 from each pixel of the pixel array 20.

FIG. 2 is a circuit diagram showing a detailed configuration of the pixels B1, B2, G1, G2, R1, R2 of FIG. Each pixel includes a photoelectric conversion element PD, a transfer transistor TX, a floating diffusion FD, a reset transistor RT, an amplification transistor SF, and an output transistor SL.

The photoelectric conversion element PD converts the incident light on each pixel into an electric charge. The photoelectric conversion element PD is, for example, a photodiode.

The transfer transistor TX is connected between the photoelectric conversion element PD and the floating diffusion FD. A control signal is applied to the gate terminal of the transfer transistor TX from the pixel control circuit 10 via the control line LTX. The control line LTX of FIG. 2 corresponds to one of the control lines L11, L12, L21, L22, L31, L32 of FIG. The transfer transistor TX transfers charges from the photoelectric conversion element PD to the floating diffusion FD according to the control signal applied via the control line LTX.

The floating diffusion FD is a region on the semiconductor substrate that temporarily stores the charges transferred from the photoelectric conversion element PD.

The reset transistor RT is connected between the reset power supply VDDRT and the floating diffusion FD. A control signal is applied to the gate terminal of the reset transistor RT from the pixel control circuit 10 via the control line LRT. The reset transistor RT resets the potential of the floating diffusion FD to the potential of the reset power supply VDDRT according to the control signal applied via the control line LRT.

The drain of the amplification transistor SF is connected to the power supply VDD, and the source of the amplification transistor SF is connected to the terminal VOUT via the output transistor SL. The terminal VOUT is connected to the signal line 22a or 22b. The gate of the amplification transistor SF is connected to the floating diffusion FD. The amplification transistor SF constitutes a source follower together with the constant current source outside the pixel array 20. The amplification transistor SF amplifies the voltage in the floating diffusion FD and generates a pixel signal having the amplified voltage.

The drain of the output transistor SL is connected to the source of the amplification transistor SF, and the source of the output transistor SL is connected to the terminal VOUT. A control signal is applied to the gate terminal of the output transistor SL from the pixel control circuit 10 via the control line LSL. The output transistor SL selectively outputs the pixel signal to the signal lines 22a and 22b via the terminal VOUT according to the control signal applied via the control line LSL. In the pixels B1, B2, G1, G2, R1 and R2 aligned along the sub-scanning direction, the output transistors SL of only the pixels from which pixel signals should be read are turned on, and the output transistors SL of the other pixels are turned off.

In the plurality of pixels in the same row in the pixel array 20, the transfer transistor is connected to the common control line, the reset transistor is connected to the common control line, and the output transistor is connected to the common control line. Thereby, the plurality of pixels in the same row operate in synchronization with each other.

FIG. 3 is a timing chart showing the operation of the pixels B1, B2, G1, G2, R1 and R2 of FIG.

According to FIG. 3, in the pixels B1 and B2 of the pixel sub-array 21B, the pixel signal generated from the light exposed during the exposure period from time t00 to t10 is read out at time t10. Further, the pixel signal generated from the light exposed during the exposure period from time t10 to t20 is read at time t20. Further, the pixel signal generated from the light exposed during the exposure period from time t20 to t30 is read at time t30. Hereinafter, similarly, the pixel signal generated from the light exposed during the exposure period from time t(n−1)0 to t(n)0 is read at time t(n)0.

According to FIG. 3, in the pixels R1 and R2 of the pixel sub-array 21R, the pixel signal generated from the light exposed in the exposure period from time t01 to t11 is read out at time t11. Further, the pixel signal generated from the light exposed during the exposure period from time t11 to t21 is read at time t21. Further, the pixel signal generated from the light exposed during the exposure period from time t21 to t31 is read at time t31. Similarly, pixel signals generated from the light exposed during the exposure period from time t(n-1)1 to t(n)1 are read at time t(n)1.

According to FIG. 3, in the pixels G1 and G2 of the pixel sub-array 21G, the pixel signal generated from the light exposed during the exposure period from time t02 to t12 is read at time t12. Further, the pixel signal generated from the light exposed during the exposure period from time t12 to t22 is read at time t22. Further, the pixel signal generated from the light exposed during the exposure period from time t22 to t32 is read at time t32. Hereinafter, similarly, the pixel signal generated from the light exposed during the exposure period from time t(n-1)2 to t(n)2 is read at time t(n)2.

In each of the pixel sub-arrays 21B, 21G and 21R, the potential of the floating diffusion FD of each pixel is reset by turning on the reset transistor RT of each pixel according to the control signal applied via the control line LRT. Further, in each pixel of each pixel sub-array 21B, 21G, 21R, the transfer transistor TX of each pixel is turned on according to the control signal applied via the control line LTX, so that the photoelectric conversion element PD of each pixel is floated. The charges are transferred to the diffusion FD. Further, in each pixel of each pixel sub-array 21B, 21G, 21R, by turning on the output transistor SL of each pixel according to the control signal applied via the control line LSL, the pixel signal can be read from each pixel. Become.

As described above, the pixel signals from the pixels B1 and B2 of the pixel sub-array 21B are read at the times t10, t20, t30,.... The pixel signals from the pixels R1 and R2 of the pixel sub-array 21R are read at times t11, t21, t31,.... Further, the pixel signals from the pixels G1 and G2 of the pixel sub-array 21G are read at times t12, t22, t32,.... In this way, in each column of the pixel array 20, pixel signals from pixels of different pixel sub-arrays are read at different times, so that the pixel sub-arrays 21B, 21G, and 21R can share the signal lines 22a and 22b. For reading pixel signals having a time difference for each of the pixel sub-arrays 21B, 21G, and 21R, as described above, the sizes of the invalid areas N1 and N2 are set to two-thirds of one side of each pixel in the sub-scanning direction. It is realized by.

FIG. 4 is a timing chart showing positions and exposure periods of the pixels B1, B2, G1, G2, R1 and R2 of FIG.

The pixel array 20 moves relatively to the subject in the sub-scanning direction at a predetermined speed. In the upper side of FIG. 4, the horizontal axis represents time, and the vertical axis represents the positions of the pixels B1, B2, G1, G2, R1, R2 in one column of the pixel array 20 relative to the subject. The positions Y1, Y2, Y3,... On the vertical axis are separated from each other by a length equal to one side of each pixel. On the upper side of FIG. 4, each pixel B1, B2, G1, G2, R1, R2 is shown as moving from bottom to top. The moving speed of the pixel array 20 is set to a value obtained by dividing the length of one side of each pixel by the length of time to expose each pixel (for example, the period from time t00 to time t10). Therefore, as described above, the movement time for one pixel is equal to the exposure period for one pixel, and this period is called a "frame". On the lower side of FIG. 4, for each of the pixel sub-arrays 21B, 12G, and 21R, the frame (R1(Y1), R2(Y0), etc.) of the exposure period of each pixel of the pixel sub-array, and the pixel read from each pixel. The frame (R1+R2(Y-1) etc.) which adds a signal is shown.

In frame B1 (Y7), the tip of pixel B1 moves from position Y8 to position Y9. Therefore, in the frame B1 (Y7), when the exposure of the pixel B1 is started, the rear end of the pixel B1 is at the position Y7, and when the exposure of the pixel B1 is ended, the front end of the pixel B1 is at the position Y9.

In frame B2 (Y7), the tip of pixel B2 moves from position Y8 to position Y9. Therefore, in frame B2 (Y7), when the exposure of pixel B2 is started, the rear end of pixel B2 is at position Y7, and when the exposure of pixel B2 is finished, the front end of pixel B2 is at position Y9.

Thus, in the frames B1(Y7) and B2(Y7), the pixels B1 and B2 are exposed when light from the same region of the subject is incident. The pixel signals generated by the pixels B1 and B2 in response to the incident light in the frames B1(Y7) and B2(Y7) indicate the same region of the subject. The generated pixel signals are read out at the end of each frame. The read pixel signals are added to each other in frame B1+B2 (Y7).

Further, as can be seen from FIG. 4, in the frames G1(Y7) and G2(Y7), the pixels G1 and G2 receive light from the same region of the subject as when the pixel B1 was exposed in the frame B1(Y7). Each is exposed while doing. The pixel signals respectively generated by the pixels G1 and G2 in the frames G1(Y7) and G2(Y7) in response to the incident light also have the same subject area as the pixel signals generated by the pixel B1 in the frame B1(Y7). Show. The generated pixel signals are read when the frames G1(Y7) and G2(Y7) are completed. The read pixel signals are added to each other in the frame G1+G2 (Y7).

Similarly, in the frames R1(Y7) and R2(Y7), the pixels R1 and R2 respectively receive the light from the same subject area as when the pixel B1 was exposed in the frame B1(Y7). Exposed. The pixel signals respectively generated by the pixels R1 and R2 in the frames R1(Y7) and R2(Y7) in response to the incident light also have the same subject area as the pixel signals generated by the pixel B1 in the frame B1(Y7). Show. The generated pixel signals are read when the frames R1(Y7) and R2(Y7) are completed. The read pixel signals are added to each other in the frame R1+R2 (Y7).

In this way, since the pixel signals generated by the pixels B1 and B2 respectively indicate the same region of the subject, the solid-state image sensor can operate on these pixel signals by the TDI method. Further, since the pixel signals generated by the pixels G1 and G2 respectively indicate the same area of the subject, the solid-state image sensor can operate with respect to these pixel signals by the TDI method. Further, since the pixel signals generated by the pixels R1 and R2 respectively indicate the same region of the subject, the solid-state image sensor can operate with respect to these pixel signals by the TDI method.

As described above, for each pixel sub-array of the pixel sub-arrays 21B, 21G, and 21R, the two signal lines 22a and 22b are individually connected to the two pixels in each column in the pixel sub-array. Therefore, the two pixels in each column in a certain pixel sub-array can independently output pixel signals via the signal lines 22a and 22b. The signal lines 22a and 22b are shared by the pixels of different pixel sub-arrays 21B, 21G, and 21R. Therefore, it is possible to suppress an increase in the number of signal lines in the solid-state image sensor as a whole.

As described above, according to the solid-state image sensor of FIG. 1, when the pixels aligned in the sub-scanning direction are exposed, the relative position between the target position of the subject and the pixels is exposed without impairing the degree of freedom of the size and the interval of each pixel. The positions can be matched to each other among the pixels. The solid-state image sensor of FIG. 1 is applicable to a CMOS solid-state image sensor and can operate in the TDI system.

Further, according to the solid-state imaging device of FIG. 1, it is not necessary to reduce the pixel interval and the pixel size in order to reduce the deviation of the relative position between the target position of the subject and the pixel. There is no problem that the sensitivity is reduced due to the reduction of the size of the.

FIG. 5 is a diagram showing a configuration of a pixel array 20A according to a modified example of Embodiment 1 of the present invention. In the pixel array 20 of the solid-state imaging device of FIG. 1, each column of each pixel sub-array 21B, 21G, 21R includes two pixels (two rows), but the present invention is not limited to this. In the pixel array 20A of FIG. 5, each column of each pixel sub-array 21B, 21G, 21R includes three pixels (three rows).

Referring to FIG. 5, the pixel sub-array 21B has a plurality of rows (three rows in FIG. 5) along the main scanning direction and a plurality of columns arranged two-dimensionally so as to form a plurality of columns along the sub-scanning direction. The pixels B1 to B3 are included. The pixel sub-array 21G includes a plurality of pixels G1 to G3 arranged two-dimensionally so as to form a plurality of rows (three rows in FIG. 5) along the main scanning direction and a plurality of columns along the sub-scanning direction. .. The pixel sub-array 21R includes a plurality of pixels R1 to R3 arranged two-dimensionally so as to form a plurality of rows (three rows in FIG. 5) along the main scanning direction and a plurality of columns along the sub-scanning direction. ..

For each column of the pixel array 20A, the pixels B1 to B3 of the pixel sub array 21B, the pixels G1 to G3 of the pixel sub array 21G, and the pixels R1 to R3 of the pixel sub array 21R are aligned in the sub-scanning direction.

In each column of the pixel sub-array 21B, the pixels B1 to B3 are connected to different signal lines 22a to 22c, respectively. In each column of the pixel sub-array 21G, the pixels G1 to G3 are connected to different signal lines 22a to 22c, respectively. In each column of the pixel sub-array 21R, the pixels R1 to R3 are connected to different signal lines 22a to 22c, respectively.

In the pixels B1 to B3, G1 to G3, and R1 to R3 arranged along the sub-scanning direction, at least one pixel in one pixel sub array of the pixel sub arrays 21B, 21G, and 21R has at least one pixel sub array 21B, 21G, and 21R. At least one pixel in at least one other pixel sub-array is connected to the connected signal line. In the case of FIG. 5, in the pixels B1 to B3, G1 to G3, and R1 to R3 arranged along the sub-scanning direction, one pixel from each pixel sub array 21B, 21G, and 21R is connected to one signal line. .. Therefore, in each column of the pixel array 20A, the pixel B1, the pixel G1, and the pixel R1 are connected to the signal line 22a, the pixel B2, the pixel G2, and the pixel R2 are connected to the signal line 22b, and the pixel B3, the pixel G3, And the pixel R3 is connected to the signal line 22c.

The pixel control circuit controls generation of pixel signals by the pixels B1 to B3, G1 to G3, and R1 to R3 via a plurality of control lines. The control lines include, for example, control lines L11 to L13, L21 to L23, and L31 to L33 which are respectively connected to the transfer transistors of each pixel. Although omitted for simplification of illustration, the reset transistor and output of each pixel are included. It also includes other control lines each connected to a transistor.

The solid-state image sensor including the pixel array 20A of FIG. 5 also has the same effect as the solid-state image sensor of FIG.

In the pixel array, each column of each pixel sub-array 21B, 21G, 21R may include four or more pixels.

Also, the pixel array may include two or more than four pixel sub-arrays. In this case, the size of the invalid area is set to M/N, which is the size of one side of each pixel in the sub-scanning direction, where N is the number of pixel sub-arrays and M is a coprime integer. This allows the pixel signals to be read out with a time difference for each pixel sub-array.

Embodiment 2.
FIG. 6 is a block diagram showing the overall configuration of the solid-state image sensor according to the second embodiment of the present invention.
The solid-state image sensor of FIG. 6 includes a pixel control circuit 10, a pixel array 20B, output control circuits 30-1 and 30-2, and readout circuits 40-1 and 40-2.

Each pixel of the pixel array 20B is two-dimensionally arranged in the main scanning direction (X direction of FIG. 6) and the sub scanning direction (Y direction of FIG. 6), as in the pixel array 20 of FIG. Like the pixel array 20 of FIG. 1, the pixel array 20B includes a plurality of pixel sub arrays 21B, 21G, and 21R arranged at predetermined intervals in the sub scanning direction. For each column of the pixel array 20B, similarly to the pixel array 20 of FIG. 1, the pixels B1 and B2 of the pixel sub array 21B, the pixels G1 and G2 of the pixel sub array 21G, and the pixels R1 and R2 of the pixel sub array 21R are arranged in the sub-scanning direction. To line up.

The solid-state imaging device further includes a plurality (four in FIG. 6) of pixel circuits 23a to 23d that read out pixel signals from the pixels B1, B2, G1, G2, R1, and R2 and output the signal to the signal lines 22a and 22b. The pixels B1, B2, G1, G2, R1, R2 are connected to the signal lines 22a, 22b via the pixel circuits 23a-23d. The pixel circuits 23a to 23d have a size of two-thirds of one side of each pixel in the sub-scanning direction, similarly to the invalid areas N1 and N2 in FIG.

The pixel circuit 23b is provided between two pixels B2 and G1 facing each other between two pixel sub-arrays 21B and 21G adjacent to each other, and is shared by the two pixels B2 and G1. In each column of the pixel array 20, the pixel circuit 23c is provided between two pixels G2 and R1 facing each other between two pixel sub arrays 21G and 21R adjacent to each other, and is shared by the two pixels G2 and R1. It The pixel circuit 23a is provided adjacent to the pixel B1 at one end of the pixels B1, B2, G1, G2, R1 and R2 aligned along the sub-scanning direction. The pixel circuit 23d is provided adjacent to the pixel R2 at the other end of the pixels B1, B2, G1, G2, R1 and R2 arranged in the sub-scanning direction. In the present specification, the former two pixel circuits 23b and 23c are also referred to as “first pixel circuit”, and the latter two pixel circuits 23a and 23d are also referred to as “second pixel circuit”.

For the pixels B1, B2, G1, G2, R1 and R2 aligned along the sub-scanning direction, the plurality of pixel circuits 23a to 23d are alternately connected to the two signal lines 22a and 22b. In the case of FIG. 6, the pixel circuits 23a and 23c are connected to the signal line 22a, and the pixel circuits 23b and 23d are connected to the signal line 22b.

In the solid-state image sensor of FIG. 6, read circuits 40-1 and 40-2 are connected to both ends of the signal lines 22a and 22b of each column of the pixel array 20B, respectively. The read circuits 40-1 and 40-2 are configured and operate similarly to the read circuit 40 of FIG. The output control circuits 30-1 and 30-2 are configured and operate similarly to the output control circuit 30 of FIG.

FIG. 7 is a circuit diagram showing a detailed configuration of the pixel array 20B of FIG. Different from the pixel of FIG. 2, each pixel B1, B2, G1, G2, R1, R2 of FIG. 7 includes only the photoelectric conversion element PD, and the other constituent elements shown in the pixel of FIG. 23d. The pixel control circuit 10 controls the generation of pixel signals by the pixels B1, B2, G1, G2, R1 and R2 via a plurality of control lines. The control lines include control lines L11, L12, L21, L22, L31, and L32 connected to the transfer transistors TX1 and TX2 of each pixel, respectively. Although omitted in FIG. 6, they are connected to the reset transistor RT of each pixel. Control lines LRT1 to LRT4.

FIG. 8 is a circuit diagram showing a detailed configuration of the pixel circuits 23a to 23d of FIG. Each of the pixel circuits 23a to 23d includes transfer transistors TX1 and TX2, a floating diffusion FD, a reset transistor RT, and an amplification transistor SF. These components of each pixel circuit 23a-23d are configured and operate similarly to the corresponding components of the pixel of FIG.

As described above, the pixel circuit 23b is shared by the pixels B2 and G1. Referring to FIG. 8, PD1 indicates the photoelectric conversion element PD of the pixel B2, and PD2 indicates the photoelectric conversion element PD of the pixel G1. The transfer transistor TX1 transfers charges from the photoelectric conversion element PD1 to the floating diffusion FD, and the transfer transistor TX2 transfers charges from the photoelectric conversion element PD2 to the floating diffusion FD. The floating diffusion FD, the reset transistor RT, and the amplification transistor SF of the pixel circuit 23b are shared to process the charges from the photoelectric conversion elements PD1 and PD2.

Further, as described above, the pixel circuit 23c is shared by the pixels B2 and G1. The pixel circuit 23c also operates similarly to the pixel circuit 23b.

Considering the repeatability of the circuit configuration, the pixel circuits 23a and 23d may also be configured to include two transfer transistors TX1 and TX2, like the pixel circuits 23b and 23c. Alternatively, the pixel circuits 23a and 23d may be configured to include one transfer transistor that transfers charges from one photoelectric conversion element to the floating diffusion.

The pixel circuits 23a to 23d in FIG. 8 do not include the output transistor SL in the pixel in FIG. Therefore, the pixel signal generated by the amplification transistor SF can always be read out via the terminal VOUT. In the pixel circuits 23a to 23d of FIG. 8, the pixel signal is selectively output to the signal lines 22a and 22b via the terminal VOUT according to the control signal applied to the gates of the transfer transistors TX1 and TX2.

According to the solid-state image sensor of FIG. 6, since the constituent elements other than the photoelectric conversion element of each pixel are provided in the pixel circuit outside the pixel, and two pixels share one pixel circuit, the solid-state image sensor of FIG. The circuit scale can be reduced as compared with the case of the image sensor. Moreover, the circuit scale can be reduced by not having the output transistor SL of FIG. Further, in each pixel sub-array, the time difference between the read times of the pixel signals indicating the same region of the subject can be reduced.

Further, referring to FIG. 7, the control lines L11 and LRT1 for the transfer transistor TX2 and the reset transistor of the pixel circuit 23a are provided adjacent to the pixel B1 without overlapping the pixel B1. The control lines L12, L21, LRT2 for the transfer transistors TX1, TX2 and the reset transistor RT of the pixel circuit 23b are provided between the pixels B2, G1 without overlapping the pixels B2, G1. The control lines L22, L31, LRT3 for the transfer transistors TX1, TX2 and the reset transistor RT of the pixel circuit 23c are provided between the pixels G2, R1 without overlapping the pixels G2, R1. The control lines L32 and LRT4 for the transfer transistor TX1 and the reset transistor of the pixel circuit 23d are provided adjacent to the pixel R2 without overlapping the pixel R2. The control lines for the transfer transistors TX1 and TX2 and the reset transistor RT of the pixel circuits 23b and 23c are provided between two pixels that face each other between two pixel sub arrays that are adjacent to each other. The control lines for the transfer transistors TX1 and TX2 and the reset transistor RT of the pixel circuits 23a and 23d are provided adjacent to the pixels at both ends of the plurality of pixels arranged in the sub-scanning direction.

Since the control line is arranged outside the pixel in this way, the control line does not overlap the photoelectric conversion element, and the influence on the photoelectric conversion element due to the presence of the control line can be reduced.

The positions of the pixels B1, B2, G1, G2, R1 and R2 when the solid-state image sensor of FIG. 6 captures an image and the exposure period are the same as those described with reference to FIG. 4, and the description thereof will be omitted.

The solid-state image sensor of FIG. 1 also includes output control circuits 30-1 and 30-2 and read circuits 40-1 and 40-2 at both ends of each signal line 22a and 22b, as in the solid-state image sensor of FIG. May be.

FIG. 9 is a block diagram showing the overall configuration of a solid-state image sensor according to a modification of the second embodiment of the present invention. FIG. 10 is a circuit diagram showing a detailed configuration of the pixel array 20C of FIG. The solid-state image sensor of FIG. 9 includes a pixel control circuit 10, a pixel array 20C, output control circuits 30-1 and 30-2, and read circuits 40C-1 and 40C-2.

Each pixel of the pixel array 20C is two-dimensionally arranged in the main scanning direction (X direction of FIG. 6) and the sub scanning direction (Y direction of FIG. 6), as in the pixel array 20 of FIG. The pixel array 20C includes a plurality of pixel sub-arrays 21B, 21G, and 21R arranged at predetermined intervals in the sub-scanning direction, similar to the pixel array 20 of FIG. For each column of the pixel array 20C, similarly to the pixel array 20 of FIG. 1, the pixels B1 and B2 of the pixel sub-array 21B, the pixels G1 and G2 of the pixel sub-array 21G, and the pixels R1 and R2 of the pixel sub-array 21R are arranged in the sub-scanning direction. To line up.

The solid-state imaging device includes pixel circuits 23a to 23d similar to the pixel circuits 23a to 23d in FIG. However, the pixel circuit 23a is connected to the additional signal line 22d instead of the signal line 22a, and the pixel circuit 23d is connected to the additional signal line 22e instead of the signal line 22b. The pixel circuits 23b and 23c are alternately connected to the signal lines 22a and 22b.

In the solid-state image sensor of FIG. 6, read circuits 40C-1 and 40C-2 are connected to both ends of the signal lines 22a and 22b of each column of the pixel array 20C, respectively. The readout circuit 40C-1 further includes an amplifier 41 provided for each signal line 22d in each column of the pixel array 20C, and has a plurality of memories and addition circuits 42C in place of the plurality of memories and addition circuits 42 in FIG. Prepare Each memory of the read circuit 40C-1 and the adder circuit 42C are connected to the signal lines 22a, 22b, 22d of each column of the pixel array 20C via the amplifier 41. The readout circuit 40C-2 further includes an amplifier 41 provided for each signal line 22e in each column of the pixel array 20C, and has a plurality of memories and addition circuits 42C in place of the plurality of memories and addition circuits 42 in FIG. Prepare Each memory of the read circuit 40C-2 and the adder circuit 42C are connected to the signal lines 22a, 22b, 22e of each column of the pixel array 20C via the amplifier 41. Otherwise, the read circuits 40C-1 and 40C-2 are configured and operate in the same manner as the read circuit 40 of FIG. Further, the output control circuits 30-1 and 30-2 are configured and operate similarly to the output control circuit 30 of FIG.

The solid-state image sensor of FIG. 9 also has the same effect as the solid-state image sensor of FIG.

Embodiment 3.
FIG. 11 is a block diagram showing the configuration of the image pickup apparatus according to the third embodiment of the present invention. The imaging device of FIG. 11 includes a lens 1, a solid-state imaging device 2, a driving device 3, and a signal processing circuit 4. The imaging device in FIG. 11 is, for example, a camera.

The solid-state image sensor 2 is the solid-state image sensor according to the first or second embodiment.

The lens 1 is an optical system that guides incident light to each pixel of the solid-state image sensor 2.

The drive device 3 moves the solid-state image sensor 2 relative to the subject in the sub-scanning direction at a predetermined speed. The driving device 3 includes a timing generator that generates a timing signal for driving each circuit in the imaging device, and drives the imaging device.

The signal processing circuit 4 processes the output signal of the solid-state image sensor 2.

The output signal of the signal processing circuit 4 may be recorded in a recording medium such as a memory. The image information recorded on the recording medium may be hard-copied by a printer or the like. The output signal of the signal processing circuit 4 may be displayed as a still image or a moving image on a monitor such as a liquid crystal display.

When the output signal of the signal processing circuit 4 is an analog signal, an analog/digital conversion circuit (AFE) may be provided at the subsequent stage of the signal processing circuit 4. When the output signal of the signal processing circuit 4 is a digital signal, a digital signal processing circuit (DFE) may be provided at the subsequent stage of the signal processing circuit 4.

As described above, by mounting the solid-state imaging device according to the first or second embodiment, it is possible to realize a highly accurate imaging device (camera or the like).

A solid-state imaging device and an imaging device according to aspects of the present invention have the following configurations.

According to the solid-state image sensor according to the first aspect,
A solid-state imaging device comprising a pixel array in which a plurality of pixels that respectively generate pixel signals according to incident light are two-dimensionally arranged in a main scanning direction and a sub scanning direction,
The pixel array includes a plurality of pixel sub-arrays arranged at predetermined intervals in the sub-scanning direction, and each one pixel sub-array among the plurality of pixel sub-arrays is a plurality of pixels in the main-scanning direction. And a plurality of pixels arranged two-dimensionally so as to form a plurality of rows and a plurality of columns along the sub-scanning direction,
The solid-state image sensor,
For each one pixel sub-array of the plurality of pixel sub-arrays, a plurality of signal lines individually connected to the plurality of pixels of each column in the pixel sub-array,
A memory for temporarily storing pixel signals read from the plurality of pixels via the plurality of signal lines;
An adder circuit that adds pixel signals read from a plurality of pixels in the same column to each other for each one pixel sub-array of the plurality of pixel sub-arrays,
The plurality of pixels in each column in one pixel sub-array of the plurality of pixel sub-arrays are arranged on a column-by-column basis in the sub-scanning direction along the sub-scanning direction. Aligned with multiple pixels in a row,
In the plurality of pixels aligned along the sub-scanning direction, at least one pixel in one pixel sub-array of the plurality of pixel sub-arrays is at least in another pixel sub-array of at least one of the plurality of pixel sub-arrays. It is connected to a signal line to which one pixel is connected.

According to the solid-state image sensor according to the second aspect, in the solid-state image sensor according to the first aspect,
In the plurality of pixels arranged in the sub-scanning direction, one pixel from each pixel sub-array is connected to one signal line.

According to the solid-state image sensor according to the third aspect, in the solid-state image sensor according to the second aspect,
Each pixel is
A photoelectric conversion element for converting the incident light into an electric charge;
With floating diffusion,
A transfer transistor for transferring charges from the photoelectric conversion element to the floating diffusion;
A reset transistor for resetting the potential of the floating diffusion,
An amplifying transistor for amplifying a voltage in the floating diffusion to generate a pixel signal,
And an output transistor that selectively outputs the pixel signal to the signal line.

According to the solid-state image sensor according to the fourth aspect, in the solid-state image sensor according to the first aspect,
Each column in each pixel sub-array includes two pixels,
The solid-state imaging device further includes a plurality of pixel circuits that read out the pixel signals from the plurality of pixels and output the signal lines to the signal lines, and the plurality of pixels are connected to the plurality of signal lines via the plurality of pixel circuits. The plurality of pixel circuits are provided between two pixels facing each other between two pixel sub-arrays adjacent to each other, and a first pixel circuit shared by the two pixels, and the sub-scanning. A second pixel circuit provided adjacent to the pixels at both ends of the plurality of pixels aligned along the direction,
Regarding the plurality of pixels arranged in the sub-scanning direction, the plurality of pixel circuits are alternately connected to two signal lines.

According to the solid-state image sensor according to the fifth aspect, in the solid-state image sensor according to the first aspect,
Each column in each pixel sub-array includes two pixels,
The solid-state imaging device further includes a plurality of pixel circuits that read out the pixel signals from the plurality of pixels and output the signal lines to the signal lines, and the plurality of pixels are connected to the plurality of signal lines via the plurality of pixel circuits. The plurality of pixel circuits are provided between two pixels facing each other between two pixel sub-arrays adjacent to each other, and a first pixel circuit shared by the two pixels, and the sub-scanning. A second pixel circuit provided adjacent to the pixels at both ends of the plurality of pixels aligned along the direction,
For the plurality of pixels arranged in the sub-scanning direction, the first pixel circuits are alternately connected to two signal lines, and the second pixel circuits are connected to additional signal lines.

According to the solid-state image sensor according to the sixth aspect, in the solid-state image sensor according to the fourth or fifth aspect,
Each of the pixels includes a photoelectric conversion element that converts the incident light into an electric charge,
Each of the pixel circuits is
With floating diffusion,
One or two transfer transistors that transfer charge from one or two of the photoelectric conversion elements to the floating diffusion;
A reset transistor for resetting the potential of the floating diffusion,
And an amplification transistor that amplifies a voltage in the floating diffusion to generate a pixel signal.

According to the solid-state image sensor according to the seventh aspect, in the solid-state image sensor according to the sixth aspect,
The control lines for the transfer transistor and the reset transistor of the first pixel circuit are provided between two pixels facing each other between two pixel sub-arrays adjacent to each other,
The control lines for the transfer transistor and the reset transistor of the second pixel circuit are provided adjacent to pixels at both ends of the plurality of pixels aligned in the sub-scanning direction.

According to the solid-state image sensor according to the eighth aspect, in the solid-state image sensor according to one of the first to seventh aspects,
The solid-state image sensor,
A first memory and a first addition circuit connected to one end of the plurality of signal lines;
A second memory and a second adder circuit connected to the other ends of the plurality of signal lines are provided.

According to the solid-state image sensor according to the ninth aspect,
A solid-state imaging device according to one of the first to eighth aspects,
An optical system that guides incident light to each pixel of the solid-state image sensor,
A signal processing circuit for processing an output signal of the solid-state image sensor;
And a drive device that moves the solid-state imaging device relative to the subject in the sub-scanning direction at a predetermined speed.

1... lens,
2... Solid-state image sensor,
3... Drive device,
4... Signal processing circuit,
10... Pixel control circuit,
20, 20A to 20C... Pixel array,
21B, 21G, 21R... Pixel sub-array,
22a to 22e... Signal line,
23a to 23d... Pixel circuit,
30, 30-1, 30-2... Output control circuit,
40, 40-1, 40-2, 40C-1, 40C-2... Readout circuit,
41...Amplifier,
42, 42C... Memory and adder circuit,
43... Analog-to-digital converter (ADC),
44... Digital transfer circuit,
45... amplifier,
B1, B2, B3, G1, G2, G3, R1, R2, R3... Pixel,
FD... floating diffusion,
L11 to L33, LRT1 to LRT4... Control lines,
N1, N2... invalid area,
PD, PD1, PD2... Photoelectric conversion element,
RT... reset transistor,
SF... Amplifying transistor,
SL... Output transistor,
TX, TX1, TX2... Transfer transistors.

Japanese Patent No. 5594362

Claims (9)

A solid-state image sensor including a pixel array in which a plurality of pixels that respectively generate pixel signals according to incident light are two-dimensionally arranged in a main scanning direction and a sub scanning direction,
The pixel array includes a plurality of pixel sub-arrays arranged at predetermined intervals in the sub-scanning direction, and each one pixel sub-array among the plurality of pixel sub-arrays is a plurality of pixels in the main-scanning direction. And a plurality of pixels arranged two-dimensionally so as to form a plurality of rows and a plurality of columns along the sub-scanning direction,
The solid-state image sensor,
For each one pixel sub-array of the plurality of pixel sub-arrays, a plurality of signal lines individually connected to the plurality of pixels of each column in the pixel sub-array,
A memory for temporarily storing pixel signals read from the plurality of pixels via the plurality of signal lines;
For each one pixel sub-array of the plurality of pixel sub-arrays, an adding circuit that adds pixel signals read from a plurality of pixels in the same column to each other is provided for each column,
The plurality of pixels in each column in one pixel sub-array of the plurality of pixel sub-arrays are arranged on a column-by-column basis in the sub-scanning direction along the sub-scanning direction. Aligned with multiple pixels in a row,
In the plurality of pixels arranged along the sub-scanning direction, at least one pixel in one pixel sub-array of the plurality of pixel sub-arrays is at least in another at least one pixel sub-array of the plurality of pixel sub-arrays. A solid-state image sensor connected to a signal line to which one pixel is connected. The solid-state imaging device according to claim 1, wherein, in the plurality of pixels arranged in the sub-scanning direction, one pixel from each pixel sub-array is connected to one signal line. Each pixel is
A photoelectric conversion element for converting the incident light into an electric charge;
With floating diffusion,
A transfer transistor for transferring charges from the photoelectric conversion element to the floating diffusion;
A reset transistor for resetting the potential of the floating diffusion,
An amplifying transistor for amplifying a voltage in the floating diffusion to generate a pixel signal,
The solid-state imaging device according to claim 2, further comprising an output transistor that selectively outputs the pixel signal to the signal line. Each column in each pixel sub-array includes two pixels,
The solid-state imaging device further includes a plurality of pixel circuits that read out the pixel signals from the plurality of pixels and output the signal lines to the signal lines, and the plurality of pixels are connected to the plurality of signal lines via the plurality of pixel circuits. The plurality of pixel circuits are provided between two pixels facing each other between two pixel sub-arrays adjacent to each other, and a first pixel circuit shared by the two pixels, and the sub-scanning. A second pixel circuit provided adjacent to the pixels at both ends of the plurality of pixels aligned along the direction,
The solid-state image pickup device according to claim 1, wherein the plurality of pixel circuits are alternately connected to two signal lines for a plurality of pixels arranged in the sub-scanning direction. Each column in each pixel sub-array includes two pixels,
The solid-state imaging device further includes a plurality of pixel circuits that read out the pixel signals from the plurality of pixels and output the signal lines to the signal lines, and the plurality of pixels are connected to the plurality of signal lines via the plurality of pixel circuits. The plurality of pixel circuits are provided between two pixels facing each other between two pixel sub-arrays adjacent to each other, and a first pixel circuit shared by the two pixels, and the sub-scanning. A second pixel circuit provided adjacent to the pixels at both ends of the plurality of pixels aligned along the direction,
The first pixel circuit is alternately connected to two signal lines, and the second pixel circuit is connected to an additional signal line with respect to a plurality of pixels aligned along the sub-scanning direction. Solid-state image sensor. Each of the pixels includes a photoelectric conversion element that converts the incident light into an electric charge,
Each of the pixel circuits is
With floating diffusion,
One or two transfer transistors that transfer charge from one or two of the photoelectric conversion elements to the floating diffusion;
A reset transistor for resetting the potential of the floating diffusion,
The solid-state imaging device according to claim 4, further comprising an amplification transistor that amplifies a voltage in the floating diffusion to generate a pixel signal. The control lines for the transfer transistor and the reset transistor of the first pixel circuit are provided between two pixels facing each other between two pixel sub-arrays adjacent to each other,
7. The control line for the transfer transistor and the reset transistor of the second pixel circuit is provided adjacent to pixels at both ends of a plurality of pixels aligned in the sub-scanning direction. Solid-state image sensor. The solid-state image sensor,
A first memory and a first addition circuit connected to one end of the plurality of signal lines;
The solid-state image sensor according to claim 1, further comprising a second memory and a second adder circuit connected to the other ends of the plurality of signal lines. A solid-state image sensor according to claim 1;
An optical system that guides incident light to each pixel of the solid-state image sensor,
A signal processing circuit for processing an output signal of the solid-state image sensor;
An image pickup apparatus comprising: a drive device that moves the solid-state image pickup element relative to a subject in the sub-scanning direction at a predetermined speed.

Images