JP2011023917A - Solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element which reduces variation in the signal of a pixel to be read first in a pixel block and signals to be read from other blocks in the pixel block. <P>SOLUTION: A vertical scanning circuit sequentially turns on transfer transistors TX1, TX2 of a pixel block 20 of the n-th line in mutually different timing. The vertical scanning circuit turns on the reset transistor RES of the n-th line in a predetermined period (periods t2-t3 and periods t5-t6) before on-periods of the respective transfer transistors TX1, TX2. Length of the on-periods t2-t3 of the reset transistor RES of the n-th line immediately before the on-period of the transistor TX1 which is turned on first among the transfer transistors TX1, TX2 of the pixel block of the n-th line is set to T which is the same as the length of the on-periods t5-t6 of the reset transistor RES of the n-th line immediately before the on-period of the other transfer transistor TX2 of the pixel block 20 of the n-th line. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  In the solid-state imaging device disclosed in Patent Document 1 below, a pixel block is formed for each predetermined number of pixels, and for each pixel block, the predetermined number of pixels belonging to the pixel block includes a set of charge-voltage conversion units and an amplification unit. The transistor, the reset transistor, and the selection transistor are shared. Therefore, the number of transistors per pixel can be reduced and the aperture ratio can be increased. When the aperture ratio is large, a lot of charges are handled, and the SN ratio is improved.

1 and 3 of JP-A-9-46596, etc.

  However, in the conventional solid-state imaging device, when a signal is output independently from all the pixels, even when uniform light is irradiated, the signal of the pixel read first in the pixel block and other signals in the pixel block As a result, the signal read out from the other pixel varies, and the image quality deteriorates.

  The present invention has been made in view of such circumstances, and can reduce variation between a signal of a pixel read first in a pixel block and a signal read from another pixel in the pixel block. An object is to provide a solid-state imaging device.

  The following aspects are presented as means for solving the problems. The solid-state imaging device according to the first aspect includes a plurality of photoelectric conversion units, a charge-voltage conversion unit that is provided in common to the plurality of photoelectric conversion units and converts a transferred charge into a voltage, and the plurality of photoelectric conversion units. A transfer switch that is provided corresponding to each of the plurality of photoelectric conversion units to transfer charges from the plurality of photoelectric conversion units to the charge voltage conversion unit, an amplification transistor that outputs a signal corresponding to a potential of the charge voltage conversion unit, and the charge voltage conversion A reset switch for resetting the potential of the unit and a transfer switch provided corresponding to the charge-voltage conversion unit are sequentially turned on at different timings, and the reset switch is turned on before the on-period of each transfer switch, A control unit configured to set the length of the on period of the reset switch that is turned on first to 1.5 or less of the length of the on period of the other reset switch. Than is. The plurality of pixels may be sequentially arranged in a predetermined direction.

  In the solid-state imaging device according to the second aspect, in the first aspect, the length of the on-period of the reset switch that is turned on first is equal to or longer than the length of the on-period of the other reset switches. There is something.

  In the solid-state imaging device according to the third aspect, in the first aspect, the length of the on-period of the reset switch that is turned on first is the same as the length of the on-period of the other reset switches. is there.

  In any one of the first to third aspects, the solid-state imaging device according to the fourth aspect is the start of the on-period of the transfer switch for any of the transfer switches provided corresponding to the charge-voltage converter. The time interval between the time and the end of the on period of the reset switch immediately before the on period of the transfer switch is the same.

  The solid-state imaging device according to a fifth aspect is the solid-state imaging device according to any one of the first to fourth aspects, wherein the reset switch is turned off during a period other than the on-period of the reset switch immediately before the on-period of each transfer switch. It is maintained.

  In the solid-state imaging device according to the sixth aspect, in any one of the first to fourth aspects, the reset switch is repeatedly turned on and off at a constant cycle and duty.

  In any one of the first to fourth aspects, the solid-state imaging device according to the seventh aspect is the first period before the on period of the reset switch immediately before the on period of the transfer switch that is first turned on. The reset switch OFF period immediately before the ON period of the reset switch immediately before the ON period of the transfer switch to be turned ON, and the ON period of the reset switch before that.

  A solid-state imaging device according to an eighth aspect includes a plurality of photoelectric conversion units, a charge-voltage conversion unit that is provided in common to the plurality of photoelectric conversion units and converts a transferred charge into a voltage, and the plurality of photoelectric conversion units A transfer switch that is provided corresponding to each of the plurality of photoelectric conversion units to transfer charges from the plurality of photoelectric conversion units to the charge voltage conversion unit, an amplification transistor that outputs a signal corresponding to a potential of the charge voltage conversion unit, and the charge voltage conversion A reset switch for resetting the potential of the unit and a transfer switch provided corresponding to the charge-voltage conversion unit are sequentially turned on at different timings, and the charge-voltage conversion unit before the on-period of each transfer switch And a control unit that controls the reset switch so that the reset state of the charge-voltage conversion unit is the same.

  ADVANTAGE OF THE INVENTION According to this invention, the solid-state image sensor which can reduce the dispersion | variation between the signal of the pixel read first in a pixel block and the signal read from the other pixel in the pixel block can be provided.

1 is a circuit diagram illustrating a schematic configuration of a solid-state imaging device according to a first embodiment of the present invention. It is a circuit diagram which shows the pixel block of the solid-state image sensor shown in FIG. 3 is a timing chart illustrating a read operation of the solid-state imaging element according to the first embodiment of the present invention. It is a timing chart which shows the read-out operation | movement of the solid-state image sensor by a comparative example. It is a figure which shows typically the relationship between the voltage of a floating diffusion, and the voltage of a vertical signal line. It is a timing chart which shows the read-out operation | movement of the solid-state image sensor by the 2nd Embodiment of this invention. It is a timing chart which shows the read-out operation | movement of the solid-state image sensor by the 3rd Embodiment of this invention.

  Hereinafter, a solid-state imaging device according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit diagram showing a schematic configuration of a solid-state imaging device according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing the pixel block 20 of the solid-state imaging device shown in FIG. The solid-state imaging device according to the present embodiment is formed as a CMOS solid-state imaging device.

  As shown in FIG. 1, the solid-state imaging device according to the present embodiment includes a plurality of pixels 1 arranged in a two-dimensional shape (in FIG. 1, 4 × 4 × 2 pixels 1 (4 × 4 pixel blocks). 20) only)), the vertical scanning circuit 2, the horizontal scanning circuit 3, the drive signal lines 11 to 15 connected thereto, and the pixel 1 for each column provided for each column of the pixel 1. Are supplied to the vertical signal line 4, the constant current source 5 and the column amplifier 6 connected to each vertical signal line 4, a switch 7 formed of a transistor, and a signal output from the column amplifier 6 through the switch 7. And a horizontal signal line 8 and an output amplifier 9 are provided.

  In this embodiment, the correlated double sampling circuit (CDS circuit) is provided outside the solid-state imaging device, and the correlated double sampling process is performed after the signal is output to the outside through the output amplifier 9. It has come to be. However, it goes without saying that the CDS circuit may be mounted on the solid-state imaging device. In this case, the CDS circuit may be configured using the column amplifier 6.

  In the present embodiment, each pixel 1 has a photodiode PD as a photoelectric conversion unit that generates and accumulates signal charges according to incident light, and a transfer as a transfer switch that transfers charges from the photodiode PD to the floating diffusion FD. And a transistor TX.

  In the drawing, in the pixel block 20 described later, the upper pixel in FIGS. 1 and 2 is denoted by 1-1 and the lower pixel in FIGS. 1 and 2 is denoted by 1-2. Although they are different, when they are described without distinguishing between them, there are cases where they are described with reference numeral 1 attached. In the drawing, the photodiode of the pixel 1-1 is denoted by PD1, and the photodiode of the pixel 1-2 is identified by PD2, and they are distinguished from each other. May be described. Similarly, the transfer transistor of the pixel 1-1 is denoted by TX1 and the transfer transistor of the pixel 1-2 is denoted by TX2. The two are distinguished from each other. May be explained.

  In the present embodiment, the plurality of pixels 1 form a pixel block 20 for every two pixels 1 in which photodiodes PD are sequentially arranged in the column direction. As shown in FIG. 2, for each pixel block 20, two pixels 1 (1-1, 1-2) belonging to the pixel block 20 have a set of floating diffusion FD, amplification transistor AMP, and reset transistor RES. And the selection transistor SEL is shared. The floating diffusion FD constitutes a charge-voltage conversion unit that converts the transferred charge into a voltage. The amplification transistor AMP constitutes an amplification unit that outputs a signal corresponding to the potential of the floating diffusion FD. The reset transistor RES constitutes a reset switch that resets the potential of the floating diffusion FD. The selection transistor SEL constitutes a selection unit for selecting the pixel 1. The photodiode PD and the transfer transistor TX are provided for each pixel 1 without being shared by the two pixels 1 (1-1, 1-2). 1 and 2, n indicates a row of the pixel block 20. For example, a pixel block 20 in the first row is constituted by the pixel 1 in the first row and a pixel 1 in the second row, and the pixel block 20 in the second row is constituted by the pixel 1 in the third row and the pixel 1 in the fourth row. Is configured.

  The gate of the transfer transistor TX is connected to control lines 12 and 14 for supplying a drive signal φTX for controlling the transfer transistor TX from the vertical scanning circuit 2 to the transfer transistor TX for each pixel row. However, the drive signal φTX includes a drive signal φTX1 supplied to the upper transfer transistor TX1 of each pixel block row via the control line 12, and a lower transfer transistor of each pixel block row via the control line 14. There is a drive signal φTX2 supplied to TX2.

  A gate of the reset transistor RES is connected to a control line 11 that supplies a drive signal φRST for controlling the reset transistor RES from the vertical scanning circuit 2 to the reset transistor RES for each pixel block row. The gate of the selection transistor SEL is connected to a control line 13 that supplies a driving signal φSEL for controlling the selection transistor SEL from the vertical scanning circuit 2 to the selection transistor SEL for each pixel block row.

  The photodiode PD generates a signal charge according to the amount of incident light (subject light). The transfer transistor TX is turned on during the high level period of the transfer pulse (drive signal) φTX, and transfers the signal charge accumulated in the photodiode PD to the floating diffusion FD. The reset transistor RES is turned on during a high level period of the reset pulse (drive signal) φRST, and resets the floating diffusion FD.

  The amplification transistor AMP has a drain connected to the power supply voltage Vdd, a gate connected to the floating diffusion FD, a source connected to the drain of the selection transistor SEL, and a source follower circuit having the constant current source 5 as a load. is doing. The amplification transistor AMP outputs a read current to the vertical signal line 4 via the selection transistor SEL according to the voltage value of the floating diffusion FD. The selection transistor SEL is turned on during the high level period of the selection pulse (drive signal) φSEL, and connects the source of the amplification transistor AMP to the vertical signal line 4.

  In the present embodiment, the transistors AMP, TX (TX1, TX2), RES, and SEL of the pixel 1 are all nMOS transistors. In FIG. 2, Vdd is a power supply voltage.

  The vertical scanning circuit 2 constitutes a control unit that outputs a selection pulse φSEL, a reset pulse φRST, and a transfer pulse φTX (φTX1, φTX2) for each row of the pixel block 20. The horizontal scanning circuit 3 outputs drive signals φH1 to φH4 that control the switch 7.

  FIG. 3 is a timing chart showing the reading operation of the solid-state imaging device according to the present embodiment. 3 schematically shows not only the drive signals φSEL, φTX1, φTX2, and φRST supplied from the vertical scanning circuit 2, but also the voltage value of the floating diffusion FD (gate potential of the amplification transistor AMP) generated thereby. is doing. Note that (n) indicates a signal of the pixel block 20 in the n-th row.

  In this embodiment, after a mechanical shutter (not shown) is opened for a predetermined exposure period and charges are accumulated in the charge accumulation layer of the photodiode PD of each pixel 1, the pixel blocks 20 are sequentially selected one by one. Then, the same operation is sequentially performed for each row of the pixel block 20. FIG. 3 shows an operation when the pixel block 20 in the n-th row is selected.

  In FIG. 3, t0 indicates the start time of this series of operations. In the example shown in FIG. 3, the voltage of the floating diffusion FD in the n-th row (hereinafter referred to as “FD (n) voltage”) is assumed to be level SIG at time t0. Here, the FD (n) voltage is described on the assumption that signal charges that are not saturated but have a large amount of charge are accumulated in the same amount in the photodiode PD of each pixel 1 during the exposure period.

  In a period t1-t8 (period from time t1 to time t8), the pixel block 20 in the n-th row is selected, the selection pulse φSEL (n) in the n-th row changes to a high level, and the selection transistor in the n-th row. SEL is turned on, and the source of the n-th amplification transistor AMP is connected to the vertical signal line 4.

  A period t2-t3 from the time point t2 after the time point t1 is a reset period for preparing to read out the pixel 1-1 of the pixel block 20 in the n-th row. In a period t2-t3, the reset pulse φRST (n) in the n-th row changes to a high level, and the reset transistor RES is turned on. As a result, the FD (n) voltage rises from time t2, and reaches the reset level RST at time t3. When the reset transistor RES is turned off at time t3, the FD (n) voltage becomes a so-called dark level DARK corresponding to the noise component. Horizontal scanning by φH1 to φH4 is performed in a predetermined period in the period t3-t4, and the dark level of each pixel 1-1 of the pixel block 20 in the n-th row is output to the outside. The transfer pulse φTX1 (n) in the n-th row changes to a high level for a predetermined period from the time point t4, and the transfer transistor TX1 in the pixel block 20 in the n-th row is turned on, whereby the pixels in the pixel block 20 in the n-th row are turned on. The signal charges photoelectrically converted and accumulated by the photodiode PD1 of 1-1 are transferred to the floating diffusion FD in the nth row. As a result, the FD (n) voltage falls from time t4 to a so-called signal level SIG that falls from the dark level DARK by an amount corresponding to the signal charge. Thereafter, horizontal scanning is performed by φH1 to φH4 in a predetermined period of the period t4-t5, and the signal level of each pixel 1-1 of the pixel block 20 in the n-th row is output to the outside. As described above, a correlated double sampling process that takes the difference between the signal level and the dark level is performed outside.

  The same operations as those performed in the period t2-t3, the period t3-t4, and the period t4-t5 for the pixel 1-1 in the pixel block 20 in the n-th row are the pixels in the pixel block 20 in the n-th row. 1-2 is performed in a period t5-t6, a period t6-t7, and a period t7-t8. These corresponding periods have the same length. For example, the reset period t2-t3 related to the pixel 1-1 and the reset period t5-t6 related to the pixel 1-2 have the same length T. In this embodiment, only in the period t2-t3 and the period t5-t6, the φRST (n) in the n-th row is set to the high level, and the reset transistor RES in the n-th row is turned on. ΦRST (n) in the row is set to the low level, and the reset transistor RES in the n-th row is turned off.

  As can be seen from the above description, in the present embodiment, the vertical scanning circuit 2 transfers the transfer transistors TX1, TX2 of the pixel block 20 in the n-th row so that the transfer transistors TX1, TX2 are sequentially turned on at different timings. TX2 is controlled. Further, the vertical scanning circuit 2 resets the reset transistor RES in the n-th row in a predetermined period (period t2-t3 and period t5-t6) before the on-period of each transfer transistor TX1, TX2. RES is controlled. The length of the on period t2-t3 of the reset transistor RES in the n-th row immediately before the on-period of the transfer transistor TX1 that is first turned on among the transfer transistors TX1 and TX2 in the pixel block 20 in the n-th row is n The length T is the same as the length of the on period t5-t6 of the reset transistor RES in the nth row immediately before the on period of the other transfer transistor TX2 in the row pixel block 20. Furthermore, the time between the start time t4 of the on-period of the transfer transistor TX1 of the pixel block 20 in the n-th row and the end time t3 of the on-period t2-t3 of the n-th reset transistor RES immediately before the on-time. The interval (the length of the period t3-t4) is the start time t7 of the on-period of the transfer transistor TX2 of the pixel block 20 in the n-th row and the on-period t5- of the reset transistor RES in the n-th row immediately before the on-period. The time interval from the end time t6 of t6 (the length of the period t6-t7) is the same. Furthermore, the n-th row reset transistor RES is turned off during a period other than the on-period (period t2-t3 and period t5-t6) immediately before the on-period of the transfer transistors TX1 and TX2 of the pixel block 20 in the n-th row. Is maintained. The same applies to the pixel blocks 20 in other rows.

  According to the present embodiment, the length of the reset period of all the rows in the pixel block 20 is the same. As a result, the reset state of the floating diffusion FD is made substantially the same, so that the pixel signal of the pixel 1-1 that is read first in the pixel block 20 and the other pixel 1-2 in the pixel block 20 are read out. Variations between the pixel signals are reduced. Hereinafter, this point will be described in comparison with a comparative example.

  FIG. 4 is a timing chart showing the reading operation of the solid-state imaging device according to the comparative example, and corresponds to FIG. This comparative example corresponds to the prior art. This comparative example is different from the present embodiment in that the period t0-t2 and the period after time t8 are changed to the ON period (reset period) of the reset transistor RES in the n-th row, and the transfer transistor TX1 in the n-th row. In all other periods except for the period t3-t5 before and after the on-time of the n-th and the period t6-t8 before and after the on-time of the transfer transistor TX2 of the n-th row, the n-th row reset transistor RES is turned on. It is only a point made into the period (reset period). Accordingly, the FD (n) voltage in this comparative example is different from the FD (n) voltage in the present embodiment.

  In this comparative example, since the period t0-t2 is changed to the ON period of the reset transistor RES in the n-th row, the reset period for the pixel 1-1 of the pixel block 20 in the n-th row is a period t0-t3. As for the length T ′, the length of the reset period t5-t6 related to the pixel 1-2 of the pixel block 20 in the n-th row is significantly longer than T. The same applies to the rows of other pixel blocks 20. Focusing on the first-selected pixel block 20 in the first row and taking various conditions into consideration, the length T ′ does not fall below 1.5 times the length T.

  In this comparative example, since T ′ >> T, the reset of the pixel 1-1 that is read first is performed more completely than the reset of the other pixels 1-2. For this reason, the reset level RST2 related to the pixel 1-2 of the FD (n) voltage is lower than the reset level RST1 related to the pixel 1-1 of the FD (n) voltage. The dark level DARK1 and the signal level SIG1 related to the pixel 1-1 are determined based on the reset level RST1, and the dark level DARK2 and the signal level SIG2 related to the pixel 1-2 are determined based on the reset level RST2. Therefore, even if W1 = SIG1-DARK1 and W2 = SIG2-DARK2 in FIG. 4 are irradiated with uniform light, the dark level DARK1 and the dark level DARK2 are equal to the difference between the reset level RST1 and the reset level RST2. Are different, and the signal level SIG1 is different from the signal level SIG2.

  The FD voltage is a gate voltage of the amplification transistor AMP of the pixel block 20. If the selection transistor SEL is turned on and the source of the amplification transistor AMP is connected to the vertical signal line 4, a voltage subjected to an amplification action according to the amplification characteristic of the amplification transistor AMP appears on the vertical signal line 4. FIG. 5 is a diagram schematically showing the relationship between the FD voltage and the vertical signal line voltage when the selection transistor SEL is turned on. Reflecting that the amplification transistor AMP does not have an ideal perfect linear characteristic, the relationship between the FD voltage and the vertical signal line voltage is not a perfect linear relationship but has a non-linearity.

  As shown in FIG. 5, the levels DARK1 ', DARK2', SIG1 ', SIG2' of the vertical signal line voltages are obtained corresponding to the aforementioned levels DARK1, DARK2, SIG1, SIG2 of the FD voltage, respectively. From FIG. 5, it can be understood that despite the fact that W1 = W2, W1 '≠ W2' due to the influence of the nonlinearity described above. However, W1 '= SIG1'-DARK1' and W2 '= SIG2'-DARK2'. In the comparative example, due to this, the signal of the pixel 1-1 read first in the pixel block 20 and the signal read from the other pixel 1-2 in the pixel block 20 vary.

  On the other hand, in the present embodiment, as shown in FIG. 3, the length of the reset period for the pixel 1-1 and the length of the reset period for the pixel 1-2 are the same length T. The reset levels for −1 and 1-2 are both the same level RST. Therefore, the dark levels for both pixels 1-1 and 1-2 are both the same level DARK, and the signal levels for both pixels 1-1 and 1-2 are both the same level SIG. For this reason, according to the present embodiment, W1 ′ = W2 ′ corresponding to the fact that W1 = W2 without being affected by the above-described nonlinearity. Therefore, according to the present embodiment, the above-described variation is reduced.

  In order to further reduce the above-described variation, it is most preferable to set the length of the reset period for the pixel 1-1 and the length of the reset period for the pixel 1-2 to the same T as in the present embodiment. However, since the length T ′ does not fall below 1.5 times the length T as described above, in the present invention, the length of the reset period for the pixel 1-1 is set to the length of the reset period for the pixel 1-1. It may be 1.5 times or less. Then, the effect of reducing variation can be obtained to some extent. However, instead of 1.5 times or less, it is more preferably 1.3 times or less, even more preferably 1.2 times or less, and even more preferably 1.1 times or less. Further, such a magnification is preferably 0.8 or more, more preferably 0.9 or more, and even more preferably 1 or more. These points are the same for each embodiment described later.

  In the present embodiment, as described above, the length of the period t3-t4 is the same as the length of the period t6-t7, so that the reset state for the pixel 1-1 and the reset state for the pixel 1-2 are Is closer to the same state. Therefore, also from this point, the above-described variation is further reduced. However, in the present invention, the length of the period t3-t4 and the length of the period t6-t7 are not necessarily the same.

[Second Embodiment]
FIG. 6 is a timing chart showing the read operation of the solid-state imaging device according to the second embodiment of the present invention, and corresponds to FIG.

  The only difference between the solid-state imaging device according to the present embodiment and the solid-state imaging device according to the first embodiment is that the reset pulse φRST output from the vertical scanning circuit 2 is different. In the first embodiment, in the period t0-t2 and the period after the time point t8, φRST (n) is fixed at the low level, and the reset transistor RES in the n-th row is kept off. On the other hand, in the present embodiment, in the period t0-t2 and the period after the time point t8, the n-th row reset transistor RES in the period t2-t8 is turned on / off (that is, the high level and low level of φRST (n)). The reset transistor RES in the nth row is repeatedly turned on and off at the same cycle and duty. Therefore, in the present embodiment, on / off of the reset transistor RES in the n-th row is repeated at a constant cycle and duty over the entire period. The same applies to the reset pulse φRST and the reset transistor RES in the other rows.

  According to the present embodiment, the same advantages as those of the first embodiment can be obtained, and the following advantages can also be obtained.

  In the first embodiment, the reset transistor RES in the n-th row is maintained in the off state over a long period (period t0-t2 and the period after the time point t8), and the floating diffusion FD in the n-th row is reset. Not. Therefore, there is a slight increase in the possibility that a trouble that the charge that has entered the floating diffusion FD in the nth row overflows due to some factor and moves to another place to cause noise, as compared with the comparative example. The same applies to the reset transistors RES in other rows. However, in the present embodiment, the reset transistor RES is repeated with a constant period and duty, so that the reset transistor RES is not kept off for a long period. Therefore, according to the present embodiment, there is an advantage that such a possibility can be reduced.

  In the present embodiment, the reset transistor RES is repeated with a constant period and duty, so that the reset pulse φRST in any row can be made the same. Therefore, according to the present embodiment, there is an advantage that the circuit configuration of the vertical scanning circuit 2 can be simplified.

[Third Embodiment]
FIG. 7 is a timing chart showing the read operation of the solid-state imaging device according to the third embodiment of the present invention, and corresponds to FIG.

  The only difference between the solid-state imaging device according to the present embodiment and the solid-state imaging device according to the first embodiment is that the reset pulse φRST output from the vertical scanning circuit 2 is different. In the first embodiment, in the period t0-t2 and the period after the time point t8, φRST (n) is fixed at the low level, and the reset transistor RES in the n-th row is kept off. On the other hand, in the present embodiment, φRST (n) is fixed at the high level and the reset transistor RES in the n-th row is also set in the period t0-t2 and the period after time t8 except for the period t20-t2. Kept on. In the period t20-t2, the reset transistor RES in the n-th row is turned off. The time point t20 is a time point before the time point t2. The length of the period t20-t2 is set to the same T ″ as the length of the period t3-t5 and the length of the period t6-t8. However, the length of the period t20-t2 is not limited to this. The same applies to the reset pulse φRST and the reset transistor RES in this row.

  As can be seen from the above description, in the present embodiment, the reset transistor RES in the nth row immediately before the on-period of the transfer transistor TX1 that is turned on first among the transfer transistors TX1 and TX2 in the pixel block 20 in the nth row. The period before the on-period t2-t3 is the off-period t20-t2 of the n-th reset transistor RES immediately before the period t2-t3, and the on-period t0-t20 of the n-th reset transistor RES before the period t2-t3. Consists of.

  According to the present embodiment, advantages similar to those of the second embodiment can be obtained. However, in this embodiment, since the reset pulse φRST of each row cannot be made the same, the circuit configuration of the vertical scanning circuit 2 is not as simple as that of the second embodiment.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

  For example, each of the above embodiments is an example in which the present invention is applied to a solid-state imaging device in which a pixel block 20 is formed for every two pixels 1 in which photodiodes PD are sequentially arranged in the column direction. However, the present invention is not limited to this, and, for example, solid-state imaging in which the pixel block 20 is formed for each of a predetermined number (for example, four) of three or more pixels 1 in which photodiodes PD are sequentially arranged in the column direction. It can also be applied to elements.

1,1-1,1-2 pixel 20 pixel block PD, PD1, PD2 photodiode AMP amplifying transistor RES reset transistor (reset switch)
TX, TX1, TX2 Transfer transistor (transfer switch)
SEL selection transistor (selection switch)
FD floating diffusion

Claims (8)

A plurality of photoelectric conversion units;
A charge-to-voltage converter that converts the charge transferred to the voltage provided in common to the plurality of photoelectric converters;
A transfer switch that is provided corresponding to the plurality of photoelectric conversion units and transfers charges from the plurality of photoelectric conversion units to the charge voltage conversion unit;
An amplification transistor that outputs a signal corresponding to the potential of the charge-voltage converter;
A reset switch for resetting the potential of the charge-voltage converter,
The transfer switches provided corresponding to the charge-voltage converters are sequentially turned on at different timings, the reset switch is turned on before the on-period of each transfer switch, and the reset switch that is turned on first is turned on A control unit for setting the length of the period to 1.5 times or less of the length of the ON period of the other reset switch;
A solid-state imaging device comprising:   2. The solid-state imaging device according to claim 1, wherein the length of the on period of the reset switch that is turned on first is equal to or longer than the length of the on period of the other reset switch.   2. The solid-state imaging device according to claim 1, wherein an on period of the reset switch that is turned on first is the same as an on period of the other reset switch.   For any of the transfer switches provided corresponding to the charge-voltage converter, between the start of the on-period of the transfer switch and the end of the on-period of the reset switch immediately before the on-period of the transfer switch 4. The solid-state imaging device according to claim 1, wherein the time intervals are the same.   5. The solid-state imaging device according to claim 1, wherein the reset switch is kept off during a period other than the on-period of the reset switch immediately before the on-period of each transfer switch.   The solid-state imaging device according to any one of claims 1 to 4, wherein the reset switch is repeatedly turned on and off at a constant cycle and duty.   The period before the on-period of the reset switch immediately before the on-period of the first-on transfer switch is the reset immediately before the on-period of the reset switch just before the on-period of the first-on transfer switch. 5. The solid-state imaging device according to claim 1, comprising a switch off period and a previous on period of the reset switch. A plurality of photoelectric conversion units;
A charge-to-voltage converter that converts the charge transferred to the voltage provided in common to the plurality of photoelectric converters;
A transfer switch that is provided corresponding to the plurality of photoelectric conversion units and transfers charges from the plurality of photoelectric conversion units to the charge voltage conversion unit;
An amplification transistor that outputs a signal corresponding to the potential of the charge-voltage converter;
A reset switch for resetting the potential of the charge-voltage converter,
The transfer switches provided corresponding to the charge voltage conversion units are sequentially turned on at different timings, and the reset state of the charge voltage conversion unit of the charge voltage conversion unit before the on period of each transfer switch is the same A control unit for controlling the reset switch,
A solid-state imaging device comprising:

Images