JP2008172069A - Nonvolatile semiconductor storage device and nonvolatile semiconductor storage device manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device, in which the occurrence of a short-circuit between the upper part of a word gate and the upper part of a backup part can be prevented. <P>SOLUTION: The nonvolatile semiconductor storage device comprises: a memory cell transistor 20 that is provided in a first region 31 of a semiconductor substrate 30; first and second pseudo-memory cell transistors 10 provided on a second region 32; and a connection layer 5 for connecting both the pseudo-memory cell transistors 10. The first pseudo-memory cell transistor 10 comprises a third gate 2 formed on an element separation layer 21 of the second region 32; and a fourth gate 3 formed on the side of the third gate 2. The second pseudo-memory cell transistor 10 comprises a fifth gate 2, formed on the element separation layer 21; and a sixth gate 3 formed on the side of the fifth gate 2 to face the fourth gate 3. The connection layer 5 is coupled to the fourth gate 3 and sixth gate 3, and at least its lower part is embedded in a recessed part 41 that is provided in the element isolation layer 21. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the nonvolatile semiconductor memory device.

  As represented by a MONOS structure (Metal-Oxide-Nitride-Oxide structure) nonvolatile memory cell, a nonvolatile memory cell structure in which a control gate is formed on the side wall of a word gate is known. For example, JP 2002-353346 A discloses a cell structure of a flash memory having a twinMONOS structure. FIG. 1 is a cross-sectional view showing a configuration of a memory cell having a twinMONOS structure disclosed in Japanese Patent Laid-Open No. 2002-353346 (see FIG. 10B of Japanese Patent Laid-Open No. 2002-353346). The memory cell 101 includes a source / drain diffusion layer 144, a word gate insulating film 126, a word gate 130, a control gate 132, and an ONO (Oxide Nitride Oxide film) stacked film 131. A sidewall insulating film 142, silicide layers 149 and 150, and an LDD diffusion layer 138.

  The source / drain diffusion layer 144 is formed on the surface of the semiconductor substrate 120. The word gate insulating film 126 is formed on the channel region sandwiched between the source / drain diffusion layers 144. The word gate 130 is formed on the channel region via the word gate insulating film 126. The control gate 132 is formed on both side surfaces of the word gate 130 via the ONO laminated film 131. The ONO stacked film 131 is formed between the word gate electrode 130 and the control gate electrode 132 and between the control gate 132 and the channel region. The sidewall insulating film 142 is formed on both side surfaces of the word gate 130 so as to cover the control gate 132. The silicide layers 149 and 150 are formed on the word gate electrode 130 and the source / drain diffusion layer 144, respectively. The LDD diffusion layer 138 is formed in the channel region immediately below the sidewall insulating film 142.

  The memory cell 101a (101b) is provided on the element isolation region 123 on the extension line of the control gate 132 of the memory cell 101 (in the direction perpendicular to the drawing sheet). Although it has a memory cell structure, it is a pseudo memory cell having no memory function. The control gate 132 of the memory cell 101a is integral with the control gate 132 of the memory cell 101. In order to make contact between the control gate 132 of the memory cell 101 and the upper metal wiring, the control gate 132 of the memory cell 101a is connected to the control gate 132 of the adjacent memory cell 101b by the connection layer 135. As a result, the control gate 132 is connected to the upper metal wiring (backing wiring) via the connection layer 135, the silicide layer 151 and the contact 154 thereabove. The control gate 132 of the memory cell 101 is connected to the backing wiring because of the structural factor that the control gate 132 is formed on the side wall of the word gate 130 and the material factor that polysilicon is used. This is because, since the wiring resistance is high, it is necessary to lower the wiring resistance as a whole by “lining” with a low-resistance metal wiring. Note that the word gate 130 extends in a direction perpendicular to the control gate 132 (a direction parallel to the drawing sheet) (see FIGS. 8.1 and 8.2 of JP-A-2002-353346).

  As related technology, “Embedded Twin MONOS Flash Memories with 4 ns and 15 ns Fast Access Times” (2003 Symposium on VLSI Circuits of Sciences J. Technology). 12-14, 2003 discloses a nonvolatile memory cell having a TwinMONOS structure in which two MONOS structures are integrated. This nonvolatile memory is different from the nonvolatile memory disclosed in JP-A-2002-353346 mainly in that a word gate and a control gate are formed in the same direction (see FIG. 2 of this paper). ). In the present invention, contacts are provided on the diffusion layers on both sides of the nonvolatile memory cell and connected to the upper wiring. Thereby, compared with the non-volatile memory cell of Unexamined-Japanese-Patent No. 2002-353346, high-speed reading is enabled.

JP 2002-353346 A (Climing priority to US Provisional Patent Application serial No. 60 / 278,622) T.A. Ogura, et al. , “Embeded Twin MONOS Flash Memory with 4 ns and 15 ns Fast Access Times”, 2003 Symposium on VLSI Circuits Digest of Technical Journal. 12-14, 2003

  In the nonvolatile memory disclosed in the above paper, when the backing of the control gate is formed as disclosed in JP-A-2002-353346, as the miniaturization further proceeds, the polysilicon upper portion of the word gate and the polysilicon upper portion of the backing portion The distance may be shortened. In that case, due to the influence of the manufacturing yield, the distance becomes too short, and there is a possibility that a short circuit occurs between them. A technique for preventing a short circuit from occurring between the polysilicon upper portion of the word gate and the polysilicon upper portion of the backing portion is desired.

  In addition, in a flash memory embedded microcomputer, as the speed of the microcomputer increases, a high-speed read operation is also required for the flash memory. In the nonvolatile memory disclosed in the above paper, in order to further increase the reading speed, it is advantageous to reduce the resistance by silicidizing the word gate and the diffusion layer. Further, siliciding the control gate is difficult because it causes a short circuit between the control gate and the word gate, but it is effective to reduce the contact resistance by siliciding the backing portion of the control gate. However, when the backing of the control gate is formed as disclosed in JP-A-2002-353346, when the upper portion of the word gate and the backing portion is silicided, the distance between the silicide on the backing portion and the silicide on the upper portion of the word gate. Since the distance is close, the distance becomes too short and a short circuit may occur between the two. Therefore, it is difficult to silicide the backing portion. There is a need for a technique for siliciding the upper portion of the word gate and the backing portion so that no short circuit occurs between them.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in the best mode for carrying out the invention. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of the claims and the best mode for carrying out the invention. However, these numbers and symbols should not be used for interpreting the technical scope of the invention described in the claims.

  The nonvolatile semiconductor memory device of the present invention is provided in the memory cell transistor (20) provided in the first region (31) of the semiconductor substrate (30) and in the second region (32) on the semiconductor substrate (30). A first pseudo memory cell transistor (10), a second pseudo memory cell transistor (10) provided in the second region, a first pseudo memory cell transistor (10), and a second pseudo memory cell transistor (10), And a connection layer (5) for connecting the two. The memory cell transistor (20) includes a first gate (2) formed on the channel region (15) of the first region (31) via the first insulating layer (11), and a first gate (2). A second gate (3) formed on the side surface and the channel region (15) via the second insulating layer (14), and a diffusion layer (16) formed at the end of the channel region (15). . The first pseudo memory cell transistor (10) includes a third gate (2) formed on the element isolation layer (21) in the second region (32), and a third insulating layer on the side surface of the third gate (2). A fourth gate (3) formed through (4) and coupled to the second gate (3). The second pseudo memory cell transistor (10) includes a fifth gate (2) formed on the element isolation layer (21) and a side surface of the fifth gate (2) through the fourth insulating layer (4). And a sixth gate (3) formed to face the four gates (3). The connection layer (5) is coupled to the fourth gate (3) and the sixth gate (3) and has a contact (9) connected to the upper portion thereof. At least the lower part is embedded in a recess (41) provided in the element isolation layer (21).

  In the nonvolatile semiconductor memory device of the present invention, at least a part (lower part) of the connection layer (5, for example, the backing part) is embedded in the concave part (41) provided in the element isolation layer (21). That is, the height of the connection layer (5) can be reduced by the depth of the recess (41). Therefore, when the backing of the control gate as in Japanese Patent Laid-Open No. 2002-353346 is formed in the invention of the conventional paper, the third gate (2, example: word gate) or the fifth gate (2, example: word gate) It is possible to prevent the distance between the upper part of the metal layer and the upper part of the connection layer (5) from becoming too short. Thereby, it is possible to suppress the occurrence of a short circuit between the third gate (2) or the fifth gate (2) and the connection layer (5). The nonvolatile semiconductor memory device of the present invention includes a nonvolatile memory mixed semiconductor device in which a nonvolatile memory is mounted.

  Further, by appropriately selecting the depth of the recess (41), the upper part of the third gate (2, eg: word gate) or the fifth gate (2, eg: word gate) and the upper part of the connection layer (5). Can be designed appropriately. Therefore, even if the upper part of the third gate (2) or the fifth gate (2) and the upper part of the connection layer (5) are silicided, the third gate (2) or the fifth gate (2) and the connection layer (5 ) Can be prevented from occurring.

  According to the present invention, it is possible to suppress the occurrence of a short circuit between the upper portion of the word gate and the upper portion of the backing portion. Further, even if the upper part of the word gate and the upper part of the backing part are silicided, the occurrence of a short circuit between them can be suppressed.

  Embodiments of a nonvolatile semiconductor memory device and a method for manufacturing the nonvolatile semiconductor memory device of the present invention will be described below with reference to the accompanying drawings. FIG. 2 is a schematic top view showing the configuration of the embodiment of the nonvolatile semiconductor memory device of the present invention. However, a part of the configuration is omitted for easy understanding.

  The nonvolatile semiconductor memory device 1 has a memory cell region 31 and a backing region 32. In the memory cell region 31, a plurality of memory cells 20 having a Twin-MONOS type are arranged in a virtual ground array shape. The backing region 32 is disposed between the memory cell regions 31. In the backing region 32, a plurality of pseudo memory cells 10 are arranged in a row.

  The nonvolatile semiconductor memory device 1 includes a plurality of word gates 2 and a plurality of control gates 3. Each of the plurality of word gates 2 extends in the X direction in the memory cell region 31 and the backing region 32. Each of the plurality of control gates 3 extends along both sides of the word gate 2 via an ONO stacked film (oxide-nitride-oxide film) 4 in the memory cell region 31 and the backing region 32. Stretch in the X direction.

  In the memory cell region 31, a plurality of element isolation regions 21 extending in the Y direction are formed to separate the surface regions. The memory cell 20 is sandwiched between element isolation regions 21 and includes a single word gate 2, a control gate 3 provided on both sides of the word gate 2 via an ONO stacked film 31, and a source / drain diffusion layer 16 in the vicinity. is there. For example, it is a region (20) surrounded by a square frame in the figure. A contact 19 connects the diffusion layer 16 to a bit line (not shown).

  In the backing region 32, an element isolation region 21 for separating the surface region is similarly formed. The pseudo memory cell 10 is sandwiched between element isolation regions 21 and includes one word gate 2, a control gate 3 provided on both sides of the word gate 2 via an ONO stacked film 31, and a connection layer 5 connecting adjacent control gates 3. It is an area. For example, it is a region (10) surrounded by a square frame in the figure. The contact 9 connects the connection layer 5 to a backing wiring (not shown).

  The connection layer 5 extends in the Y direction while jumping while connecting adjacent control gates 3. The connection layer 5 is connected to the upper backing wiring (metal wiring) as a backing contact structure for the control gate 3 together with the silicide layer (7) and the contact (9). On the word gate 2, a backing contact structure for the word gate 2 including a silicide layer (6) and a contact (not shown) is formed.

  FIG. 3 is a schematic sectional view showing the configuration of the embodiment of the nonvolatile semiconductor memory device of the present invention. 3A is a cross-sectional view taken along the line A-A ′ of FIG. 2, and FIG. 3B is a cross-sectional view taken along the line B-B ′ of FIG. 2.

  With reference to FIG. 3A, in the memory cell region 31, the diffusion layer 17, the contact 19, and the element isolation region 21 are periodically formed in the X direction on the surface region of the semiconductor substrate 30. In the backing region 32, an element isolation region 21 having a recess 41 is provided in the surface region of the semiconductor substrate 30. In the recess 41, the connection layer 5 and the contact 9 are formed. An upper portion of the semiconductor substrate 30 is covered with an interlayer insulating layer 22.

  3B, in the backing region 32, the word gate 2, the control gate 3, the ONO stacked film 4, the connection layer 5 and the contact 9 are periodically arranged in the Y direction in the recess 41 of the element isolation region 21. Is formed. An upper portion of the semiconductor substrate 30 is covered with an interlayer insulating layer 22.

  FIG. 4 is a cross-sectional view showing a part of the configuration in the embodiment of the nonvolatile semiconductor memory device of the present invention. In this figure, the left side of the alternate long and short dash line indicates the C region of FIG. The right side of the alternate long and short dash line indicates the D region in FIG.

  Referring to the D region, the pseudo memory cell 10 is provided in the recess 41 of the element isolation region 21, and includes the word gate 2, the control gate 3, the ONO stacked film 4, the sidewall insulating film 8, and the silicide layer. 6 is provided.

  The word gate 2 is formed on the bottom of the recess 41. Examples are polysilicon. The control gate 3 is formed on both side surfaces of the word gate 2 via the ONO laminated film 4. Examples are polysilicon. The ONO multilayer film 4 is continuously formed between the word gate 2 and the control gate 3 and between the control gate 3 and the bottom of the recess 41. Examples are a laminated film of silicon oxide, silicon nitride, and silicon oxide. The sidewall insulating film 42 is formed on the side surface of the word gate 2 so as to cover the control gate 3. Examples thereof include a single layer film of silicon oxide and a stacked film of silicon oxide, silicon nitride, and silicon oxide. The silicide layer 6 is formed on the word gate 3. Illustrative is cobalt silicide.

  Control gates 3 of adjacent pseudo memory cells 10 are connected to each other by a connection layer 5. The connection layer 5 is made of the same material as the control gate 3 and is exemplified by polysilicon. A silicide layer 7 is formed on the connection layer 5. Illustrative is cobalt silicide. The control gate 3 is connected to the upper backing wiring via the connection layer 5, the silicide layer 7 and the contact 9.

  Referring to the C region, the surface of the silicide layer 7 above the connection layer 5 in the backing region 32 is substantially equal to or lower than the surface of the silicide layer 17 above the diffusion layer 16 in the memory region 31. . This is because the connection layer 5 is embedded in the recess 41 provided in the element isolation region 21. In order to make the connection between the connection layer 5 and the control gate 3 more reliable, it is more preferable that the pseudo memory cell 10 is also embedded in the recess 41 provided in the element isolation region 21.

  FIG. 5 is a cross-sectional view showing a part of the configuration in the embodiment of the nonvolatile semiconductor memory device of the present invention. In this figure, the left side of the alternate long and short dash line indicates the C region of FIG. The right side of the alternate long and short dash line shows the E-E 'cross section of FIG.

  Referring to the section EE ′, the memory cell 20 includes a diffusion layer 16, a word gate insulating film 11, a word gate 2, a control gate 3, an ONO stacked film 14, a sidewall insulating film 18, and silicide layers 6 and 17. It comprises.

  The diffusion layer 16 functions as a source or drain and is formed in the surface region of the semiconductor substrate 30. The dopant of the diffusion layer 16 is exemplified by As or P. The word gate insulating film 11 is formed on the channel region 15 sandwiched between the diffusion layers 16. Illustrative is silicon oxide. The word gate 2 is formed on the channel region 15 via the word gate insulating film 11. Examples are polysilicon. The control gate 3 is formed on both side surfaces of the word gate 2 via the ONO laminated film 4. Examples are polysilicon. The ONO laminated film 4 is formed between the word gate 2 and the control gate 3 and between the control gate 3 and the channel region 15. Examples are a laminated film of silicon oxide, silicon nitride, and silicon oxide. The sidewall insulating film 18 is formed on both side surfaces of the word gate 2 so as to cover the control gate 3. Examples thereof include a single layer film of silicon oxide and a stacked film of silicon oxide, silicon nitride, and silicon oxide. The silicide layers 6 and 17 are formed above the word gate 2 and the diffusion layer 16, respectively. Illustrative is cobalt silicide. The diffusion layer 16 is connected to the bit line via the silicide layer 17 and the contact 19.

  The pseudo memory cell 10 is on an extension line of the memory cell 20 and basically has the same structure as the memory cell 20. For example, the word gate 2 and the control gate 3 of the pseudo memory cell 10 are on an extension line of the word gate 2 and the control gate 3 of the memory cell 20, respectively, and are integrated. However, it is provided on the element isolation region 23 to make contact between the memory cell 20 and the upper metal wiring (backing wiring) for “lining”. Therefore, the pseudo memory cell 10 does not operate as a memory cell.

  Referring to the C region, the surface of the silicide layer 7 above the connection layer 5 in the backing region 32 is substantially equal to or lower than the surface of the silicide layer 17 above the diffusion layer 16 in the memory region 31. . As a result, the height difference between the silicide layer 6 above the word gate 2 and the silicide layer 7 above the connection layer 5 of the pseudo memory cell 10 is different from the silicide layer 6 above the word gate 2 and the diffusion layer 16 above the memory cell 20. It becomes as large as the height difference with the layer 17 or more. Therefore, it is possible to suppress the occurrence of a short circuit between the word gate 2 and the connection layer 5 of the pseudo memory cell 10.

  Next, the operation of the embodiment of the nonvolatile semiconductor memory device will be described with reference to FIGS. First, an operation of writing information to the memory cell 20 will be described. A positive potential of about 1 V is applied to the word gate 2, a positive potential of about 6 V is applied to the control gate 3 on the writing side (hereinafter referred to as “selection side”), and writing that makes a pair with the control gate 3 is performed. A positive potential of about 3V is applied to the control gate 3 on the non-selected side (hereinafter referred to as “non-selected side”), a positive potential of about 5V is applied to the diffusion layer 16 on the selected side, and about Apply 0V. As a result, hot electrons generated in the channel region are injected into the chamber film of the ONO multilayer film 14 on the selection side. This is called CHE (Channel Hot Electron) injection. Thereby, data is written.

  Next, the erase operation of information written in the memory cell 20 will be described. About 0 V is applied to the word gate 2, a negative potential of about −3 V is applied to the control gate 3 on the selection side, a positive potential of about 2 V is applied to the control gate 3 on the non-selection side, and the diffusion layer 16 on the selection side A positive potential of about 5 V is applied to As a result, a hole-electron pair is generated by the band-to-band tunnel, and the hole or the hole generated by colliding with this hole is accelerated to become a hot hole, which is injected into the nitride film of the ONO multilayer film 14 on the selection side. . As a result, the negative charges accumulated in the nitride film of the ONO multilayer film 14 are canceled and data is erased.

  Next, a read operation of information written in the memory cell 20 will be described. A positive potential of about 2V is applied to the word gate 2, a positive potential of about 2V is applied to the control gate 3 on the selection side, a positive potential of about 3V is applied to the control gate 3 on the non-selection side, and diffusion on the selection side About 0 V is applied to the layer 16 and about 1.5 V is applied to the non-selection side diffusion layer 16. In this state, the threshold value of the memory cell 20 is detected. If negative charges are accumulated in the ONO multilayer film 14 on the selection side, the threshold value increases compared to the case where no negative charges are accumulated. Therefore, by detecting the threshold value, the ONO multilayer film 14 on the selection side is detected. The information written in can be read out. In the memory cell 20 shown in FIG. 5, 2-bit information can be recorded on each side of the word gate 2.

  In each of the above-described operations, the voltage applied to the control gate 3 and the current flow associated therewith are the control gate 3 backing contact structure (control gate 3, connection layer 5 silicide layer 7, contact 9 and metal wiring (backing). Via wiring)). Similarly, the application of a voltage related to the word gate 2 and the accompanying current flow are performed through the above-described backing contact structure for the word gate 2.

  Next, an embodiment of a method for manufacturing a nonvolatile semiconductor memory device of the present invention will be described. 6 to 9 are cross-sectional views showing respective steps in the embodiment of the method for manufacturing the nonvolatile semiconductor memory device of the present invention. In each figure, the left side of the alternate long and short dash line indicates the C region of FIG. The right side of the alternate long and short dash line indicates the D region in FIG.

  Referring to FIG. 6A, element isolation regions 21 are formed at predetermined positions in the surface regions of the memory cell region 31 and the backing region 32 of a p-type silicon semiconductor substrate 30 by a conventional shallow trench isolation (STI) method. Respectively.

  Next, referring to FIG. 6B, a recess 41 having a predetermined width and depth is formed in a region where the pseudo memory cell 10 and the connection layer 5 are formed in the element isolation region 21. The width and depth of the recess 41 will be described later.

  Next, referring to FIG. 6C, the word gate insulating film 11 is formed on the surface of the semiconductor substrate 30 by thermal oxidation. The film thickness of the word gate insulating film 11 is, for example, 10 nm. Thereafter, a word gate polysilicon film 42 is formed by CVD so as to cover the word gate insulating film 11. The word gate polysilicon film 42 becomes the word gate 2 of the memory cell 20 and the pseudo memory cell 10. The film thickness of the word gate polysilicon film 42 is, for example, 200 nm.

  Subsequently, referring to FIG. 7A, the word gate polysilicon film 42 is etched by photolithography and dry etching so that the word gate 2 of the pseudo memory cell 10 and the word gate 2 of the memory cell 20 (illustrated). Not). At that time, the surface of the word gate insulating film 11 is exposed in a portion where the word gate 2 is not present. Thereafter, using the word gate 2 as a mask, the word gate insulating film 11 not covered with the word gate 2 is removed by selective etching. At that time, the surface of the element isolation region 21 is also slightly etched. As a result, the word gate insulating film 11 remains only immediately below the word gate 2 of the memory cell 20. The surface of the semiconductor substrate 30 is exposed in a portion where the word gate 2 is not present, but not in the element isolation region 21.

  Next, referring to FIG. 7B, silicon oxide, silicon nitride, and silicon oxide are stacked in this order so as to cover the surface of the semiconductor substrate 30, the element isolation region 21 (including the recess 41), and the word gate 2. . An oxidation method or a CVD method is used for forming silicon oxide, and a CVD method is used for forming silicon nitride. Thereby, an ONO multilayer film 43 as a charge storage layer is formed. The ONO laminated film 43 also covers the inner surface of the recess 41.

  Thereafter, a control gate polysilicon film 44 is formed by a CVD method so as to cover the ONO laminated film 43. The control gate polysilicon film 44 later becomes the control gate 3. As shown in the drawing, the control gate polysilicon film 44 fills the recess 41. Since the recess 41 has a shape (width and depth) described later, the control gate polysilicon film 44 can be formed substantially flat even on the upper portion of the recess 41. That is, the control gate polysilicon film 44 on the recess 41 is relatively thick, and the other control gate polysilicon films 44 are relatively thin.

  Subsequently, referring to FIG. 7C, the control gate polysilicon film 44 and the ONO laminated film 43 are etched back, respectively, and the control gate polysilicon film other than the side surface of the word gate 2 and the vicinity of the connection layer 5 is etched. 44 and ONO laminated film 43 are removed. Thereby, in the backing region 32, the control gate 3 is formed on the side surface of the word gate 2 of the pseudo memory cell 10 via the ONO laminated film 4, and the connection layer 5 is formed between the control gates 3. On the other hand, in the memory cell region 31, a control gate 3 (not shown) is formed on the side surface of the word gate 2 of the memory cell 20 via the ONO stacked film 4.

  Thereafter, referring to FIG. 8A, although not shown, after LDD (Lightly Doped Drain) is implanted into the memory cell region 31, the silicon oxide film 45 is CVD-coated so as to cover the entire surface of the semiconductor substrate 30. Form by the method. Part of this silicon oxide film 45 later becomes sidewall insulating films 8 and 18.

  Subsequently, referring to FIG. 8B, the silicon oxide film 45 is etched back, and the silicon oxide film 45 other than the side of the word gate 2 (side surface and upper surface of the control gate 3) is removed. Thereby, in the backing region 32, the sidewall insulating film 8 is formed so as to cover the side of the word gate 2 of the pseudo memory cell 10 (the side surface and the upper surface of the control gate 3). On the other hand, in the memory cell region 31, a sidewall insulating film 18 (not shown) is formed so as to cover the side of the word gate 2 of the memory cell 20 (side surface and upper surface of the control gate 3). At this time, the upper part of the word gate 2 and the upper part of the center of the connection layer 5 are exposed.

  In the memory cell region 31, for example, an n-type impurity such as arsenic (As) is implanted into the semiconductor substrate 30 using the word gate 2 and the sidewall insulating film 18 as a mask. As a result, the source / drain diffusion layer 16 is formed in a self-aligned manner in a region excluding the word gate 2 and the region immediately below the sidewall insulating film 18 and the element isolation region 21 on the surface of the semiconductor substrate 30 in the memory cell region 31. Is formed.

  Thereafter, referring to FIG. 8C, a cobalt film is formed on the entire surface of the semiconductor substrate 30 by sputtering, and heat treatment is performed. By this heat treatment, the upper part of the word gate 2 and the surface side of the diffusion layer 16 are silicided in the memory cell region 31 to become silicide layers 6 and 17, respectively. In the backing region 32, the upper portion of the word gate 2 and the surface side of the connection layer 5 are silicided to become silicide layers 6 and 7, respectively. At this time, since the control gate 3 is covered with the sidewall insulating films 8 and 18, it is not silicided. Thereafter, the cobalt film other than the silicide layer is removed by etching.

  Subsequently, referring to FIG. 9A, an interlayer insulating layer 22 is formed so as to cover the entire surface of the semiconductor substrate 30. Subsequently, referring to FIG. 9B, a via hole is formed in a predetermined portion (at least the diffusion layer 16 and the connection layer 5) of the interlayer insulating layer 22. Then, a metal film is formed and polished by a CMP method. As a result, in the memory cell region 31, a contact 19 that connects the diffusion layer 16 and the upper wiring (not shown) via the silicide layer 18 is formed. In the backing region 32, a contact 9 that connects the connection layer 5 and an upper wiring (not shown) through the silicide layer 8 is formed.

  After the manufacturing process, a normal logic process is performed to manufacture a nonvolatile semiconductor memory device.

The width of the recess 41 substantially corresponds to the width of the connection layer 5. Therefore, the minimum value is determined by design from the viewpoint that the resistance of the connection layer 5 does not become too high. For example, it is about the thickness of the polysilicon film 44 for control gate (about the thickness of the connection layer 5).
If the width of the recess 41 is too wide, when the control gate polysilicon film 44 is formed (FIG. 7B), a recess may be formed in a portion corresponding to the recess 41. In this case, when the film is etched back (FIG. 7C), the control gate polysilicon film 44 in the recess 41 is too thin and most of the film is etched, making it impossible to form the connection layer 5 well. . Therefore, when the control gate polysilicon film 44 is formed (FIG. 7B), the maximum width is such that no depression is formed in the portion corresponding to the recess 41. For example, it is about twice the film thickness of the control gate polysilicon film 44.

  If the depth of the recess 41 is small, the occurrence of a short circuit between the silicide layer 7 above the connection layer 5 and the silicide layer 6 above the word gate 2 of the recess 41 can be improved. Since it can improve more, there is no restriction | limiting in particular. However, the maximum value is a depth at which no leakage occurs between the semiconductor substrate 30 below the element isolation region 21 and the connection layer 5.

  In the nonvolatile semiconductor memory device of the present invention, at least a part (lower part) of the connection layer 5 is embedded in the recess 41 provided in the element isolation region 21. In other words, the height of the connection layer 5 can be reduced by the depth of the recess 41 (in the above embodiment, the height of the upper portion of the connection layer is equal to or lower than the surface of the semiconductor substrate 30). ing). Therefore, when a control gate backing as in Japanese Patent Application Laid-Open No. 2002-353346 is formed in the invention of the conventional paper, the distance between the upper portion of the word gate 2 and the upper portion of the connection layer 5 in the backing region becomes too short. This can be suppressed. Thereby, it is possible to suppress occurrence of a short circuit between the word gate 2 and the connection layer 5 in the backing region 32.

  In addition, by appropriately selecting the depth of the recess 41, the distance between the upper portion of the word gate 2 and the upper portion of the connection layer 5 in the backing region 21 can be appropriately designed. That is, a sufficient distance can be taken. Therefore, even if the upper part of the word gate 2 and the upper part of the connection layer 5 are silicided, it is possible to suppress the occurrence of a short circuit between the word gate 2 and the connection layer 5. By siliciding, the resistance related to the connection of the control gate can be lowered, and high-speed operation becomes possible.

  Further, in the step shown in FIG. 7C, the control gate polysilicon film 44 and the ONO laminated film 43 are etched back, and the control gate 3 and the connection layer 5 of the pseudo memory cell 10 are formed in the backing region 32. ing. At this time, according to the conventional technique, in the connection portion Q between the control gate 3 and the connection layer 5 shown in FIG. 2, the control gate polysilicon film 44 and the ONO laminated film 43 are in a state where the corners are rounded as shown by the broken line. Etching phenomenon may occur. Although there is no problem in performance, it is necessary to increase the width of the backing region 32 by that amount in order to improve the yield, which is not preferable in terms of area efficiency.

  However, in the present invention, since the lower part or the whole of the connection layer 5 is buried in the concave portion 41, in the step shown in FIG. 7 (c), the corners of the connection part Q in FIG. Etching phenomenon is difficult to occur. Thereby, the width of the backing region 32 can be made narrower, and the area efficiency can be improved.

FIG. 1 is a cross-sectional view showing a configuration of a memory cell having a twinMONOS structure disclosed in Japanese Patent Laid-Open No. 2002-353346. FIG. 2 is a schematic top view showing the configuration of the embodiment of the nonvolatile semiconductor memory device of the present invention. FIG. 3 is a cross-sectional view showing the configuration of the embodiment of the nonvolatile semiconductor memory device of the present invention. FIG. 4 is a cross-sectional view showing a part of the configuration in the embodiment of the nonvolatile semiconductor memory device of the present invention. FIG. 5 is a cross-sectional view showing a part of the configuration in the embodiment of the nonvolatile semiconductor memory device of the present invention. FIG. 6 is a cross-sectional view showing each step in the embodiment of the method for manufacturing the nonvolatile semiconductor memory device of the present invention. FIG. 7 is a cross-sectional view showing each step in the embodiment of the method for manufacturing the nonvolatile semiconductor memory device of the present invention. FIG. 8 is a cross-sectional view showing each step in the embodiment of the method for manufacturing the nonvolatile semiconductor memory device of the present invention. FIG. 9 is a cross-sectional view showing each step in the embodiment of the method for manufacturing the nonvolatile semiconductor memory device of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Nonvolatile semiconductor memory device 2 Word gate 3 Control gate 4, 14 ONO laminated film 5 Connection layer 6, 7, 17 Silicide layer 8, 18 Side wall insulating film 9, 19 Contact 10 Pseudo memory cell 11 Word gate insulating film 15 Channel Region 16 Diffusion layer 20 Memory cell 21 Element isolation region 22 Interlayer insulating layer 30 Semiconductor substrate 31 Memory cell region 32 Backing region 41 Recess 42 Word gate polysilicon film 44 Control gate polysilicon film 45 Silicon oxide film

Claims (12)

A memory cell transistor provided in a first region of a semiconductor substrate;
A first pseudo memory cell transistor provided in a second region on the semiconductor substrate;
A second pseudo memory cell transistor provided in the second region;
A connection layer connecting the first pseudo memory cell transistor and the second pseudo memory cell transistor;
The memory cell transistor is
A first gate formed on a channel region of the first region via a first insulating layer;
A second gate formed on a side surface of the first gate and on the channel region via a second insulating layer;
A diffusion layer formed at an end of the channel region,
The first pseudo memory cell transistor includes:
A third gate formed on the element isolation layer in the second region;
A fourth gate formed on a side surface of the third gate through a third insulating layer and coupled to the second gate;
The second pseudo memory cell transistor is
A fifth gate formed on the device isolation layer;
A sixth gate formed on a side surface of the fifth gate so as to face the fourth gate through a fourth insulating layer;
The connection layer is
The fourth gate and the sixth gate are coupled with a contact at the top,
A non-volatile semiconductor storage device, wherein at least a lower part is embedded in a recess provided in the element isolation layer. The nonvolatile semiconductor memory device according to claim 1,
The non-volatile semiconductor memory device, wherein lower portions of the fourth gate and the sixth gate are embedded in a recess provided in the element isolation layer. The nonvolatile semiconductor memory device according to claim 1,
A nonvolatile semiconductor memory device, wherein lower portions of the first pseudo memory cell transistor and the second pseudo memory cell transistor are embedded in a recess provided in the element isolation layer. The nonvolatile semiconductor memory device according to any one of claims 1 to 3,
The non-volatile semiconductor memory device, wherein the top surfaces of the third gate, the fifth gate, and the connection layer are silicided. The nonvolatile semiconductor memory device according to claim 1,
A non-volatile semiconductor memory device, wherein the position of the upper surface of the connection layer is equal to or lower than the position of the upper surface of the diffusion layer. The nonvolatile semiconductor memory device according to claim 1,
The depth of the concave portion is equal to or greater than the thickness of the connection layer. The nonvolatile semiconductor memory device according to any one of claims 1 to 6,
The height difference between the upper surface of the third gate and the fifth gate and the upper surface of the connection layer is compared with the height difference between the upper surface of the first gate and the upper surface of the diffusion layer. Equivalent or large nonvolatile semiconductor memory device. (A) forming a recess in the element isolation layer formed in the second region of the semiconductor substrate;
(B) a first gate of a memory cell transistor on a first region of the semiconductor substrate via a first insulating layer, and a third gate and a second pseudo memory cell of a first pseudo memory cell transistor on the element isolation layer; Forming each of the fifth gates of the transistors;
(C) laminating a second insulating film and a gate film so as to cover the first gate, the third gate, and the fifth gate;
(D) Etching back the gate film, the second gate of the memory cell transistor on the first region, the fourth gate of the first pseudo memory cell transistor and the second pseudo on the element isolation layer. Forming a sixth gate of a memory cell transistor and a connection layer for coupling the fourth gate and the sixth gate on the recess, respectively. A method for manufacturing a nonvolatile semiconductor memory device. The method for manufacturing a nonvolatile semiconductor memory device according to claim 8,
The step (a)
(A1) comprising a step of forming the concave portion at a position corresponding to the fourth gate, the sixth gate, and the connection layer in the element isolation layer;
The step (d)
(D1) A method for manufacturing a nonvolatile semiconductor memory device, comprising: forming the fourth gate, the sixth gate, and the connection layer on the concave portion of the element isolation layer. The method for manufacturing a nonvolatile semiconductor memory device according to claim 8,
The step (a)
(A2) including a step of forming the concave portion at a position corresponding to the first pseudo memory cell transistor, the second pseudo memory cell transistor, and the connection layer in the element isolation layer;
The step (b)
(B1) comprising a step of forming the third gate and the fifth gate on the recess,
The step (d)
(D2) A method for manufacturing a nonvolatile semiconductor memory device, comprising: forming the fourth gate, the sixth gate, and the connection layer on the concave portion of the element isolation layer. In the manufacturing method of the non-volatile semiconductor memory device according to any one of claims 8 to 10,
(E) A method for manufacturing a nonvolatile semiconductor memory device, further comprising the step of silicidizing the third gate, the fifth gate, and the upper portion of the connection layer. The method for manufacturing a nonvolatile semiconductor memory device according to any one of claims 8 to 11,
The step (a)
(A3) A method for manufacturing a nonvolatile semiconductor memory device, comprising the step of forming the recess so that the depth of the recess is equal to or greater than the thickness of the connection layer.

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