JPWO2009096083A1 - Floating gate type nonvolatile memory device and manufacturing method thereof - Google Patents

Abstract

The present invention is suitable for incorporation into a logic LSI, prevents interference during writing and erasing, and has a configuration advantageous for data retention. The floating gate nonvolatile memory device of the present invention includes a memory FET having a first gate insulating film, a source region, and a drain region on a semiconductor substrate, and a control gate portion having a second gate insulating film. A floating gate configured to cover and cover the first gate insulating film of the memory FET and the second gate insulating film of the control gate portion is provided. The first gate insulating film is made of a tunnel insulating film, and the second gate insulating film is made of a two-layer structure of a tunnel insulating film and a high dielectric constant insulating film, and the control gate voltage is applied to the substrate of the control gate portion or Apply to wells.

Description

  The present invention relates to a floating gate type nonvolatile memory device having a two-transistor configuration including a memory FET and a control gate portion, and particularly suitable for being mixed with a logic circuit portion in a logic LSI chip, and a method for manufacturing the same.

  A logic LSI in which a logic circuit portion and a memory are mounted in one chip has been developed. In such a logic LSI, a six-transistor SRAM cell is usually used as a memory. However, the SRAM cell has a large cell area, and information is lost when the power is turned off. On the other hand, a normal nonvolatile memory has a complicated process and is not suitable for introduction into a logic LSI.

  Conventionally, a stack type floating gate structure is known as a nonvolatile memory. FIG. 30 is a diagram showing a nonvolatile memory device having a conventional stack structure described in Patent Document 1. In FIG. A gate insulating film made of a thin silicon oxide film and source and drain regions are formed on the silicon substrate, and a floating gate electrode made of a polycrystalline silicon film, an interlayer insulating film and a polycrystalline silicon film are formed on the gate insulating film. Gate electrodes are sequentially stacked. In the illustrated nonvolatile memory device, information is written, held, and erased by accumulating charges in the floating gate electrode or discharging charges from the floating gate electrode. Since it is a structure usually used in a memory chip, it is well known as a process and a device. High density due to 1 transistor structure. However, since the structure is completely different from that of a logic transistor, it is not suitable for an embedded application.

  A non-volatile memory having a layout that realizes a floating gate using two transistors is also known. 31A and 31B are diagrams showing a conventional nonvolatile memory device described in Patent Document 2. FIG. 31A is a pattern layout, and FIG. 31B is a cross-sectional view taken along line XX.

  A memory FET including source and drain regions and a control gate diffusion region are formed in the element region on the surface of the silicon substrate. Floating gates are formed on the channel region between the source and drain regions and on a part of the control gate diffusion region via ultrathin oxide films a and b, respectively. Further, a select transistor in which a select gate is formed via a gate oxide film is provided on the channel region between the drain region and the bit line diffusion region. Further, on the CVD oxide film deposited on the entire surface, a common potential line connected to the source region via the contact hole a, and a bit line diffusion region connected to the contact hole b are connected. Bit lines are formed.

  In such a nonvolatile memory, erasing is performed by setting the control gate diffusion region to a high potential, the drain region to 0 V, and accumulating charges in the floating gate. Writing is performed by setting the control gate diffusion region to 0 V, the drain region to a high potential, and allowing charge to flow out from the floating gate to the drain region.

Since the illustrated nonvolatile memory device uses only the tunnel insulating films (oxide films a and b) for both the memory FET and the control gate, no process change other than the introduction of the tunnel film thickness is required. However, the current density of the memory FET and the control gate is equal, and interference occurs during writing and erasing, which is a disadvantageous configuration for data retention.
Japanese Patent Laid-Open No. 10-223783 JP-A-6-53521

  The present invention solves such problems, and provides a floating gate type memory device having a configuration suitable for incorporation into a logic LSI, preventing interference during writing and erasing, and having a configuration advantageous for data retention. The purpose is that. As a result, a cell structure that realizes a non-volatile memory cell with almost no change in process using a high dielectric constant (High-k) gate insulating film that has been introduced to logic LSIs since the 45 nm generation, its process flow, or its Layout can be provided.

  The floating gate nonvolatile memory device of the present invention includes a memory FET having a first gate insulating film, a source region, and a drain region on a semiconductor substrate, and a control gate portion having a second gate insulating film. A floating gate configured to cover and cover the first gate insulating film of the memory FET and the second gate insulating film of the control gate portion is provided. The first gate insulating film is a tunnel insulating film that performs writing and / or erasing through the insulating film, and the second gate insulating film includes an insulating film made of the same material as the tunnel insulating film, and a high dielectric constant insulating film. A contact for applying a control gate voltage to the substrate or well of the control gate portion is provided.

  According to the method of manufacturing the floating gate nonvolatile memory device of the present invention, a tunnel insulating film for writing and / or erasing through the insulating film is grown on the semiconductor substrate as the first gate insulating film of the memory FET. A first gate electrode is formed thereon, and in the control gate portion, a high dielectric constant insulating film is formed on the insulating film made of the same material as the tunnel insulating film. Thus, the second gate insulating film is formed. A second gate electrode coupled to the first gate electrode is formed on at least the second gate insulating film, and the first and second gate electrodes are configured as floating gates, and the control gate unit substrate or A contact for applying a control gate voltage is provided in the well.

  The present invention can realize a floating gate type memory cell while maintaining a process flow of a logic LSI.

  In addition, by introducing a high-k insulating film, leakage current can be reduced while maintaining the capacitance on the control gate side.

(A) is a figure which shows the 1st example of the floating gate type memory layout for logic LSI embodying this invention, (B) and (C) are each shown by the dotted line in (A). FIG. 6 is a cross-sectional view in the poly gate direction and a cross-sectional view in the source / drain direction of the portion. It is a figure which illustrates the detail of FIG. 1 (B) in parallel with logic FET. It is a figure which illustrates the detail of FIG.1 (C) in parallel with logic FET. It is a figure explaining the deposition of the gate electrode. It is a figure explaining the patterning of a gate electrode. It is a figure explaining the patterning of a tunnel insulating film. It is a figure explaining the deposition of a gate insulating film and a gate electrode. It is a figure explaining the deposition of the gate electrode 3. FIG. It is a figure explaining the patterning of a gate electrode. It is a figure which illustrates the 1st method which formed the control gate part in the n well. It is a figure which illustrates the 2nd method of forming a p-type layer in addition to the 1st method. It is a figure which illustrates the 3rd method by SOI. FIG. 10 is a diagram showing a second example of a floating gate type memory layout for incorporating a logic LSI different from FIG. 1. It is a figure which shows the 3rd example of the floating gate type memory layout for logic LSI incorporation. It is a figure which shows the 4th example of the floating gate type memory layout for logic LSI incorporation. It is a figure explaining the deposition of the gate electrode. It is a figure explaining the patterning of the gate electrode. It is a figure explaining the patterning of a tunnel insulating film. It is a figure explaining the deposition of a gate insulating film (high-k). It is a figure explaining the deposition of the gate electrode 3. FIG. It is a figure explaining formation of the gate electrodes 3c and 3a. FIG. 22 is a diagram showing the same steps as shown in FIG. It is a figure explaining creation of a drain and a source, a sidewall spacer, and silicide. It is a figure explaining the etching of the poly gate of a logic FET. It is a figure which shows formation of the gate electrode of logic FET. FIG. 25 is a diagram showing the same steps that differ only in the viewing direction. It is a figure explaining the etching of the poly gate of a logic FET and a control gate part. It is a figure which shows formation of the gate electrode of a logic FET and a control gate part. FIG. 28 is a diagram showing the same steps that differ only in the viewing direction. 1 is a diagram showing a nonvolatile memory device having a conventional stack structure described in Patent Document 1. FIG. It is a figure which shows the conventional non-volatile memory device described in patent document 2. FIG.

  Hereinafter, the present invention will be described based on examples. FIG. 1A is a diagram showing a first example of a floating gate type memory layout for embedding a logic LSI embodying the present invention. FIGS. 1B and 1C are respectively dotted lines in FIG. FIG. 6 is a cross-sectional view in the poly gate direction and a cross-sectional view in the source / drain direction of the portion indicated by. 2 and 3 are diagrams illustrating the details of FIGS. 1B and 1C, respectively, along with logic FETs to show that they can be implemented with the same process flow. Note that the poly (polycrystalline silicon) gate shown in FIG. 1A corresponds to the gate electrode 3a in FIG.

  In the layout shown in FIG. 1A, a bit line is formed of metal 2 and connected to a source and a drain through a via, metal 1 and a contact. The word line is connected to the active region by a metal 1 at a contact portion indicated by a cross in a rectangle in the drawing. As described above, the illustrated layout is a high-speed type in which all nodes are accessed by metal. The floating gate type memory cell shown in FIGS. 2 and 3 can be realized while maintaining the process flow with the logic FET. As will be clear from the details of the manufacturing method described later with reference to FIGS. 4 to 9, the gate insulating film 2C, the gate electrode 2c, and the gate electrode 3c of the logic FET are respectively the gate insulating film 2A of the memory cell. The gate electrode 2a and the gate electrode 3a can be formed at the same height position by the same process.

  The gate insulating film 2C of the logic FET realizes high capacity and high performance by a high dielectric constant (High-k) insulating film. A memory cell (floating gate type memory cell) mixed with a logic FET in one chip is configured by using two transistors including a memory FET and a control gate portion. The gate insulating film 1B (tunnel insulating film) of the memory FET is written and erased by hot carriers or FN current. The gate insulating film of the control gate portion is composed of two layers of a gate insulating film 1A (an insulating film made of the same material as the tunnel insulating film) and a gate insulating film 2A (High-k insulating film). The present invention combines a tunnel insulating film, which is indispensable for realizing a nonvolatile memory, and a high-k insulating film already possessed by a logic process, thereby suppressing leakage current while maintaining the capacity (high capacity / (Low leakage). Thereby, stable writing and erasing and long-term storage of electric charge are possible. Although it is theoretically possible to realize a control gate structure with only a high-k insulating film, the tunnel insulating film introduced with the method cannot be used with this method, and the high-k insulating film is used for logic MOS and memory. Separate optimization is required. The two-layer structure of the present invention can realize a nonvolatile memory with a minimum process change from a normal logic CMOS process (using a high-k insulating film).

  In the present specification, the “tunnel insulating film” is used as a term meaning an insulating film in which writing and / or erasing is performed through this film during device operation. Even in the high-k oxide film, tunneling is naturally applied to a high voltage, but it is designed not to occur in device operation. Also, a laminated structure that would not be so can be made by the present invention. Such a tunnel insulating film is usually formed of a silicon oxide film of about 90 A (or a film in which nitrogen is slightly added). It is necessary to secure a certain film thickness in order to guarantee the data retention characteristics for 10 years. On the other hand, when the holding period may be short, the film thickness may be reduced and it is not necessary to be restricted by this film thickness.

  The memory FET can be formed of either NMOS or PMOS, but is preferably formed of NMOS in the same manner as a normal nonvolatile memory in view of carrier mobility and write characteristics. When formed of NMOS, the substrate under the channel is p-type, the source S and drain D are n +, and the gate electrode 1 (polysilicon) is n +.

  On the control gate portion, the electrode material of the gate electrode 2a on the gate insulating film 2A (high-k insulating film) can be formed of metal or polysilicon. When the gate electrode 2a is a metal, the impurity type of the gate electrode 3a (polysilicon) does not matter. Here, depositing a thin metal gate directly on a high-k gate insulating film and depositing a thick polysilicon on the thin metal gate makes it possible to use an arbitrary work function of the metal gate and ease the processing of the polysilicon. It is taken into consideration. The example configuration thus uses the gate electrode 3a (polysilicon) to connect the memory FET and the control gate.

  The gate electrode 1, the gate electrode 2a, and the gate electrode 3a are integrally connected to form a floating gate. This makes it possible to realize a non-volatile memory without significantly changing the process from the manufacturing process of the logic LSI. Specifically, it is possible to prevent the gate and the polysilicon from overlapping each other like an ordinary floating gate type. By making the polysilicon substantially one stage, the polysilicon gate etching does not need to be changed from the logic LSI process. In addition, the metal of the gate electrode 2a is data retention among the two types of metal gates used in logic FETs (in high-k / metal gate systems, metals with different work functions are usually used for NMOS and PMOS). Any one that optimizes the characteristics can be selected. Note that it is not necessary for the device operation to overlap a part of the gate insulating film 2A and the gate electrode 2a on the gate electrode 1, but the cell layout is more compact in terms of the design rule if it is laid out in an overlapping manner. It becomes possible to summarize.

  Next, an example of a method for manufacturing the floating gate type memory cell of FIGS. 2 and 3 will be described with reference to FIGS. In FIG. 4, after an active region isolated by an element isolation region is formed on a semiconductor substrate, a tunnel insulating film such as a silicon oxide film is grown, and a gate electrode 1 (polysilicon) is deposited thereon ( accumulate. As is well known, the active region is “a portion where the silicon substrate is exposed” or “outside the element isolation region formed of a thick oxide film”.

  In FIG. 5, the gate electrode 1 is patterned on the memory FET.

  In FIG. 6, the insulating film is patterned and the insulating film of the logic FET is removed. As a result, the insulating film of the memory cell is manufactured separately from the gate insulating film of the logic FET (this insulating film can also be used for a high voltage device).

  In FIG. 7, a gate insulating film (high-k) is deposited, and then a gate electrode (metal or polysilicon) is deposited thereon.

  In FIG. 8, after the gate insulating film (high-k) 2C and gate electrode 2c of the logic FET and the gate insulating film (high-k) 2A and gate electrode 2a of the control gate portion are etched, the gate electrode 3 (polysilicon) is etched. ).

  In FIG. 9, the gate electrodes 3c and 3a are formed by patterning the gate electrodes of the logic FET and the memory cell, respectively. In the memory cell, the gate electrode 1, the gate electrode 2a, and the gate electrode 3a are integrally connected to form a floating gate, and in the logic FET, the gate electrode 2c and the gate electrode 3c are integrally connected. As a result, a non-volatile memory structure of a normal floating gate that can be formed by a control gate-floating gate-channel connection using a poly gate (or metal) as the floating gate can be configured.

  Thereafter, a drain and a source (see FIG. 3) are created by implantation (ion implantation). At this time, the edges of the gate electrodes 3a and 3c are aligned with the edges of the drain and source. Further, in accordance with a normal technique, as shown in FIG. 2, a side wall spacer for LDD (Lightly Doped Drain) fabrication is formed on the gate side surface, and the upper portion of the gate electrode 3a is covered with silicide.

  The operation condition of the memory cell having the layout illustrated in FIG. 1 is a NOR type. Basically, it operates according to existing floating gate type memory cells. The control gate voltage is applied to the substrate or the well through the metal wiring (the word line in FIG. 1A) from the contact of the control gate portion through the active region, as will be described later with reference to FIGS. .

  At the time of writing, if a high voltage is applied to the contact (control gate) and drain electrode of the control gate portion and electrons flowing between the source and the drain are made high energy, the electrons break through the gate insulating film 1B (tunnel insulating film). Jump into the floating gate.

  To erase data, a negative (−) high voltage is applied to the control gate, a positive (+) high voltage is applied to the source electrode, and 0 V is applied to the drain electrode, and electrons are extracted from all floating gates. Normally, the drain is often floated in NOR-type erasure, but in the illustrated layout, the drain is shared by a plurality of cells, so that the drain is set to 0V.

  When reading data, a constant voltage is applied to the drain electrode and a voltage about twice the drain voltage is applied to the control gate to determine whether a large amount of current flows. The read voltage can be arbitrarily determined based on the balance between speed and reliability. For example, a power supply voltage is applied to the gate and a low voltage is applied to the drain to prevent electrons from being injected into the floating gate due to a high voltage. In the illustrated layout, the same potential as the drain is applied to the source of the cell sharing the drain in order to eliminate the current flowing in the direction other than the reading side. When there are no electrons in the floating gate, many electrons move between the source and drain (channel), and current flows. On the other hand, when electrons are present in the floating gate, the number of electrons flowing through the channel is reduced.

  A method of forming the control gate portion when the memory FET is formed of NMOS will be described with reference to FIGS. 10 to 12 which are the same cross-sectional views in the polygate direction as FIG. FIG. 10 is a diagram illustrating a first method in which the control gate portion is formed in the n-well. When a positive voltage is applied as the control gate voltage, a positive voltage is applied to the entire n-well, and when a negative voltage is applied, a negative voltage is applied to the p source / drain.

  FIG. 11 is a diagram illustrating a second method for forming a p-type layer in addition to the first method. When a positive voltage is applied as the control gate voltage, a positive voltage is applied to the entire n-well, and when a negative voltage is applied, a negative voltage is applied to the p-type layer. Although the resistance of the word line is lower than that of the first method, an additional process (lithography and implantation) for forming the p-type layer is required.

  FIG. 12 is a diagram illustrating a third method using SOI (Silicon On Insulator). Each node is formed on an oxide film as an insulating film. The control gate portion can be easily insulated from other nodes, and the impurity type of the control gate portion can be arbitrarily set. A gate voltage is applied to the substrate of the control gate part insulated by the oxide film.

  FIG. 13 is a diagram showing a second example of a floating gate type memory layout for incorporating a logic LSI different from FIG. By using the active region as a word line, the area can be reduced. For example, the area shown in FIG. 1 is 15.5 × 9 = 139.5 (arbitrary unit: effective only for comparison). In the layout shown in FIG. 13, the area is 14 × 9 = 126.

  FIG. 14 is a diagram showing a third example of a floating gate type memory layout for incorporating a logic LSI. The active word line similar to the second example is used. The redundancy of the word line is increased on the assumption that the metal is reduced. Area: 11 × 9 = 99.

  FIG. 15 is a diagram showing a fourth example of a floating gate type memory layout for incorporating a logic LSI. The NAND is constructed assuming the overlap of the active region polysilicon gate and the reduction of the metal rule. The control gate CG / floating gate FG is not self-aligned. The area is 21 × 4 = 84.

  In order to form a NAND cell array, in addition to connecting the memory cell portions in series, it is necessary to take a word line perpendicular to the series direction of the cells. As shown in FIG. 15, the memory FETs are arranged in series in the vertical direction. The word line is formed by making a rectangular active contact from the metal 1 drawn in the horizontal direction. Each rectangle functions as a control gate for the memory cells on both sides. In order to optimize the layout density, rectangular control gate active regions are alternately arranged beside the memory FET.

The area of the control gate is defined by self-alignment at the intersection of active and gate in FIGS. 1, 13, and 14, but this cannot be done in the NAND type of FIG. As a result of the misalignment of the left and right with respect to the active of the photolithography of the gate, the area of the control gate changes. As a result, the write, erase, and read characteristics change depending on which side of the active rectangle is used as the control gate. (This deviation can be corrected by causing a similar misalignment in the reference cell of the sense amplifier during reading.)
The layout of this specification is basically drawn with lambda rules. Lambda rules were mainly used as standard rules before the 1um rule generation, and each rule is expressed using a virtual parameter lambda. For example, in the 1um rule, lambda (λ) is 0.5, the gate width is 2λ = 1 um, the active width is 3λ = 1.5 um, and so on, and each rule is expressed as a multiple of lambda. On the other hand, the current state-of-the-art technology rules are different from the standard rules, and are designed to reduce everything that can be shortened. This tendency is particularly strong in the memory cell array, and there are many special cases that can be satisfied only in the array. In the NAND example of FIG. 15, the memory cell array is efficiently arranged by assuming reduction of the above two rules.

  Next, an example of manufacturing the floating gate type nonvolatile memory device of the present invention by a replacement gate process will be described. Recently, a process called “Replacement gate” (conventional CMOS creation method is called gate-first, sometimes referred to as gate-last) is known. A typical process flow for a replacement gate is to first manufacture a normal MOS transistor using a dummy gate electrode (usually polysilicon. If the insulating film is also removed, a dummy insulating film, usually an oxide film). A source / drain is also formed, and an interlayer insulating film before contact is deposited. The CMP (Chemical Mechanical Polishing: a well-known process for removing and flattening the nano-order level difference from the interlayer insulating film and wiring) is polished so that the head of the polygate is exposed, and the polygate (and the insulating film if necessary) is removed. Etch. Arbitrary gates (and insulating films) are deposited here, and subsequent processes such as contact are advanced. The advantage of this process is that the gate electrode and, if necessary, the insulating film can be processed after high-temperature annealing for activation after source / drain implantation. You can avoid doing it.

  The floating gate nonvolatile memory device of the present invention can also be manufactured using such a replacement gate process. This Replacement gate process can be applied to any one or more of the logic FET, memory FET, and control gate unit shown in FIG. 2, and in this application, only the gate electrode or In addition, it can be used for insulating films.

  FIGS. 16 to 26 are diagrams showing a method for manufacturing a floating gate type memory layout for incorporation into a logic LSI, in which the Replacement gate process is applied to the manufacture of only a logic FET. The manufacturing process of FIGS. 16 to 18 can be the same process as FIGS. 4 to 6 described above. In FIG. 16, after forming an active region separated into element isolation regions on a semiconductor substrate, a tunnel insulating film such as a silicon oxide film is grown, and a gate electrode 1 (polysilicon) is deposited thereon. . In FIG. 17, the gate electrode 1 is patterned on the memory FET. In FIG. 18, the insulating film is patterned to cut out the insulating film of the logic FET.

  In FIG. 19, the gate insulating film (high-k) is deposited. However, the gate electrode on the gate insulating film is not deposited as shown in FIG.

  In FIG. 20, after the gate insulating film (high-k) 2C of the logic FET and the gate insulating film (high-k) 2A of the control gate portion are etched, the gate electrode 3 (polysilicon) is deposited.

  In FIG. 21, the gate electrodes 3c and 3a are formed by patterning the gate electrodes of the logic FET and the memory cell, respectively. In the memory cell, the gate electrode 1 and the gate electrode 3a are integrally connected to form a floating gate. FIG. 22 shows the same steps that differ from FIG. 21 only in the viewing direction.

  Next, as shown in FIG. 23, a drain and a source are formed by implantation (ion implantation). At this time, the edges of the gate electrodes 3a and 3c are aligned with the edges of the drain and source. Further, a sidewall spacer for LDD (Lightly Doped Drain) fabrication is formed on the gate side surface, and the upper surfaces of the drain and source are covered with silicide above the gate electrodes 3a and 3c. This silicide is simultaneously silicided and reduced in resistance by a normal process. The silicide above the gate electrodes 3a and 3c is created according to the exemplified manufacturing process, but is not necessarily required and will be removed in a later process.

  Next, as shown in FIG. 24, an interlayer insulating film is deposited, and CMP processing is performed to cut off silicide above the gate electrodes 3a and 3c. Then, the poly gate (gate electrode 3c) of the logic FET is etched.

  FIG. 25 is a diagram illustrating the formation of the gate electrode of the logic FET, and FIG. 26 is a diagram illustrating the same steps in which only the viewing direction is different. As shown in the figure, after depositing metal a and then metal b, CMP processing is performed. Metal a is a metal for adjusting the work function, and metal b is a metal such as Al for reducing the resistivity. Thereby, the gate electrode of the logic FET is formed. In this case, the structure is different from that shown in FIG. 2 in that the gate electrode 3a is directly above the tunnel insulating film / high-k insulating film in the control gate portion. By using a poly gate (or metal) as the floating gate, a normal floating gate nonvolatile memory structure that can be formed by connection of control gate-floating gate-channel can be configured.

  FIG. 27 to FIG. 29 are diagrams showing a floating gate type memory layout manufacturing method for incorporating a logic LSI in which a replacement gate process is applied not only to the above-described logic FET but also to a control gate portion. Since the steps from FIGS. 16 to 23 can be the same, the description thereof is omitted. As shown in FIG. 23, sidewall spacers for LDD (Lightly Doped Drain) fabrication are formed on the gate side surface, and the upper surfaces of the drain and source and the gate electrodes 3a and 3c are covered with silicide. As shown in FIG. 3, the interlayer insulating film is deposited and subjected to CMP to cut off the silicide above the gate electrodes 3a and 3c. Then, not only the logic FET but also the poly gate (gate electrodes 3c, 3a) of the control gate portion is etched.

  FIG. 28 is a diagram illustrating the formation of the logic FET and the gate electrode of the control gate portion, and FIG. 29 is a diagram illustrating the same steps in which only the viewing direction is different. As shown in the figure, after depositing metal a and then metal b, CMP processing is performed. As a result, the logic FET and the gate electrode of the control gate portion are formed.

  Although only a few embodiments have been described in detail in the present disclosure by way of example only, many embodiments may be used without departing substantially from the novel teachings and advantages of the present invention. Modifications are possible.

Claims (15)

A memory FET having a first gate insulating film, a source region, and a drain region on a semiconductor substrate, and a control gate portion having a second gate insulating film, the first gate insulation of the memory FET In a floating gate type nonvolatile memory device provided with a floating gate connecting and covering the film and the second gate insulating film of the control gate portion,
The first gate insulating film is formed of a tunnel insulating film that performs writing or erasing through the insulating film,
The second gate insulating film has a two-layer structure of an insulating film made of the same material as the tunnel insulating film and a high dielectric constant insulating film,
A floating gate type nonvolatile memory device comprising applying a control gate voltage to a substrate or a well of the control gate portion. A first gate electrode formed on the first gate insulating film of the memory FET and a second gate electrode coupled to the first gate electrode on at least the second gate insulating film of the control gate portion The floating gate nonvolatile memory device according to claim 1, wherein the first and second gate electrodes are configured as the floating gate. A logic LSI is configured by incorporating a logic FET in one chip, and the logic FET includes a gate insulating film and a gate electrode realized by the same process flow as the high dielectric constant insulating film and the second gate electrode. The floating gate type non-volatile memory device according to claim 1. 2. The floating gate nonvolatile memory device according to claim 1, wherein the memory FET is formed of NMOS, the substrate under the channel is p-type, and the source S and drain D are n +. 2. The floating gate type nonvolatile memory device according to claim 1, wherein the first gate electrode is made of polysilicon and the second gate electrode is made of polysilicon. A third gate electrode coupled to the second gate electrode is provided between the second gate insulating film and the second gate electrode of the control gate portion, the first gate electrode being polysilicon, 2. The floating gate type nonvolatile memory device according to claim 1, wherein the gate electrode is made of polysilicon, and the third gate electrode is made of metal or polysilicon. The floating gate nonvolatile memory device according to claim 1, wherein the control gate portion is formed in a well provided in a semiconductor substrate, and a control gate voltage is applied to the well. The control gate portion is formed in an n-type or p-type well provided on the semiconductor substrate, a p-type or n-type layer is formed under the first gate insulating film, and a control gate voltage is applied to the layer. The floating gate type nonvolatile memory device according to claim 1. 2. The floating gate nonvolatile memory according to claim 1, wherein an insulating film is provided under the control gate portion so as to insulate the control gate portion from other nodes, and a control gate voltage is applied to a semiconductor substrate separated by the insulating film. Memory device. 2. The contact according to claim 1, wherein a contact for applying a control gate voltage to a substrate or well of the control gate portion is provided, a word line is connected to the contact, and a bit line is connected to the source region and the drain region. Floating gate type non-volatile memory device. The floating gate nonvolatile memory device according to claim 1, wherein a word line is connected through an active region, and a bit line is connected to the source region and the drain region. 2. The floating gate type nonvolatile memory device according to claim 1, wherein, in addition to connecting the memory FETs in series, a NAND is formed by taking a word line perpendicular to the series direction of the memory FETs. 3. A memory FET having a first gate insulating film, a source region, and a drain region on a semiconductor substrate, and a control gate portion having a second gate insulating film, the first gate insulation of the memory FET In a method of manufacturing a floating gate type nonvolatile memory device provided with a floating gate connected to cover a film and the second gate insulating film of the control gate portion,
A tunnel insulating film for writing or erasing through the insulating film is grown as a first gate insulating film of the memory FET on the semiconductor substrate, and a first gate electrode is formed thereon,
In the control gate portion, a high dielectric constant insulating film is formed on an insulating film made of the same material as the tunnel insulating film, and a second gate insulating film is constituted by the two insulating films.
Forming a second gate electrode coupled to the first gate electrode on at least the second gate insulating film, and configuring the first and second gate electrodes as the floating gate;
A method of manufacturing a floating gate type nonvolatile memory device comprising applying a control gate voltage to a substrate or well of the control gate portion. 14. The method of manufacturing a floating gate type nonvolatile memory device according to claim 13, wherein the source region and the drain region are formed by ion implantation. Etching is applied to one or both of the first and second gate electrodes, or in addition to the underlying insulating film by applying a replacement gate process, and the source region and the drain region are ionized. 14. The method of manufacturing a floating gate type nonvolatile memory device according to claim 13, wherein after the formation by plantation, the etched gate electrode or an insulating film in addition thereto is formed again.

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