JP2007165552A - Non-volatile semiconductor storage device, and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately delete information stored in a memory cell while achieving miniaturization and high integration of non-volatile semiconductor storage devices. <P>SOLUTION: The non-volatile semiconductor storage device includes a substrate which has a first semiconductor layer 11, a first insulating layer 12 provided on the first semiconductor layer 11, and a second semiconductor layer 13 provided on the first insulating layer 12; a plurality of memory cell rows which are composed by connecting a plurality of memory cells in series while each memory cell row is extended in a first direction, and in which each of a plurality of the memory cells is composed by laminating a tunnel insulating film 14, an electric-charge accumulation layer 15, a gate insulating film 16, and a control gate electrode 17 in turn on the second semiconductor layer 13; and a conductive layer 22 provided in the first insulating layer 12 and the second semiconductor layer 13 on the first semiconductor layer 11, so as to electrically connect between the first/second semiconductor layers 11, 13. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof, and more particularly to a NAND flash memory.

  In recent years, with the rapid expansion of the market of portable audio devices such as recording media including digital cameras and mobile phones, the demand for NAND flash memories used for these has been rapidly expanding. Currently, in order to meet the demands for miniaturization, weight reduction, and high functionality of these devices, there is an increasing demand for miniaturization, high integration, low power supply voltage, and improved reliability of NAND flash memory. ing.

  This NAND-type flash memory is configured by connecting a plurality of MOS transistors including a stacked structure of floating gate electrodes and control gate electrodes in series, and is an array structure suitable for high integration.

  In such a NAND flash memory, the limit of miniaturization in the conventional structure has been recognized. For this reason, introduction of new materials and new structures is being studied. Among them, a device structure using an SOI (Silicon On Insulator) substrate is considered as one of the promising new structures (Patent Document 1).

However, all of the data erasing methods of the NAND flash memory (hereinafter referred to as SOI-NAND flash memory) using the SOI substrate disclosed so far have a drawback that is difficult to solve. That is, there is no established erase method as an erase method for SOI-NAND flash memory.
JP 2000-174241 A

  The present invention provides a nonvolatile semiconductor memory device that can be miniaturized and highly integrated, and that can accurately erase information stored in a memory cell, and a method of manufacturing the same.

  A nonvolatile semiconductor memory device according to one aspect of the present invention is provided on a first semiconductor layer, a first insulating layer provided on the first semiconductor layer, and the first insulating layer. A substrate having a second semiconductor layer, each extending in a first direction and having a plurality of memory cells connected in series, wherein each of the plurality of memory cells includes the second semiconductor layer; A plurality of memory cell columns configured by sequentially stacking a tunnel insulating film, a charge storage layer, a gate insulating film, and a control gate electrode; and the first insulating layer and the second layer on the first semiconductor layer. And a conductive layer that is provided in the semiconductor layer and electrically connects the first semiconductor layer and the second semiconductor layer.

  According to one aspect of the present invention, a method of manufacturing a nonvolatile semiconductor memory device includes a plurality of substrates corresponding to a plurality of memory cells on a substrate in which a first semiconductor layer, a first insulating layer, and a second semiconductor layer are stacked. A step of sequentially forming a tunnel insulating film and a plurality of charge storage layers; and etching the second semiconductor layer and a part of the first insulating layer formed between the plurality of charge storage layers, Forming an opening exposing the upper surface of the first semiconductor layer in the second semiconductor layer and the first insulating layer; and the first semiconductor layer and the second semiconductor layer in the opening. And a step of forming a plurality of gate insulating films and a plurality of control gate electrodes in order on the plurality of charge storage layers.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device that can be miniaturized and highly integrated, and that can accurately erase information stored in a memory cell, and a method of manufacturing the same.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
FIG. 1 is a circuit diagram of an SOI-NAND flash memory according to the first embodiment of the present invention. One unit as a data erasing unit is connected in series to a plurality of memory cells MC connected in series, a select transistor ST1 connected in series to one end (source side), and the other end (drain side). And the selection transistor ST2.

  A word line WL is connected to the control gate of the memory cell transistor as the memory cell MC. A selection gate line SGS is connected to the gate of the selection transistor ST1. A source line SL is connected to the source of the selection transistor ST1. A selection gate line SGD is connected to the gate of the selection transistor ST2. A bit line BL is connected to the drain of the selection transistor ST2.

  The selection gate lines SGS, SGD are provided for controlling on / off of the selection transistors ST1, ST2. The selection transistors ST1 and ST2 function as gates for supplying a predetermined potential to the memory cells MC in the unit at the time of data writing and reading.

  A plurality of units are arranged so as to be commonly connected to the word lines to form a block. In the present embodiment, for simplification, a case where three memory cells MC are included in one unit is shown as an example. Actually, one unit is configured to include, for example, 16 memory cells MC.

  FIG. 2 is a plan view showing the configuration of the SOI-NAND flash memory shown in FIG. 3 is a cross-sectional view of the SOI-NAND flash memory taken along line III-III shown in FIG. FIG. 4 is a cross-sectional view of the SOI-NAND flash memory taken along line IV-IV shown in FIG. FIG. 5 is a sectional view of the SOI-NAND flash memory taken along line VV shown in FIG.

  The flash memory is provided on the SOI substrate. The SOI substrate includes a semiconductor layer 11, a buried insulating layer (BOX (Buried Oxide) insulating layer) 12 provided on the semiconductor layer 11, and a semiconductor layer 13 provided on the BOX insulating layer 12. ing. The semiconductor layer 13 is used as an active layer.

As the semiconductor layer 11, for example, the silicon layer 11 is used. As the BOX insulating layer 12, for example, a SiO ₂ layer is used. As the semiconductor layer 13, for example, an SOI layer 13 made of a silicon layer is used.

  The SOI substrate has a memory cell region, which is a region where the memory cell MC is formed, and a selection transistor region, which is a region where the selection transistors ST1, ST2 are formed. The memory cell MC group formed in the memory cell region is referred to as a memory cell portion, and the selection transistor group formed in the selection transistor region is referred to as a selection transistor portion.

The SOI layer 13 in the memory cell region is provided with an n ⁻ type semiconductor region 13-1 into which a low concentration n type impurity (for example, P) is introduced. The SOI layer 13 in the selection transistor region is provided with p ⁻ type semiconductor regions 13-2 and 13-3 into which a low concentration p type impurity (for example, B) is introduced. The p ⁻ type semiconductor regions 13-2 and 13-3 function as channel regions of the select transistors ST1 and ST2.

The memory cell MC is configured as follows. On the n ⁻ type semiconductor region 13-1, a plurality of floating gate electrodes (charge storage layers) 15 corresponding to the plurality of memory cells MC are provided in an island shape via the tunnel insulating film 14. The plurality of floating gate electrodes 15 are provided so as to be arranged along the X direction and the Y direction. As the tunnel insulating film 14, for example, SiO ₂ is used. For example, polysilicon is used as the floating gate electrode 15.

  A control gate electrode 17 is provided on the floating gate electrode 15 via a gate insulating film 16 so as to extend in the X direction. For example, an ONO film is used as the gate insulating film 16. For example, polysilicon is used as the control gate electrode 17.

The selection transistor ST1 is configured as follows. A gate electrode 19 is provided on the p ⁻ type semiconductor region 13-2 via a gate insulating film 18 so as to extend in the X direction. The gate electrode 19 includes a gate electrode 19A and a gate electrode 19B that are electrically connected. The gate electrode 19A is provided in an island shape corresponding to each selection transistor. The gate electrode 19B is provided on the gate electrode 19A so as to extend in the X direction.

In the p ⁻ type semiconductor region 13-2, an n type diffusion region 13-4 as a drain of the selection transistor ST1 is provided. Thus, the select transistor ST1 including the gate electrode 19, the gate insulating film 18, and the n-type diffusion region 13-4 is configured.

The p ⁻ type semiconductor region 13-3 is provided with a selection transistor ST2 including an n type diffusion region 13-5 as a source. Each memory cell MC and select transistors ST1, ST2 are insulated by an element isolation region 25. Further, the periphery of each memory cell MC and select transistors ST1, ST2 is covered with an interlayer insulating layer 26.

  Here, as shown in FIG. 3, in the SOI-NAND flash memory of this embodiment, there is no diffusion layer in the cell region of the SOI layer 13. That is, memory cell transistors having no diffusion layer as a source region and a drain region are connected in series to constitute a unit.

  It has been confirmed by simulation that the memory cell transistor having no diffusion layer operates as a transistor. FIG. 6 is a diagram showing a transistor used in this simulation. For simplicity, the control gate electrode is not considered.

The gate voltages of the cells marked VFG are changed, and the gate voltages of the other cells are fixed at 2.5V. The drain voltage Vd in FIG. 6 is set to 0.5V. Further, the potential Vsub of the SOI layer 13 (specifically, the n ⁻ type semiconductor region 13-1) is controlled.

  FIG. 7 shows the drain current Id when the potential Vsub of the SOI layer 13 is changed when the SOI layer 13 having a thickness of 10 nm is used. FIG. 8 shows the drain current Id when the potential Vsub of the SOI layer 13 is changed when the SOI layer 13 having a thickness of 50 nm is used. In both FIG. 7 and FIG. 8, the voltage VFG is set to 0V.

  In order to ensure transistor operation, the transistor must exhibit off characteristics. It can be seen that when the SOI layer 13 is thick, a large off-current flows regardless of how the potential Vsub is changed. On the other hand, when the SOI layer 13 is thin, the drain current Id can be reduced by appropriately controlling the potential Vsub. This is because the SOI layer can be almost depleted by making the SOI layer 13 thinner.

  Therefore, transistor operation can be performed by reducing the thickness of the SOI layer appropriately. FIG. 9 shows the drain current Id when Vsub = −1.17 V and the voltage VFG is changed. The film thickness of the SOI layer 13 is 10 nm. As shown in FIG. 9, the transistor formed in the SOI layer 13 has clear on-off characteristics. That is, it can be seen that the transistor operates.

  From the above, in the SOI-NAND flash memory shown in FIG. 3, if the thickness of the SOI layer 13 is appropriately reduced, the transistor operation is performed even though there is no diffusion layer in the cell region of the SOI layer 13. Therefore, device operation as a NAND flash memory is possible.

  By the way, as shown in FIG. 4, a plurality of conductive layers are connected between the plurality of memory cell columns connected in series so that the SOI layer 13 and the silicon layer 11 are physically and electrically connected. 22 is provided. The conductive layer 22 is provided in the SOI layer 13 and the BOX insulating layer 12, and the bottom surface is in contact with the silicon layer 11.

  The upper surface of the conductive layer 22 is set higher than the upper surface of the BOX insulating layer 12 and lower than the upper surface of the SOI layer 13. This is because the side surface of the conductive layer 22 is in contact with the SOI layer 13 and the conductive layer 22 is not in contact with the floating gate electrode 15. By preventing the conductive layer 22 from contacting the floating gate electrode 15, the potential of the conductive layer 22 is not transmitted to the floating gate electrode 15. Thereby, even when the conductive layer 22 is provided, malfunction of the flash memory can be prevented.

  The length of the conductive layer 22 in the Y direction is between the n-type diffusion region 13-4 and the n-type diffusion region 13-4 and does not contact the n-type diffusion regions 13-4 and 13-4 ( Must not overlap). This is because if such overlapping regions exist, the voltage applied to the n-type diffusion regions 13-4 and 13-4 is transmitted to the memory cell portion, which may cause malfunction.

  A data erasing operation of the SOI-NAND flash memory configured as described above will be described.

  First, a potential Vera (for example, 20 V) is supplied to the silicon layer 11. Then, 20 V is supplied to the SOI layer 13 through the conductive layer 22. Further, the word line WL of the selected block is set to 0V. Thereby, in all the memory cells MC in the selected block, electrons are extracted from the floating gate electrode 15 and the threshold value is lowered to the negative side. In this way, it is possible to erase data from the memory cell MC from the silicon layer 11 below the BOX insulating layer 12.

  For the non-selected block, the word line WL and the selection gate lines SGD and SGS are made floating. These are pulled up to near the potential Vera by capacitive coupling with the SOI layer 13, and the potential difference between the floating gate electrode 15 and the SOI layer 13 is reduced. Therefore, electrons are not extracted from the floating gate electrode 15.

  As described above, the SOI-NAND flash memory according to the present embodiment can accurately erase data in the memory cell MC. Further, the potential Vera can be supplied to the SOI layer 13 through the silicon layer 11.

  Next, a method for manufacturing an SOI-NAND flash memory will be described with reference to the drawings. First, a method for manufacturing a memory cell portion in which the memory cell MC is formed will be described. The drawings referred to in the description of the manufacturing method are sectional views along the X direction (corresponding to the IV-IV line in FIG. 2) and the Y direction (corresponding to the III-III line in FIG. 2) in FIG. It is.

First, as shown in FIG. 10, an SOI substrate including a silicon layer 11, a BOX insulating layer 12, and an SOI layer 13 is prepared. Next, a low concentration n-type impurity (for example, P) is introduced into the memory cell region of the SOI layer 13 to form an n ⁻ -type semiconductor region 13-1 (not shown). Further, p ⁻ type semiconductor regions 13-2 and 13-3 (not shown) are formed by introducing a low-concentration p type impurity (for example, B) into the select transistor region of the SOI layer 13.

  Next, a tunnel insulating film 14 and a floating gate electrode 15 are sequentially deposited on the SOI layer 13. Next, a resist layer (not shown) is formed on the floating gate electrode 15 using lithography.

  Next, as shown in FIGS. 11 and 12, the floating gate electrode 15 and the tunnel insulating film 14 are etched into a desired shape by using, for example, RIE (Reactive Ion Etching) method using the resist layer as a mask. Further, as shown in FIGS. 13 and 14, the SOI layer 13 is etched using, for example, the RIE method. Thereafter, the resist layer is removed.

  Next, as shown in FIGS. 15 and 16, the insulating layer 20 is deposited on the entire surface of the device (including the floating gate electrode 15 and the BOX insulating layer 12). As this insulating layer 20, for example, TEOS (Tetra-Ethyl-Ortho-Silicate), SiN or the like is used. Then, while leaving the insulating layer 20 only in the selection transistor region, the memory cell region is etched by lithography and RIE. The insulating layer 20 has a function of protecting the selection transistor region when the conductive layer 22 described later is formed.

  Next, as shown in FIGS. 17 and 18, sidewall insulating films 21 made of, for example, SiN are formed on the side surfaces of the SOI layer 13, the tunnel insulating film 14, and the floating gate electrode 15. Next, as shown in FIGS. 19 and 20, the BOX insulating layer 12 is etched so that the upper surface of the silicon layer 11 is exposed by using, for example, the RIE method using the sidewall insulating film 21 as a mask. Thereby, an opening is formed in the SOI layer 13 and the BOX insulating layer 12 between the memory cell columns. Thereafter, the sidewall insulating film 21 is removed.

  Next, as shown in FIGS. 21 and 22, a conductive layer 22 is deposited on the entire surface of the device (including in the opening of the SOI layer 13 and on the floating gate electrode 15). As the conductive layer 22, a material having a high etching selection ratio with the material of the floating gate electrode 15 is used. The conductive layer 22 may be a metal.

  Next, as shown in FIGS. 23 and 24, the upper surface of the conductive layer 22 is planarized using, for example, a CMP (Chemical Mechanical Polishing) method. Next, as shown in FIGS. 25 and 26, the conductive layer 22 is etched using, for example, RIE so that the position of the upper surface is higher than the upper surface of the BOX insulating layer 12 and lower than the upper surface of the SOI layer 13. . That is, the conductive layer 22 is formed so as to be in contact with the SOI layer 13 and not in contact with the floating gate electrode 15. Then, the insulating layer 20 is etched using, for example, the RIE method.

Next, as shown in FIGS. 27 and 28, the insulating films 16 and 16A are formed by a method such as oxidation or SiO ₂ deposition. Specifically, the insulating film 16 is formed on at least the floating gate electrode 15 and the side surface, and functions as the gate insulating film 16. The insulating film 16 </ b> A is formed on the conductive layer 22. The insulating film 16A has a function of protecting the conductive layer 22 from subsequent processes.

  Next, as shown in FIGS. 29 and 30, an insulating layer 25 is deposited on the entire surface of the device. Then, the insulating layer 25 is etched using, for example, RIE so that the position of the upper surface is higher than the upper surface of the tunnel insulating film 14 and lower than the upper surface of the floating gate electrode 15. Thereby, the element isolation region 25 is formed. As the element isolation region 25, for example, TEOS or SiN is used.

  Next, as shown in FIGS. 31 and 32, the control gate electrode 17 is formed by depositing polysilicon on the element isolation region 25 and the insulating film 16. Next, as shown in FIG. 33, the tunnel insulating film 14, the floating gate electrode 15, the insulating film 16, and the control gate electrode 17 are selectively etched using lithography and RIE. Thereby, a plurality of memory cells MC having a predetermined gate width are formed.

Next, as shown in FIGS. 34 and 35, an insulating film 23 is formed by a method such as oxidation or deposition of SiO ₂ . In this way, the memory cell portion of the SOI-NAND flash memory of this embodiment is formed.

  On the other hand, the select transistors ST1, ST2 are formed as follows. The manufacturing process up to FIG. 14 is the same as that of the memory cell portion. 36 to 44 are cross-sectional views in the X direction of FIG. 2 (corresponding to the VV line shown in FIG. 2).

  As shown in FIG. 36, the insulating layer 20 is formed on the BOX insulating layer 12 and the gate electrode 19 by the process of FIG. Note that the tunnel insulating film 14 of the memory cell MC corresponds to the gate insulating film 18 of the select transistors ST1, ST2. The floating gate electrode 15 of the memory cell MC corresponds to the gate electrode 19A of the select transistors ST1, ST2.

  Next, as shown in FIG. 37, the conductive layer 22 is formed on the insulating layer 20 by the step of depositing the conductive layer 22 (step of FIG. 21). As shown in FIG. 38, the conductive layer 22 on the insulating layer 20 is etched by the etching process of the conductive layer 22 (process of FIG. 25), and the insulating layer 20 is further etched.

  Next, as shown in FIG. 39, the step of forming the insulating films 16 and 16A (step of FIG. 27) causes the gate electrode 19A and the side surfaces of the gate electrode 19A, the gate insulating film 18 and the SOI layer 13 to be formed. Then, the insulating film 16 is formed.

  Next, as shown in FIG. 40, the element isolation region 25 is formed by the process of FIG. Next, as shown in FIG. 41, the gate electrode 19B is formed on the element isolation region 25 and the insulating film 16 by the step of forming the control gate electrode 17 (step of FIG. 31).

  The select transistors ST1 and ST2 perform normal transistor operations without performing write and erase operations. For this reason, the gate electrode 19B is electrically connected to the gate electrode 19A. That is, as shown in FIG. 42, a plurality of openings that expose the upper surface of the gate electrode 19B are formed, and the contact layer 24 is formed by embedding a conductive layer in these openings. In this way, select transistors ST1 and ST2 are formed.

  As described in detail above, the SOI-NAND flash memory of this embodiment includes the conductive layer 22 that electrically connects the silicon layer 11 and the SOI layer 13. As a result, the potential applied to the silicon layer 11 under the BOX insulating layer 12 is transmitted to the SOI layer 13, so that data can be erased from the silicon layer 11.

  Further, the upper surface of the conductive layer 22 is set lower than the upper surface of the SOI layer 13. Furthermore, the conductive layer 22 does not have a region overlapping the n-type diffusion regions 13-4 and 13-5. Therefore, malfunction of the flash memory due to the provision of the conductive layer 22 can be prevented.

  In addition, since there is no diffusion layer as a source and a drain in the memory cell portion, it is strong against a short channel effect. Similarly, since there is no diffusion layer, erroneous writing of data due to bonding can be suppressed.

  In the conventional structure that does not use the SOI substrate, the channel impurity concentration increases with miniaturization, so that the channel capacity increases. As a result, since it becomes difficult to control the potential of the substrate, it becomes difficult to control the write characteristics. However, if an SOI substrate is used as in this embodiment, such a problem does not occur.

  Note that the SOI-NAND flash memory only needs to include at least one conductive layer 22. Even in such a configuration, the potential of the silicon layer 11 can be supplied to the SOI layer 13.

(Second Embodiment)
The second embodiment shows another method for manufacturing an SOI-NAND flash memory. A method for manufacturing an SOI-NAND flash memory according to the second embodiment will be described below with reference to the drawings. Note that the manufacturing steps up to FIG. 16 are the same as those in the first embodiment.

As shown in FIGS. 43 and 44, the cell region is insulated on the floating gate electrode 15 and on the side surfaces of the floating gate electrode 15, the tunnel insulating film 14 and the SOI layer 13 by a method such as oxidation or SiO ₂ deposition. A film 16 is formed.

  Next, as shown in FIGS. 45 and 46, a sidewall insulating film 21 made of, for example, SiN is formed on the side surface of the insulating film 16. However, when the insulating film 16 and the BOX insulating layer 12 are formed of a material that can provide an etching selectivity, this step (the step of forming the sidewall insulating film 21) is not necessarily required.

  Next, as shown in FIGS. 47 and 48, the BOX insulating layer 12 is etched so that the upper surface of the silicon layer 11 is exposed by using, for example, the RIE method using the sidewall insulating film 21 as a mask. Thereafter, the sidewall insulating film 21 is removed.

  Next, as shown in FIGS. 49 and 50, a polysilicon layer 22 doped with impurities at a high concentration is deposited on the entire surface of the device (including the inside of the opening of the SOI layer 13 and the insulating film 16). The conductivity type of the impurity is not particularly limited, and may be n-type or p-type. Next, as shown in FIGS. 51 and 52, the upper surface of the polysilicon layer 22 is planarized using, for example, a CMP method.

  Next, as shown in FIGS. 53 and 54, the polysilicon layer 22 is etched using, for example, the RIE method so that the position of the upper surface is higher than the upper surface of the BOX insulating layer 12 and lower than the upper surface of the SOI layer 13. To do. Further, the insulating layer 20 is etched using, for example, the RIE method. At this time, the insulating film 16 remains on the floating gate electrode 15 without being removed.

Next, as shown in FIGS. 55 and 56, insulating films 16 and 16A are formed by a method such as oxidation or deposition of SiO ₂ . Specifically, the insulating film 16 is thickened and the insulating film 16A is formed on the upper surface of the polysilicon layer 22. In the step shown in FIG. 54, the insulating film 16 does not exist on the floating gate electrode 15 in the selection transistor region. Therefore, in the process of FIG. 55, the film thickness of the insulating film 16 in the select transistor region is thinner than the insulating film 16 in the memory cell region. The insulating film 16 formed on the top and side surfaces of the floating gate electrode 15 functions as the gate insulating film 16.

  Next, as shown in FIGS. 57 and 58, an insulating layer 25 is deposited on the entire surface of the device (including on the insulating films 16 and 16A). Then, the insulating layer 25 is etched using, for example, RIE so that the position of the upper surface is higher than the upper surface of the tunnel insulating film 14 and lower than the upper surface of the floating gate electrode 15. Thereby, the element isolation region 25 is formed.

  Next, as shown in FIGS. 59 and 60, a control gate electrode 17 is formed by depositing a polysilicon layer on the element isolation region 25 and the insulating film 16. Subsequent steps are the same as those in the first embodiment.

  The SOI-NAND flash memory shown in the second embodiment is different from the first embodiment in that an insulating layer 16 is provided between the polysilicon layer 22 and the SOI layer 13. . The insulating film 16 formed on the side surface of the SOI layer 13 is very thin. Actually, the film thickness of the insulating film 16 formed on the side surface of the SOI layer 13 is about half of the film thickness of the final gate insulating film 16 formed by the process of FIG. Therefore, the SOI layer 13 and the conductive layer 22 are capacitively coupled. Thereby, the potential of the SOI layer 13 can be controlled via the silicon layer 11.

  In the present embodiment, polysilicon can be used as the material of the conductive layer 22. As a result, the manufacturing cost can be reduced. Other effects are the same as those of the first embodiment.

(Third embodiment)
The third embodiment shows another method for manufacturing an SOI-NAND flash memory. A method for manufacturing an SOI-NAND flash memory according to the third embodiment will be described below with reference to the drawings. The manufacturing steps up to FIG. 47 are the same as those in the second embodiment. Further, FIGS. 61 to 71 referred to in this manufacturing method are cross-sectional views along the X direction of FIG.

  As shown in FIG. 61, the insulating layer 30 is deposited on the entire surface of the device (including the inside of the opening of the SOI layer 13 and the insulating film 16). As the insulating layer 30, for example, TEOS is used. Next, as shown in FIG. 62, the upper surface of the insulating layer 30 is planarized using, for example, a CMP method.

  Next, as shown in FIG. 63, the insulating layer 30 is etched using, for example, the RIE method so that the position of the upper surface is higher than the upper surface of the BOX insulating layer 12 and lower than the upper surface of the SOI layer 13.

  Next, as shown in FIG. 64, a sidewall insulating film 21 made of, for example, SiN is formed on the side surface of the insulating film 16 on the insulating layer 30. Next, as shown in FIG. 65, the insulating layer 30 is etched so as to expose the upper surface of the silicon layer 11 by using, for example, the RIE method using the sidewall insulating film 21 as a mask. Further, as shown in FIG. 66, the insulating layer 30 remaining in the step of FIG. 65 is etched using, for example, the RIE method.

  Next, as shown in FIG. 67, the insulating film 16 below the bottom surface of the sidewall insulating film 21 is removed. Thereafter, as shown in FIG. 68, the sidewall insulating film 21 is removed.

  Next, as shown in FIG. 69, a polysilicon layer 22 into which impurities are introduced at a high concentration is deposited on the entire surface of the device (including the inside of the opening of the SOI layer 13 and the insulating film 16). Next, as shown in FIG. 70, the upper surface of the polysilicon layer 22 is planarized using, for example, a CMP method.

  Next, as shown in FIG. 71, the polysilicon layer 22 is etched using, for example, the RIE method so that the position of the upper surface is higher than the upper surface of the BOX insulating layer 12 and lower than the upper surface of the SOI layer 13. The subsequent manufacturing process is the same as in the second embodiment.

  As described above in detail, according to the present embodiment, the polysilicon layer 22 in contact with the SOI layer 13 can be formed. Other effects are the same as those of the first embodiment.

  The present invention is not limited to the above-described embodiment, and can be embodied by modifying the components without departing from the scope of the invention. In addition, various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the embodiments, or constituent elements of different embodiments may be appropriately combined.

1 is a circuit diagram of an SOI-NAND flash memory according to a first embodiment of the present invention. FIG. 2 is a plan view showing a configuration of the SOI-NAND flash memory shown in FIG. 1. FIG. 3 is a cross-sectional view of an SOI-NAND flash memory taken along line III-III shown in FIG. 2. FIG. 4 is a cross-sectional view of an SOI-NAND flash memory taken along line IV-IV shown in FIG. 2. FIG. 3 is a cross-sectional view of an SOI-NAND flash memory taken along line VV shown in FIG. 2. FIG. 6 is a cross-sectional view of a memory cell transistor that does not have a diffusion layer. The figure which shows the drain current Id when changing the electric potential Vsub of the SOI layer 13 at the time of using the SOI layer 13 with a film thickness of 10 nm. The figure which shows the drain current Id when changing the electric potential Vsub of the SOI layer 13 at the time of using the SOI layer 13 with a film thickness of 50 nm. The figure which shows the drain current Id when setting to Vsub = -1.17V and changing the voltage VFG. Sectional drawing along the X direction which shows the manufacturing process of the memory cell part which concerns on the 1st Embodiment of this invention. FIG. 11 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 10. FIG. 11 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 10. FIG. 12 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 11. FIG. 13 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 12. FIG. 14 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 13. FIG. 15 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 14. FIG. 16 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 15. FIG. 17 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 16. FIG. 18 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 17. FIG. 19 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 18. FIG. 20 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 19. FIG. 21 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 20. FIG. 22 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 21. FIG. 23 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 22. FIG. 24 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 23. FIG. 25 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 24. FIG. 26 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 25. FIG. 27 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 26. FIG. 28 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 27. FIG. 29 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 28. FIG. 30 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 29. FIG. 31 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 30. FIG. 33 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 32. FIG. 34 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 33. FIG. 34 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 33. Sectional drawing along the X direction which shows the manufacturing process of the selection transistor part which concerns on the 1st Embodiment of this invention. FIG. 37 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 36. FIG. 38 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 37. FIG. 39 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 38. FIG. 40 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 39. FIG. 41 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 40. FIG. 42 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 41. Sectional drawing along the X direction which shows the manufacturing process of the memory cell part which concerns on the 2nd Embodiment of this invention. Sectional drawing along the Y direction which shows the manufacturing process of the memory cell part which concerns on the 2nd Embodiment of this invention. FIG. 44 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 43. FIG. 45 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 44. FIG. 46 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 45. FIG. 47 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 46. FIG. 48 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 47. FIG. 49 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 48. FIG. 50 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 49. FIG. 51 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 50. FIG. 52 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 51. FIG. 53 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 52. FIG. 54 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 53. FIG. 55 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 54. FIG. 56 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 55. FIG. 57 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 56. FIG. 58 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 57; FIG. 59 is a cross-sectional view along the Y direction showing the manufacturing process of the memory cell portion following FIG. 58. Sectional drawing along the X direction which shows the manufacturing process of the memory cell part which concerns on the 3rd Embodiment of this invention. FIG. 62 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 61. FIG. 63 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 62. FIG. 64 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 63. FIG. 65 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 64. FIG. 66 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 65. FIG. 67 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 66; FIG. 68 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 67; FIG. 69 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 68. FIG. 70 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 69. FIG. 71 is a cross-sectional view along the X direction showing the manufacturing process of the memory cell portion following FIG. 70.

Explanation of symbols

WL ... word line, BL ... bit line, SL ... source line, SGS, SGD ... selection gate line, ST1, ST2 ... selection transistor, 11 ... semiconductor layer, 12 ... BOX insulating layer, 13 ... SOI layer, 13-1 ... n ⁻ type semiconductor regions 13, 13-2, 13-3... p ⁻ type semiconductor regions, 13-4, 13-5, n-type diffusion regions, 14 ... tunnel insulating film, 15. Film 17, Control gate electrode 18, Gate insulating film 19, Gate electrode 20, Insulating layer, 21 Side wall insulating film 22, Conductive layer 23, Insulating film 24, Contact layer , 26 ... interlayer insulating layer, 30 ... insulating layer.

Claims (11)

A substrate having a first semiconductor layer, a first insulating layer provided on the first semiconductor layer, and a second semiconductor layer provided on the first insulating layer;
Each of the plurality of memory cells extends in the first direction and is connected in series, and each of the plurality of memory cells includes a tunnel insulating film, a charge storage layer, a gate on the second semiconductor layer. A plurality of memory cell columns configured by sequentially laminating an insulating film and a control gate electrode; and
A conductive layer provided in the first insulating layer and the second semiconductor layer on the first semiconductor layer and electrically connecting the first semiconductor layer and the second semiconductor layer; A non-volatile semiconductor memory device comprising:   The nonvolatile semiconductor memory device according to claim 1, wherein the conductive layer is provided between the plurality of memory cell columns.   The nonvolatile semiconductor memory device according to claim 1, wherein an upper surface of the conductive layer is lower than an upper surface of the second semiconductor layer.   4. The nonvolatile semiconductor memory device according to claim 1, wherein an erase potential is supplied to the second semiconductor layer via the first semiconductor layer when data is erased. 5.   5. The nonvolatile semiconductor memory device according to claim 1, wherein the conductive layer includes a plurality of conductive layer portions respectively provided between the plurality of memory cell columns.   The semiconductor device further comprises first and second selection transistors provided in the second semiconductor layer on both sides in the first direction of the memory cell column and connected in series to the memory cell column. Item 6. The nonvolatile semiconductor memory device according to any one of Items 1 to 5. The first and second selection transistors include first and second diffusion regions provided in the second semiconductor layer and supplied with a potential,
7. The conductive layer according to claim 1, wherein the conductive layer is provided between the first diffusion region and the second diffusion region, and does not contact the first and second diffusion regions. A non-volatile semiconductor memory device according to claim 1.   The nonvolatile semiconductor memory device according to claim 7, wherein the conductive layer extends in the first direction. Sequentially forming a plurality of tunnel insulating films and a plurality of charge storage layers corresponding to a plurality of memory cells on a substrate in which the first semiconductor layer, the first insulating layer, and the second semiconductor layer are stacked;
A part of the second semiconductor layer and the first insulating layer formed between the plurality of charge storage layers is etched, and the second semiconductor layer and the first insulating layer are etched in the first semiconductor layer. Forming an opening exposing an upper surface of the semiconductor layer of 1;
Forming a conductive layer in the opening for electrically connecting the first semiconductor layer and the second semiconductor layer;
And a step of sequentially forming a plurality of gate insulating films and a plurality of control gate electrodes on the plurality of charge storage layers.   The method for manufacturing a nonvolatile semiconductor memory device according to claim 9, wherein an upper surface of the conductive layer is lower than an upper surface of the second semiconductor layer. The step of forming the opening includes
Etching the second semiconductor layer using the charge storage layer as a mask;
Forming a sidewall insulating film on side surfaces of the charge storage layer, the tunnel insulating film, and the second semiconductor layer;
The method for manufacturing a nonvolatile semiconductor memory device according to claim 9, further comprising: etching the first insulating layer using the sidewall insulating film as a mask.

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