JP2008166477A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2008166477A
JP2008166477A JP2006354126A JP2006354126A JP2008166477A JP 2008166477 A JP2008166477 A JP 2008166477A JP 2006354126 A JP2006354126 A JP 2006354126A JP 2006354126 A JP2006354126 A JP 2006354126A JP 2008166477 A JP2008166477 A JP 2008166477A
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semiconductor chip
fillet
circuit board
circuit
stress
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Masakuni Shibamoto
正訓 柴本
Masahiro Yamaguchi
昌浩 山口
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Micron Memory Japan Ltd
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Elpida Memory Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a package structure capable of preventing a deterioration in a device characteristic. <P>SOLUTION: The semiconductor device related to this invention comprises a circuit board 1, a first semiconductor chip 10 mounted on the circuit board 1, a second semiconductor chip 20 mounted on the first semiconductor chip 10, and a sealing resin 50 for sealing the first semiconductor chip 10 and the second semiconductor chip 20. A circuit surface 11 of the first semiconductor chip 10 is positioned on the side opposite to the side of the circuit board 1. The semiconductor device further comprises a fillet 30 for covering the side surface 22 for overlapping the circuit surface 11 of the first semiconductor chip 10 out of the side surface of the second semiconductor chip 20. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関する。特に、本発明は、パッケージ内に複数の半導体チップが搭載された半導体装置に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device in which a plurality of semiconductor chips are mounted in a package.

近年、携帯機器等で用いられる半導体装置の高速化、高集積化と共に、小型化が進んでいる。半導体装置の小型化を実現するために、例えば、内部に複数の半導体チップが搭載されるＭＣＰ（Multi Chip Package）が採用されている。   2. Description of the Related Art In recent years, semiconductor devices used in portable devices and the like have been miniaturized along with higher speed and higher integration. In order to reduce the size of a semiconductor device, for example, an MCP (Multi Chip Package) in which a plurality of semiconductor chips are mounted is employed.

図１は、典型的なＭＣＰの構造を示す断面図である。回路基板１０１上に下部半導体チップ１１０が搭載されている。回路基板１０１と下部半導体チップ１１０は、接着剤１０５を介して接着されている。更に、下部半導体チップ１１０上に上部半導体チップ１２０が搭載されている。下部半導体チップ１１０と上部半導体チップ１２０は、接着剤１１５を介して接着されている。下部半導体チップ１１０は、金線１４１を通して回路基板１０１に電気的に接続されており、上部半導体チップ１２０は、金線１４２を通して回路基板１０１又は下部半導体チップ１１０に電気的に接続されている。更に、全体が封止樹脂１５０で封止されている。また、回路基板１０１の下面にはんだボール１６０が形成されている。   FIG. 1 is a cross-sectional view showing the structure of a typical MCP. A lower semiconductor chip 110 is mounted on the circuit board 101. The circuit board 101 and the lower semiconductor chip 110 are bonded via an adhesive 105. Further, the upper semiconductor chip 120 is mounted on the lower semiconductor chip 110. The lower semiconductor chip 110 and the upper semiconductor chip 120 are bonded via an adhesive 115. The lower semiconductor chip 110 is electrically connected to the circuit board 101 through the gold wire 141, and the upper semiconductor chip 120 is electrically connected to the circuit board 101 or the lower semiconductor chip 110 through the gold wire 142. Further, the whole is sealed with a sealing resin 150. A solder ball 160 is formed on the lower surface of the circuit board 101.

ＭＣＰに関連する従来技術として、次のものが知られている。   The following are known as conventional techniques related to MCP.

特許文献１に記載されたＭＣＰによれば、上部半導体チップが、“フェイスダウン”で下部半導体チップ上に搭載されている。すなわち、上部半導体チップの上面（回路面）が、下部半導体チップに対向する。その場合、上部半導体チップの下面の角部に応力が集中し、結果として、パッケージクラックや特性劣化が発生する。その応力集中を緩和するために、当該従来技術によれば、上部半導体チップの下面の角部が研磨される。あるいは、上部半導体チップの“全ての側面”が樹脂層によって覆われる。つまり、下部半導体チップは関係なく、フェイスダウン状態の上部半導体チップの角部への応力集中を緩和するために、工夫がなされている。   According to the MCP described in Patent Document 1, the upper semiconductor chip is mounted on the lower semiconductor chip “face down”. That is, the upper surface (circuit surface) of the upper semiconductor chip faces the lower semiconductor chip. In this case, stress concentrates on the corners on the lower surface of the upper semiconductor chip, resulting in package cracks and characteristic deterioration. In order to alleviate the stress concentration, according to the related art, the corner of the lower surface of the upper semiconductor chip is polished. Alternatively, “all side surfaces” of the upper semiconductor chip are covered with the resin layer. That is, regardless of the lower semiconductor chip, a device has been devised to alleviate the stress concentration on the corner of the upper semiconductor chip in the face-down state.

特許文献２に記載されたＭＣＰによれば、下部半導体チップはバンプを有し、そのバンプを介して回路基板に“フリップチップ接続”されている。すなわち、下部半導体チップは、回路面が回路基板に対向するように、回路基板にバンプ接続されている。そのバンプ接続に対する信頼性を向上させるために、下部半導体チップ及び上部半導体チップのそれぞれの側面が、回路基板から該側面に延在する樹脂によって覆われている。   According to the MCP described in Patent Document 2, the lower semiconductor chip has bumps, and is “flip-chip connected” to the circuit board via the bumps. That is, the lower semiconductor chip is bump-connected to the circuit board so that the circuit surface faces the circuit board. In order to improve the reliability of the bump connection, the side surfaces of the lower semiconductor chip and the upper semiconductor chip are covered with a resin extending from the circuit board to the side surface.

特開２００２−１９８４８７号公報JP 2002-198487 A 特開２００４−１６５２８３号公報JP 2004-165283 A

パッケージ構造の小型化、薄型化に伴い、多段積層される半導体チップの薄型化も進んでいる。その場合、半導体チップにかかる応力の影響が顕著になり、その応力に起因する特性不良が懸念される。半導体チップの薄型化に対応し、且つ、デバイス特性を確保することができるパッケージ構造が重要である。   As package structures become smaller and thinner, semiconductor chips that are stacked in multiple stages are also becoming thinner. In that case, the influence of the stress applied to the semiconductor chip becomes significant, and there is a concern about characteristic defects caused by the stress. It is important to have a package structure that can reduce the thickness of a semiconductor chip and ensure device characteristics.

半導体チップにかかる応力は、（１）封止樹脂の硬化収縮による応力、（２）各材料の線膨張係数、弾性率の差異に起因した反りによる応力、に区分することができる。後者の応力は、一般的に、次の式：Ｅｔ／２Ｒ（Ｅ；半導体チップの弾性率、ｔ；半導体チップの厚さ、Ｒ；曲率半径）で与えられる。すなわち、後者の応力は、半導体チップが薄くなるにつれて小さくなり、前者の応力に比べて十分小さくなる。従って、封止樹脂の硬化収縮による応力を最適化することが、最も有効である。   The stress applied to the semiconductor chip can be classified into (1) stress due to curing shrinkage of the sealing resin, and (2) stress due to warpage caused by the difference in linear expansion coefficient and elastic modulus of each material. The latter stress is generally given by the following formula: Et / 2R (E: elastic modulus of semiconductor chip, t: thickness of semiconductor chip, R: radius of curvature). In other words, the latter stress decreases as the semiconductor chip becomes thinner, and is sufficiently smaller than the former stress. Therefore, it is most effective to optimize the stress due to the curing shrinkage of the sealing resin.

本発明の目的は、半導体装置の小型化を実現でき、且つ、デバイス特性の劣化を防止できる技術を提供することにある。   An object of the present invention is to provide a technique capable of realizing miniaturization of a semiconductor device and preventing deterioration of device characteristics.

本発明の他の目的は、下部半導体チップの回路面に対する、封止樹脂の硬化収縮による応力を分散させることができるＭＣＰを提供することにある。   Another object of the present invention is to provide an MCP that can disperse stress due to hardening shrinkage of the sealing resin on the circuit surface of the lower semiconductor chip.

以下に、［発明を実施するための最良の形態］で使用される番号・符号を用いて、［課題を解決するための手段］を説明する。これらの番号・符号は、［特許請求の範囲］の記載と［発明を実施するための最良の形態］との対応関係を明らかにするために括弧付きで付加されたものである。ただし、それらの番号・符号を、［特許請求の範囲］に記載されている発明の技術的範囲の解釈に用いてはならない。   [Means for Solving the Problems] will be described below using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

本発明の第１の観点において、半導体装置が提供される。その半導体装置は、ＭＣＰ構造を有している。具体的には、本発明に係る半導体装置は、回路基板（１）と、回路基板（１）上に搭載された第１半導体チップ（１０）と、第１半導体チップ（１０）上に搭載された第２半導体チップ（２０）と、第１半導体チップ（１０）及び第２半導体チップ（２０）を封止する封止樹脂（５０）と、を備える。第１半導体チップ（１０）の回路面（１１）は、回路基板（１）側と反対側に位置する。本発明に係る半導体装置は更に、第２半導体チップ（２０）の側面のうち、第１半導体チップ（１０）の回路面（１１）とオーバラップする側面（２２）を覆うフィレット（３０）を備える。   In a first aspect of the present invention, a semiconductor device is provided. The semiconductor device has an MCP structure. Specifically, the semiconductor device according to the present invention is mounted on the circuit board (1), the first semiconductor chip (10) mounted on the circuit board (1), and the first semiconductor chip (10). A second semiconductor chip (20), and a sealing resin (50) for sealing the first semiconductor chip (10) and the second semiconductor chip (20). The circuit surface (11) of the first semiconductor chip (10) is located on the side opposite to the circuit board (1) side. The semiconductor device according to the present invention further includes a fillet (30) that covers a side surface (22) of the second semiconductor chip (20) that overlaps the circuit surface (11) of the first semiconductor chip (10). .

第１半導体チップ（１０）の回路面（１１）に対する、封止樹脂（５０）の硬化収縮による応力は、その封止樹脂（５０）の厚さに比例する。ＭＣＰ構造では、第１半導体チップ（１０）と第２半導体チップ（２０）が積層されているため、場所によって封止樹脂（５０）の厚さが異なる。すなわち、第１半導体チップ（１０）の回路面（１１）に対する応力は、場所によって異なる。特に、第２半導体チップ（２０）の側面のうち、第１半導体チップ（１０）の回路面（１１）とオーバラップする側面（２２）の位置では、封止樹脂（５０）の厚さが不連続であり、局所的な「応力ギャップ」が生ずる。   The stress due to curing shrinkage of the sealing resin (50) on the circuit surface (11) of the first semiconductor chip (10) is proportional to the thickness of the sealing resin (50). In the MCP structure, since the first semiconductor chip (10) and the second semiconductor chip (20) are stacked, the thickness of the sealing resin (50) varies depending on the location. That is, the stress on the circuit surface (11) of the first semiconductor chip (10) varies depending on the location. In particular, at the position of the side surface (22) that overlaps the circuit surface (11) of the first semiconductor chip (10) among the side surfaces of the second semiconductor chip (20), the thickness of the sealing resin (50) is inadequate. It is continuous and creates a local “stress gap”.

その応力ギャップを低減するために、本発明によれば、フィレット（３０）が設けられる。そのフィレット（３０）は、第２半導体チップ（２０）の側面のうち、第１半導体チップ（１０）の回路面（１１）とオーバラップする側面（２２）を少なくとも覆うように形成される。その結果、封止樹脂（５０）の厚さの差に起因する応力ギャップが緩和される。すなわち、第１半導体チップ（１０）の回路面（１１）に対する応力が分散される。従って、デバイス特性を損なうことなく、半導体装置を小型化することが可能となる。   In order to reduce the stress gap, according to the invention, a fillet (30) is provided. The fillet (30) is formed so as to cover at least the side surface (22) overlapping the circuit surface (11) of the first semiconductor chip (10) among the side surfaces of the second semiconductor chip (20). As a result, the stress gap due to the difference in thickness of the sealing resin (50) is relaxed. That is, the stress on the circuit surface (11) of the first semiconductor chip (10) is dispersed. Therefore, it is possible to reduce the size of the semiconductor device without impairing device characteristics.

本発明の第２の観点において、半導体装置の製造方法が提供される。その製造方法は、（Ａ）回路基板（１）上に、回路面（１１）が回路基板（１）側と反対側に位置するように第１半導体チップ（１０）を搭載する工程と、（Ｂ）第１半導体チップ（１０）上に、第２半導体チップ（２０）を搭載する工程と、（Ｃ）第２半導体チップ（２０）の側面のうち、第１半導体チップ（１０）の回路面（１１）とオーバラップする側面（２２）を覆うようにフィレット（３０）を形成する工程と、（Ｄ）第１半導体チップ（１０）と第２半導体チップ（２０）を封止樹脂（５０）で封止する工程と、を有する。   In a second aspect of the present invention, a method for manufacturing a semiconductor device is provided. The manufacturing method includes (A) mounting the first semiconductor chip (10) on the circuit board (1) so that the circuit surface (11) is located on the side opposite to the circuit board (1), B) A step of mounting the second semiconductor chip (20) on the first semiconductor chip (10), and (C) a circuit surface of the first semiconductor chip (10) among the side surfaces of the second semiconductor chip (20). Forming a fillet (30) so as to cover the side surface (22) overlapping with (11), and (D) sealing resin (50) between the first semiconductor chip (10) and the second semiconductor chip (20). And sealing with.

本発明によれば、下部半導体チップの回路面に対する、封止樹脂の硬化収縮による応力を分散させることが可能となる。従って、デバイス特性を損なうことなくＭＣＰ構造を採用し、高い信頼性を有する小型の半導体装置を実現することが可能となる。   According to the present invention, it is possible to disperse the stress due to the curing shrinkage of the sealing resin on the circuit surface of the lower semiconductor chip. Therefore, it is possible to realize a small semiconductor device that employs the MCP structure without impairing device characteristics and has high reliability.

添付図面を参照して、本発明の実施の形態に係る半導体装置及びその製造方法を説明する。本実施の形態に係る半導体装置は、ＭＣＰ構造を有しており、少なくとも２つの半導体チップを搭載している。   A semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the accompanying drawings. The semiconductor device according to the present embodiment has an MCP structure and is mounted with at least two semiconductor chips.

１．構造
図２は、本実施の形態に係る半導体装置の構造の一例を示す断面図である。図２に示される半導体装置は、回路基板１、下部半導体チップ（第１半導体チップ）１０、上部半導体チップ（第２半導体チップ）２０、フィレット３０、封止樹脂５０、及びはんだボール６０を備えている。回路基板１としては、ガラスクロス基板やセラミック基板が例示される。封止樹脂５０は、半導体チップ１０、２０を含む全体を封止している。はんだボール６０は、回路基板１の下面に形成されている。 1. Structure FIG. 2 is a cross-sectional view showing an example of the structure of the semiconductor device according to the present embodiment. The semiconductor device shown in FIG. 2 includes a circuit board 1, a lower semiconductor chip (first semiconductor chip) 10, an upper semiconductor chip (second semiconductor chip) 20, a fillet 30, a sealing resin 50, and solder balls 60. Yes. Examples of the circuit board 1 include a glass cloth substrate and a ceramic substrate. The sealing resin 50 seals the whole including the semiconductor chips 10 and 20. The solder ball 60 is formed on the lower surface of the circuit board 1.

下部半導体チップ１０は、回路基板１の実装面（上面）上に搭載されている。回路基板１と下部半導体チップ１０は、接着ペーストや接着シートといった接着剤５を介して互いに接着されている。下部半導体チップ１０の素子や回路は、回路面１１側に形成されている。本実施の形態において、下部半導体チップ１０の回路面１１は、回路基板１側と反対側に位置している。下部半導体チップ１０の回路面１１は、金線４１を通して回路基板１に電気的に接続されている。つまり、本実施の形態において、下部半導体チップ１０は、回路基板１に対してフリップチップ接続されていない。   The lower semiconductor chip 10 is mounted on the mounting surface (upper surface) of the circuit board 1. The circuit board 1 and the lower semiconductor chip 10 are bonded to each other via an adhesive 5 such as an adhesive paste or an adhesive sheet. The elements and circuits of the lower semiconductor chip 10 are formed on the circuit surface 11 side. In the present embodiment, the circuit surface 11 of the lower semiconductor chip 10 is located on the side opposite to the circuit board 1 side. The circuit surface 11 of the lower semiconductor chip 10 is electrically connected to the circuit board 1 through a gold wire 41. That is, in the present embodiment, the lower semiconductor chip 10 is not flip-chip connected to the circuit board 1.

上部半導体チップ２０は、下部半導体チップ１０上に搭載されている。下部半導体チップ１０と上部半導体チップ２０は、接着ペーストや接着シートといった接着剤１５を介して互いに接着されている。上部半導体チップ２０の素子や回路は、回路面２１側に形成されている。図２において、その回路面２１は、回路基板１側と反対側に位置している。上部半導体チップ２０の回路面２１は、金線４２を通して回路基板１又は下部半導体チップ１０に電気的に接続されている。つまり、上部半導体チップ２０は、フェイスダウン状態ではない。   The upper semiconductor chip 20 is mounted on the lower semiconductor chip 10. The lower semiconductor chip 10 and the upper semiconductor chip 20 are bonded to each other via an adhesive 15 such as an adhesive paste or an adhesive sheet. The elements and circuits of the upper semiconductor chip 20 are formed on the circuit surface 21 side. In FIG. 2, the circuit surface 21 is located on the side opposite to the circuit board 1 side. The circuit surface 21 of the upper semiconductor chip 20 is electrically connected to the circuit board 1 or the lower semiconductor chip 10 through a gold wire 42. That is, the upper semiconductor chip 20 is not in a face-down state.

図３は、図２で示された構造の一部を拡大して示している。図３に示されるように、フィレット３０は、下部半導体チップ１０の回路面１１上に、上部半導体チップ２０の側面２２を覆うように形成されている。フィレット３０は、ディスペンサー等でフィレット材を塗布することにより形成される。フィレット材は液状であり、半導体チップの接着に用いられた接着剤５、１５とは異なる材料である。フィレット材が液状であるため、毛細管現象等により、フィレット３０の断面形状は三角形に近くなる。   FIG. 3 shows an enlarged part of the structure shown in FIG. As shown in FIG. 3, the fillet 30 is formed on the circuit surface 11 of the lower semiconductor chip 10 so as to cover the side surface 22 of the upper semiconductor chip 20. The fillet 30 is formed by applying a fillet material with a dispenser or the like. The fillet material is liquid and is a material different from the adhesives 5 and 15 used for bonding the semiconductor chip. Since the fillet material is liquid, the cross-sectional shape of the fillet 30 is close to a triangle due to capillary action or the like.

図４は、フィレット３０による効果を説明するための図である。図４には、フィレット３０が形成されていないパターン（Ａ）と、フィレット３０が形成されているパターン（Ｂ）及びパターン（Ｃ）が示されている。更に、図４の最下段には、下部半導体チップ１０の回路面１１に印加される応力の分布が示されている。その応力は、封止樹脂５０の硬化収縮に起因する応力であり、その大きさは封止樹脂５０の厚さに比例する。ＭＣＰ構造では、下部半導体チップ１０と上部半導体チップ２０が積層されているため、場所によって封止樹脂５０の厚さが異なり得る。すなわち、下部半導体チップ１０の回路面１１に対する応力は、場所によって異なり得る。   FIG. 4 is a diagram for explaining the effect of the fillet 30. FIG. 4 shows a pattern (A) where the fillet 30 is not formed, a pattern (B) and a pattern (C) where the fillet 30 is formed. Furthermore, the lowermost stage of FIG. 4 shows the distribution of stress applied to the circuit surface 11 of the lower semiconductor chip 10. The stress is a stress caused by curing shrinkage of the sealing resin 50, and the magnitude thereof is proportional to the thickness of the sealing resin 50. In the MCP structure, since the lower semiconductor chip 10 and the upper semiconductor chip 20 are stacked, the thickness of the sealing resin 50 may vary depending on the location. That is, the stress on the circuit surface 11 of the lower semiconductor chip 10 may vary depending on the location.

パターン（Ａ）の場合、下部半導体チップ１０と上部半導体チップ２０がオーバラップしている領域での封止樹脂５０の厚さは“ｔ１”である。一方、下部半導体チップ１０と上部半導体チップ２０がオーバラップしていない領域での封止樹脂５０の厚さは“ｔ４（＞ｔ１）”である。つまり、封止樹脂５０の厚さは、上部半導体チップ２０の側面２２を挟んで不連続である。結果として、下段の応力分布で示されているように、その側面２２の位置において局所的な「応力ギャップ」が発生する。この応力ギャップが、下部半導体チップ１０の特性の劣化の原因となる。   In the case of the pattern (A), the thickness of the sealing resin 50 in the region where the lower semiconductor chip 10 and the upper semiconductor chip 20 overlap is “t1”. On the other hand, the thickness of the sealing resin 50 in the region where the lower semiconductor chip 10 and the upper semiconductor chip 20 do not overlap is “t4 (> t1)”. That is, the thickness of the sealing resin 50 is discontinuous across the side surface 22 of the upper semiconductor chip 20. As a result, as indicated by the lower stress distribution, a local “stress gap” occurs at the position of the side surface 22. This stress gap causes the characteristics of the lower semiconductor chip 10 to deteriorate.

その応力ギャップを低減するために、本実施の形態によれば、上部半導体チップ２０の側面２２を覆うようにフィレット３０が設けられている。例えばパターン（Ｂ）の場合、フィレット３０が設けられていることにより、封止樹脂５０の厚さは、“ｔ１”から“ｔ２”を経て“ｔ４”に徐々に変化する（ｔ１＜ｔ２＜ｔ４）。その結果、下部半導体チップ１０の回路面１１に対する応力も滑らかに変化する。また、パターン（Ｃ）の場合、封止樹脂５０の厚さは、“ｔ１”から“ｔ２”、“ｔ３”を経て“ｔ４”に徐々に変化する（ｔ１＜ｔ２＜ｔ３＜ｔ４）。その結果、下部半導体チップ１０の回路面１１に対する応力は、更に滑らかに変化する。   In order to reduce the stress gap, according to the present embodiment, the fillet 30 is provided so as to cover the side surface 22 of the upper semiconductor chip 20. For example, in the case of the pattern (B), since the fillet 30 is provided, the thickness of the sealing resin 50 gradually changes from “t1” through “t2” to “t4” (t1 <t2 <t4). ). As a result, the stress on the circuit surface 11 of the lower semiconductor chip 10 also changes smoothly. In the case of pattern (C), the thickness of the sealing resin 50 gradually changes from “t1” to “t4” through “t2” and “t3” (t1 <t2 <t3 <t4). As a result, the stress on the circuit surface 11 of the lower semiconductor chip 10 changes more smoothly.

このように、本実施の形態によれば、封止樹脂５０の厚さの差に起因する応力ギャップが緩和される。すなわち、下部半導体チップ１０の回路面１１に対する応力が分散され、応力集中が防止される。その結果、デバイス特性の劣化が防止され、半導体装置の信頼性が向上する。言い換えれば、デバイス特性を損なうことなくＭＣＰ構造を採用し、高い信頼性を有する小型の半導体装置を実現することが可能となる。   Thus, according to the present embodiment, the stress gap due to the difference in thickness of the sealing resin 50 is relaxed. That is, stress on the circuit surface 11 of the lower semiconductor chip 10 is dispersed, and stress concentration is prevented. As a result, device characteristics are prevented from being deteriorated, and the reliability of the semiconductor device is improved. In other words, it is possible to realize a small semiconductor device having a high reliability by adopting the MCP structure without impairing device characteristics.

尚、下部半導体チップ１０に対する応力ギャップを低減させるために、フィレット３０は、上部半導体チップ２０の側面のうち、下部半導体チップ１０の回路面１１とオーバラップする側面２２を少なくとも覆うように形成される。その側面２２での応力ギャップを極力小さくするため、フィレット３０は、上部半導体チップ２０の回路面２１（回路基板１側と反対側の面）の近傍まで達している。好適には、図３や図４で示されたように、フィレット３０は、上部半導体チップ２０の回路面２１と少なくとも同じレベルに達している。その場合、当該側面２２での応力ギャップが消滅する。   In order to reduce the stress gap with respect to the lower semiconductor chip 10, the fillet 30 is formed so as to cover at least the side surface 22 that overlaps the circuit surface 11 of the lower semiconductor chip 10 among the side surfaces of the upper semiconductor chip 20. . In order to minimize the stress gap on the side surface 22, the fillet 30 reaches the vicinity of the circuit surface 21 (surface opposite to the circuit board 1 side) of the upper semiconductor chip 20. Preferably, as shown in FIG. 3 and FIG. 4, the fillet 30 reaches at least the same level as the circuit surface 21 of the upper semiconductor chip 20. In that case, the stress gap at the side surface 22 disappears.

また、下部半導体チップ１０に対する応力分布を滑らかに変化させるために、封止樹脂５０の厚さは、図４で示されたように徐々に変化することが望ましい。言い換えれば、フィレット３０の厚さは、上部半導体チップ２０の側面２２から離れるにつれて単調減少することが好適である。応力分散の観点からは、フィレット３０の表面の勾配（単調減少の割合）は４５度以下であることが好適である。これにより、応力が効果的に分散される。   Further, in order to smoothly change the stress distribution on the lower semiconductor chip 10, it is desirable that the thickness of the sealing resin 50 gradually change as shown in FIG. 4. In other words, it is preferable that the thickness of the fillet 30 decreases monotonously as the distance from the side surface 22 of the upper semiconductor chip 20 increases. From the viewpoint of stress dispersion, it is preferable that the gradient of the surface of the fillet 30 (the monotonically decreasing rate) is 45 degrees or less. This effectively distributes the stress.

図５に示される例では、フィレット３０は、下部半導体チップ１０の回路面１１のうち上部半導体チップ２０とオーバラップしていない領域を全て覆うように形成されている。つまり、フィレット３０は、下部半導体チップ１０の端部まで達するように形成されている。この場合、フィレット３０の表面の勾配が最も小さくなり、好適である。   In the example shown in FIG. 5, the fillet 30 is formed so as to cover the entire area of the circuit surface 11 of the lower semiconductor chip 10 that does not overlap with the upper semiconductor chip 20. That is, the fillet 30 is formed to reach the end of the lower semiconductor chip 10. In this case, the gradient of the surface of the fillet 30 is the smallest, which is preferable.

図６に示される例では、フィレット３０は、上部半導体チップ２０の回路面２１の一部も覆うように形成されている。この場合でも、上述の効果が得られる。また、フィレット３０は、回路基板１の表面まで覆うように形成されていてもよい。但し、下部半導体チップ１０に対する応力ギャップを低減させるためには、フィレット３０が下部半導体チップ１０の回路面１１上にだけ形成されていれば十分である。フィレット３０が、上部半導体チップ２０の回路面２１上や回路基板１の表面上に形成されない場合、フィレット材を節約することができる。   In the example shown in FIG. 6, the fillet 30 is formed so as to cover a part of the circuit surface 21 of the upper semiconductor chip 20. Even in this case, the above-described effects can be obtained. The fillet 30 may be formed so as to cover the surface of the circuit board 1. However, in order to reduce the stress gap with respect to the lower semiconductor chip 10, it is sufficient that the fillet 30 is formed only on the circuit surface 11 of the lower semiconductor chip 10. When the fillet 30 is not formed on the circuit surface 21 of the upper semiconductor chip 20 or the surface of the circuit board 1, the fillet material can be saved.

図７は、本実施の形態に係る半導体装置の一例を示す上面図である。図７において、上部半導体チップ２０の横幅は、下部半導体チップ１０の横幅よりも小さいが、上部半導体チップ２０の縦幅は、下部半導体チップ１０の縦幅よりも大きい。すなわち、上部半導体チップ２０の一部が、下部半導体チップ１０からはみ出している。そして、上部半導体チップ２０の側面のうち、側面２２ａ、２２ｂが、下部半導体チップ１０の回路面１１とオーバラップしている。   FIG. 7 is a top view showing an example of the semiconductor device according to the present embodiment. In FIG. 7, the horizontal width of the upper semiconductor chip 20 is smaller than the horizontal width of the lower semiconductor chip 10, but the vertical width of the upper semiconductor chip 20 is larger than the vertical width of the lower semiconductor chip 10. That is, a part of the upper semiconductor chip 20 protrudes from the lower semiconductor chip 10. Of the side surfaces of the upper semiconductor chip 20, the side surfaces 22 a and 22 b overlap the circuit surface 11 of the lower semiconductor chip 10.

図７に示された例の場合、側面２２ａ、２２ｂの位置での局所的な応力ギャップを緩和する必要がある。そのため、図７に示されるように、フィレット３０は、下部半導体チップ１０とオーバラップする側面２２ａ、２２ｂだけを覆うように形成される。逆に言えば、本実施の形態において、上部半導体チップ２０の“全ての側面”を覆うようにフィレット３０を形成する必要は必ずしもない。本実施の形態によれば、フィレット３０は、上部半導体チップ２０の側面のうち、下部半導体チップ１０の回路面１１とオーバラップする側面を少なくとも覆うように形成される。   In the case of the example shown in FIG. 7, it is necessary to relax the local stress gap at the positions of the side surfaces 22a and 22b. Therefore, as shown in FIG. 7, the fillet 30 is formed so as to cover only the side surfaces 22 a and 22 b that overlap the lower semiconductor chip 10. In other words, in the present embodiment, it is not always necessary to form the fillet 30 so as to cover “all side surfaces” of the upper semiconductor chip 20. According to the present embodiment, the fillet 30 is formed so as to cover at least a side surface of the upper semiconductor chip 20 that overlaps the circuit surface 11 of the lower semiconductor chip 10.

尚、下部半導体チップ１０と回路基板１との接続形態として、フリップチップ接続も考えられる。しかしながら、その場合、封止樹脂５０は回路面１１と逆側の面上に形成されるため、封止樹脂５０の厚さの差に起因する応力ギャップを考慮する必要はない。   As a connection form between the lower semiconductor chip 10 and the circuit board 1, flip chip connection is also conceivable. However, in that case, since the sealing resin 50 is formed on the surface opposite to the circuit surface 11, it is not necessary to consider the stress gap caused by the difference in the thickness of the sealing resin 50.

ＭＣＰに搭載される半導体チップの段数は、２段に限られない。３段以上の半導体チップが１つのＭＣＰに搭載されてもよい。その場合、各層において同様にフィレットを形成することにより、上述の効果と同様の効果が得られる。但し、応力に対する耐性は半導体チップの機能によっても異なるため、全ての半導体チップに対してフィレットを適用する必要はない。必要な半導体チップのみに選択的にフィレットを適用すればよい。   The number of semiconductor chips mounted on the MCP is not limited to two. Three or more stages of semiconductor chips may be mounted on one MCP. In that case, the effect similar to the above-mentioned effect is acquired by forming a fillet in each layer similarly. However, since the resistance to stress differs depending on the function of the semiconductor chip, it is not necessary to apply fillets to all the semiconductor chips. The fillet may be selectively applied only to the necessary semiconductor chip.

２．製造方法
図８は、本実施の形態に係るＭＣＰの製造方法を示すフローチャートである。既出の図２及び図８に示されたフローチャートを参照して、本実施の形態に係るＭＣＰの製造方法を説明する。 2. Manufacturing Method FIG. 8 is a flowchart showing a method for manufacturing the MCP according to the present embodiment. The manufacturing method of the MCP according to the present embodiment will be described with reference to the flowcharts shown in FIGS.

まず、ガラスクロス基板やセラミック基板といった回路基板１が提供される。そして、その回路基板１上に、下部半導体チップ１０が搭載される（ステップＳ１）。回路基板１と下部半導体チップ１０は、接着ペーストや接着シートといった接着剤５を介して互いに接着される。この時、下部半導体チップ１０の回路面１１は、回路基板１側と反対側に位置している。続いて、下部半導体チップ１０と回路基板１とが、金線４１で電気的に接続される（ステップＳ２）。   First, a circuit board 1 such as a glass cloth substrate or a ceramic substrate is provided. Then, the lower semiconductor chip 10 is mounted on the circuit board 1 (step S1). The circuit board 1 and the lower semiconductor chip 10 are bonded to each other via an adhesive 5 such as an adhesive paste or an adhesive sheet. At this time, the circuit surface 11 of the lower semiconductor chip 10 is located on the side opposite to the circuit board 1 side. Subsequently, the lower semiconductor chip 10 and the circuit board 1 are electrically connected by the gold wire 41 (step S2).

次に、下部半導体チップ１０上に、上部半導体チップ２０が搭載される（ステップＳ３）。下部半導体チップ１０と上部半導体チップ２０は、接着ペーストや接着シートといった接着剤１５を介して互いに接着される。   Next, the upper semiconductor chip 20 is mounted on the lower semiconductor chip 10 (step S3). The lower semiconductor chip 10 and the upper semiconductor chip 20 are bonded to each other via an adhesive 15 such as an adhesive paste or an adhesive sheet.

次に、上述のフィレット３０が、上部半導体チップ２０の側面のうち、下部半導体チップ１０の回路面１１とオーバラップする側面を少なくとも覆うように形成される（ステップＳ４）。フィレット３０は、ディスペンサー等でフィレット材を塗布することにより形成される。フィレット材は液状であり、接着剤５、１５とは異なる材料である。フィレット材が液状であるため、毛細管現象等により、フィレット３０の断面形状は三角形に近くなる（図２〜図６参照）。   Next, the above-described fillet 30 is formed so as to cover at least the side surface of the upper semiconductor chip 20 that overlaps the circuit surface 11 of the lower semiconductor chip 10 (step S4). The fillet 30 is formed by applying a fillet material with a dispenser or the like. The fillet material is liquid and is different from the adhesives 5 and 15. Since the fillet material is liquid, the cross-sectional shape of the fillet 30 is close to a triangle due to a capillary phenomenon or the like (see FIGS. 2 to 6).

次に、上部半導体チップ２０と回路基板１あるいは下部半導体チップ１０とが、金線４２で電気的に接続される（ステップＳ５）。続いて、封止樹脂５０で全体が封止される（ステップＳ６）。更に、回路基板１の下面にはんだボール６０が形成される（ステップＳ７）。   Next, the upper semiconductor chip 20 and the circuit board 1 or the lower semiconductor chip 10 are electrically connected by the gold wire 42 (step S5). Subsequently, the whole is sealed with the sealing resin 50 (step S6). Further, solder balls 60 are formed on the lower surface of the circuit board 1 (step S7).

このようにして、本実施の形態に係るＭＣＰが作成される。尚、金線の接続工程、フィレット形成工程の順序は任意である。必要に応じて順番を最適化すればよい。   In this way, the MCP according to the present embodiment is created. The order of the gold wire connecting step and the fillet forming step is arbitrary. What is necessary is just to optimize an order as needed.

図１は、従来のＭＣＰ（Multi Chip Package）の構造を示す断面図である。FIG. 1 is a cross-sectional view showing the structure of a conventional MCP (Multi Chip Package). 図２は、本発明に係るＭＣＰの構造の一例を示す断面図である。FIG. 2 is a sectional view showing an example of the structure of the MCP according to the present invention. 図３は、図２に示された構造の一部を示す拡大断面図である。FIG. 3 is an enlarged cross-sectional view showing a part of the structure shown in FIG. 図４は、本発明による効果を説明するための図である。FIG. 4 is a diagram for explaining the effect of the present invention. 図５は、本発明に係るＭＣＰの変形例を示す拡大断面図である。FIG. 5 is an enlarged cross-sectional view showing a modified example of the MCP according to the present invention. 図６は、本発明に係るＭＣＰの他の変形例を示す拡大断面図である。FIG. 6 is an enlarged cross-sectional view showing another modified example of the MCP according to the present invention. 図７は、本発明に係るＭＣＰの更に他の変形例を示す上面図である。FIG. 7 is a top view showing still another modified example of the MCP according to the present invention. 図８は、本発明に係るＭＣＰの製造方法を示すフローチャートである。FIG. 8 is a flowchart showing a method for manufacturing an MCP according to the present invention.

符号の説明Explanation of symbols

１ 回路基板
５ 接着剤
１０ 下部半導体チップ（第１半導体チップ）
１１ 回路面
１５ 接着剤
２０ 上部半導体チップ（第２半導体チップ）
２１ 回路面
２２ 側面
３０ フィレット
４１ 金線
４２ 金線
５０ 封止樹脂
６０ はんだボール DESCRIPTION OF SYMBOLS 1 Circuit board 5 Adhesive 10 Lower semiconductor chip (1st semiconductor chip)
11 Circuit surface 15 Adhesive 20 Upper semiconductor chip (second semiconductor chip)
21 Circuit surface 22 Side surface 30 Fillet 41 Gold wire 42 Gold wire 50 Sealing resin 60 Solder ball

Claims (7)

回路基板と、
前記回路基板上に搭載され、回路面が前記回路基板側と反対側に位置する第１半導体チップと、
前記第１半導体チップ上に搭載された第２半導体チップと、
前記第２半導体チップの側面のうち、前記第１半導体チップの前記回路面とオーバラップする側面を覆うフィレットと、
前記第１半導体チップと前記第２半導体チップを封止する封止樹脂と
を備える
半導体装置。 A circuit board;
A first semiconductor chip mounted on the circuit board and having a circuit surface located on the opposite side of the circuit board;
A second semiconductor chip mounted on the first semiconductor chip;
A fillet that covers a side surface of the second semiconductor chip that overlaps the circuit surface of the first semiconductor chip;
A semiconductor device comprising: a sealing resin that seals the first semiconductor chip and the second semiconductor chip. 請求項１に記載の半導体装置であって、
前記フィレットは、前記第２半導体チップの前記回路基板側と反対側の主面に少なくとも達するように形成された
半導体装置。 The semiconductor device according to claim 1,
The fillet is formed so as to reach at least a main surface of the second semiconductor chip opposite to the circuit board. 請求項１又は２に記載の半導体装置であって、
前記フィレットの厚さは、前記第２半導体チップの側面から離れるにつれて単調に減少する
半導体装置。 The semiconductor device according to claim 1 or 2,
The thickness of the fillet monotonously decreases with increasing distance from the side surface of the second semiconductor chip. 請求項３に記載の半導体装置であって、
前記フィレットの表面の勾配は、４５度以下である
半導体装置。 The semiconductor device according to claim 3,
The slope of the surface of the fillet is 45 degrees or less. Semiconductor device. 請求項１乃至４のいずれかに記載の半導体装置であって、
前記フィレットは、前記第１半導体チップの前記回路面のうち前記第２半導体チップとオーバラップしていない領域を全て覆うように形成された
半導体装置。 The semiconductor device according to claim 1,
The fillet is formed so as to cover all areas of the circuit surface of the first semiconductor chip that do not overlap the second semiconductor chip. 請求項１乃至５のいずれかに記載の半導体装置であって、
前記フィレットは、前記回路基板の表面上には形成されない
半導体装置。 A semiconductor device according to claim 1,
The fillet is not formed on a surface of the circuit board. （Ａ）回路基板上に、第１半導体チップを搭載する工程と、
ここで、前記第１半導体チップの回路面は、前記回路基板側と反対側に位置し、
（Ｂ）前記第１半導体チップ上に、第２半導体チップを搭載する工程と、
（Ｃ）前記第２半導体チップの側面のうち、前記第１半導体チップの前記回路面とオーバラップする側面を覆うようにフィレットを形成する工程と、
（Ｄ）前記第１半導体チップと前記第２半導体チップを封止樹脂で封止する工程と
を有する
半導体装置の製造方法。 (A) mounting a first semiconductor chip on a circuit board;
Here, the circuit surface of the first semiconductor chip is located on the side opposite to the circuit board side,
(B) mounting a second semiconductor chip on the first semiconductor chip;
(C) forming a fillet so as to cover a side surface of the second semiconductor chip that overlaps the circuit surface of the first semiconductor chip;
(D) A method of manufacturing a semiconductor device, comprising: sealing the first semiconductor chip and the second semiconductor chip with a sealing resin.
JP2006354126A 2006-12-28 2006-12-28 Semiconductor device and its manufacturing method Withdrawn JP2008166477A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014156921A1 (en) * 2013-03-26 2014-10-02 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014156921A1 (en) * 2013-03-26 2014-10-02 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device
US10342118B2 (en) 2013-03-26 2019-07-02 Longitude Licensing Limited Semiconductor device

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