JP2008164675A - Scan converting circuit and scan converting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a scan converting circuit which is adaptive to various input image signals, small in number of set data for adaptation to display devices having various numbers of pixels, and small in circuit scale. <P>SOLUTION: A coefficient setting part 101 of the scan converting circuit sets calculation coefficients etc., for a long period and a short period (an initial term (a) and a tolerance (d) for finding a general term of an arithmetic progression), and a long period calculation part 102 and a short period calculation part 103 generate clock signals LCK and SCK having been thinned out except clock pulses in the order corresponding to the general term. Then a clock signal converting part 104 generates a conversion clock signal MCK by putting those clock signals together and then an image signal conversion part 105 obtains an output image signal Dout having been thinned out between pixel data of an input image signal Din according to the conversion clock signal MCK, so the number of set data is decreased and the circuit can be simplified. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a scan conversion circuit and a scan conversion method for converting various video signal formats, and more particularly, the number of pixels of a liquid crystal display device (LCD: Liquid Crystal Display) or a plasma display panel (PDP). The present invention relates to a scan conversion circuit and a scan conversion method for converting the format of various video signals so that the number of pixels that can be displayed on a fixed display device is obtained.

  In recent years, high-definition and high-quality display devices such as liquid crystal display devices are often used for electronic devices that perform digital image processing such as mobile phones and digital cameras. On the other hand, in recent years, with the advancement of digital television broadcasting technology, the format of the video signal (video signal) sent from the video signal sending device, for example, the scanning line frequency of the video signal to be displayed, the video display period, the video blanking period, etc. Are becoming more diverse. However, since a general display device such as a liquid crystal display device often has a fixed number of pixels in the horizontal direction on its display screen, the format of various video signals is the number of pixels that can be displayed on such a display device. A circuit for conversion is required. This circuit is called a scan conversion circuit.

  Conventionally, as a method employed in such a scan conversion circuit, an input image signal sampled by a built-in A / D conversion circuit is temporarily stored in an internal memory, and the number of pixels of the input image signal and an output image are stored. A method of converting by interpolating the image signal corresponding to the ratio to the number of pixels of the signal, or by reading out the image signal stored in the internal memory with a read clock signal corresponding to the number of pixels of the output image signal A conversion method is known.

  In such a conventional method, the scan conversion circuit adopting the former method performs predetermined weighting between pixel data according to the ratio between the number of pixels of the input image signal and the number of pixels of the output image signal, for example, There is a configuration in which complementary data is generated by multiplying each pixel data by a predetermined coefficient (hereinafter referred to as a first conventional example) (see, for example, Patent Document 1).

  In addition, in the scan conversion circuit adopting the latter method among the above conventional methods, as an example, in order to generate a clock signal corresponding to the number of pixels of the output image signal from the clock signal corresponding to the input image signal or the synchronization signal There is a configuration including a PLL circuit that locks at a ratio between the number of pixels of the input image signal and the number of pixels of the output image signal (hereinafter referred to as a second conventional example) (see, for example, FIG. 8 shown in Patent Document 1). ).

Furthermore, as another example of a scan conversion circuit that employs the latter method, a configuration (hereinafter referred to as a first configuration) that selects setting data according to the ratio between the number of pixels of the input image signal and the number of pixels of the output image signal and supplies the setting data to the clock generation circuit. 3 (referred to as Patent Document 2).
JP-A-5-316479 JP 2006-178114 A

  However, in the first and third conventional examples, weighting is applied between pixel data in order to appropriately correspond to input image signals of various formats and to appropriately correspond to display devices having various numbers of pixels. A lot of setting data given to the coefficient and the clock generation circuit must be determined in advance. Therefore, there is a problem that determination of setting data becomes complicated.

  In the third conventional example, it is necessary to adjust the parameters of the loop filter in the PLL circuit according to the type of the input signal and the ratio between the number of pixels of the input image signal and the number of pixels of the output image signal. There is a problem that the scale increases.

  Therefore, in the present invention, a scan with a small circuit scale and a small number of setting data that must be determined in advance in order to correspond to an input image signal having various formats and to correspond to a display device having various numbers of pixels. An object is to provide a conversion circuit and a scan conversion method.

According to a first aspect of the present invention, an input image signal given from the outside is set to be equal to the number of pixels in the horizontal direction in the input image signal so as to be equal to the number of display pixels in the horizontal direction in the image to be displayed on the display device. N and M are natural numbers) a scan conversion circuit for converting into an output image signal having a horizontal pixel number that is a multiple,
Based on predetermined setting data given from outside, different predetermined first and second periods, which are periodic clock pulse intervals obtained by thinning out one or more clock pulses included in an input clock signal given from outside, are set. Setting means for determining first and second period setting values for
First period calculating means for calculating a start position of the first period in the input clock signal based on the first period set value and outputting the calculated start position as a first period start signal;
Second period calculating means for calculating a start position of the second period in the input clock signal based on the second period setting value and outputting the calculated start position as a second period start signal;
Clock signal conversion means for outputting a converted clock signal having a clock pulse number that is N / M times the number of clock pulses in the input clock signal based on the first and second period start signals;
And image signal conversion means for converting the input image signal into the output image signal by thinning out pixel data included in the input image signal based on the converted clock signal.

According to a second invention, in the first invention,
The first period calculation means outputs a clock pulse of the input clock signal corresponding to a start position of the first period as the first period start signal,
The second period calculation means outputs a clock pulse of the input clock signal corresponding to a start position of the second period as the second period start signal,
The clock signal converting means generates and outputs the converted clock signal by synthesizing the first period start signal and the second period start signal.

According to a third invention, in the first or second invention,
The clock signal converting means generates a clock pulse that rises or falls at a predetermined time corresponding to each of the pixel data in synchronization with the pixel data included in the output image signal based on the first and second period start signals. An output clock signal including the same is output.

According to a fourth invention, in any one of the first to third inventions,
The setting means determines the order of the clock pulses included in the input clock signal based on the setting data and indicating the start position of the first period in the input clock signal. (N is an integer equal to or greater than 0), the initial term aL and the tolerance dL in the equation an = aL + (n−1) × dL are defined as the first period setting values, and the second period The first term aS and the tolerance dS in the equation an = aS + (n−1) × dS are defined as the first period set value when the order indicating the start position is expressed by the general term an in the arithmetic progression. And

A fifth invention is the fourth invention,
The setting means determines the natural number M based on the setting data,
The first period calculation means repeatedly increases n in the general term of the arithmetic progression determined by the first term aL and the tolerance dL, which are the first period setting values, by 1 repeatedly from 1 to M. Calculating the start position of the first period;
The second period calculation means repeatedly increases n in the general term of the arithmetic sequence determined by the first term aS and the tolerance dS, which are the second period setting values, by 1 repeatedly from 1 to M. The start position of the second period is calculated.

According to a sixth invention, in the fifth invention, further comprising third period calculating means for outputting a predetermined third period start signal,
The setting means has the first and second clock pulse intervals that are periodic clock pulse intervals obtained by thinning out one or more clock pulses included in an input clock signal supplied from the outside based on predetermined setting data supplied from the outside. A third period setting value for setting a third period different from the period is determined,
The third period calculating means calculates a start position of the third period in the input clock signal based on the third period set value, and uses the calculated start position as the third period start signal. Output,
The clock signal conversion means outputs a converted clock signal having a clock pulse number that is N / M times the number of clock pulses in the input clock signal, based on the first to third period start signals. To do.

According to a seventh aspect of the present invention, an input image signal given from the outside is set to be equal to the number of pixels in the horizontal direction in the input image signal so as to be equal to the number of display pixels in the horizontal direction in the image to be displayed on the display device. N and M are natural numbers) A scan conversion method for converting into an output image signal having a horizontal pixel number that is a multiple,
Based on predetermined setting data given from outside, different predetermined first and second periods, which are periodic clock pulse intervals obtained by thinning out one or more clock pulses included in an input clock signal given from outside, are set. A setting step for determining first and second period setting values for
A first period calculating step of calculating a start position of the first period in the input clock signal based on the first period set value and outputting the calculated start position as a first period start signal;
A second period calculating step of calculating a start position of the second period in the input clock signal based on the second period setting value and outputting the calculated start position as a second period start signal;
A clock signal converting step of outputting a converted clock signal having a clock pulse number that is N / M times the number of clock pulses in the input clock signal based on the first and second period start signals;
An image signal converting step of converting the input image signal into the output image signal by thinning out pixel data included in the input image signal based on the converted clock signal.

  According to the first invention, the setting values set by the setting means to correspond to various input image signals and to display devices having various pixel numbers are the first period setting value and the second period. Since it is a set value, the number of data to be set can be reduced and the circuit scale can be reduced.

  According to the second aspect of the present invention, the circuit scale can be further increased by a simple configuration in which the clock signal output from the first period calculation means and the second period calculation means is synthesized by the clock signal conversion means to generate the converted clock signal. Can be small.

  According to the third invention, the pixel data included in the output image signal is calculated based on the first and second period start signals, for example, without calculating the position and length of the clock pulse included in the converted clock signal. Can be obtained with a simple configuration.

  According to the fourth invention, the first period set value and the second period set value are the first term and tolerance in the equation indicating the general term of the arithmetic progression, thereby reducing the number of data to be set. can do.

  According to the fifth aspect, the first period setting value and the second period setting value can be calculated from an input clock signal composed of continuous clock pulses with a simple circuit configuration.

  According to the sixth aspect of the invention, by defining two different second periods depending on the setting means, it is possible to diversify the arrangement of clock pulses and cope with various clock reduction ratios.

  According to the seventh aspect, the same effect as that of the first aspect can be achieved in the scan conversion method.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
<1. First Embodiment>
FIG. 1 is a block diagram of a scan conversion circuit according to the first embodiment of the present invention.
As shown in FIG. 1, the scan conversion circuit 100 includes a coefficient setting unit 101 that sets a predetermined coefficient based on setting data given from the outside, and a period in which a clock interval in a conversion clock signal MCK (to be described later) becomes long (hereinafter referred to as “clock conversion interval”). A long period calculation unit 102 that calculates a start position of “long period”, a short period calculation unit 103 that calculates a start position of a period in which the clock interval is shortened (hereinafter referred to as “short period”), and A clock signal converter 104 that receives these start positions and outputs a converted clock signal MCK in which a part of the clock pulse is thinned, and an input image signal from the outside based on the thinned converted clock signal MCK as pixel data. Is converted to an output image signal Dout that is partially thinned out.

  The coefficient setting unit 101 receives setting data including predetermined numerical values given from the outside of the scan conversion circuit 100 such as a computer or a display device. This setting data includes a numerical value necessary for determining a clock pulse to be left without being thinned out of the input clock signal Cin. Here, the conversion is performed from the input clock signal Cin (before conversion) (after conversion). M, which is the denominator when the clock reduction ratio (the ratio of the number of pulses in the unit period) to the clock signal MCK is N / M (hereinafter, this value M is referred to as “base count value M”), and the conversion clock signal MCK This is data corresponding to the coefficient for calculating the start position of the long period in which the clock interval becomes longer and the start position of the short period in which the clock interval becomes shorter.

In the present scan conversion circuit 100, these start positions are represented by numbers indicating the order of clock pulses (the number from the predetermined position), and this number can be represented by a general term an in the arithmetic progression. That is, when the first term is a and the tolerance is d, it can be expressed as the following equation (1).
an = a + (n−1) × d (1)

Therefore, the number indicating the start position of the long period can be expressed as the following equation (2) when the first term is aL and the tolerance is dL. Therefore, the coefficient setting unit 101 uses the first term aL and the tolerance. dL is given to the long period calculation unit 102 as a coefficient for calculating the start position of the long period.
an = aL + (n−1) × dL (2)

The number indicating the start position of the short period can be expressed as the following equation (3) when the first term is aS and the tolerance is dS. dS is given to the short period calculation unit 103 as a coefficient for calculating the start position of the short period.
an = aS + (n−1) × dS (3)

  Furthermore, the coefficient setting unit 101 gives the base count value M included in the setting data to the long period calculation unit 102 and the short period calculation unit 103.

  The long period calculation unit 102 receives the first term aL and the tolerance dL and the base count value M, which are the coefficients, from the coefficient setting unit 101, and receives an input clock signal from a device external to the scan conversion circuit 100 such as a computer or a display device. Receive Cin. The long period calculation unit 102 extracts only the clock pulses having the numbers obtained by substituting the first term aL and the tolerance dL into the above equation (2) among the clock pulses included in the input clock signal Cin (transmission without thinning out). And output as a long clock signal LCK. The long clock signal LCK may be newly generated at the same clock pulse interval.

  Specifically, by repeating the sequential output of clock pulses having numbers obtained by sequentially substituting the numbers obtained by incrementing n from 1 to M one by one in the above formula (2), the long clock signal LCK is Generated. Of course, it is not always necessary to limit the upper limit value of n to M. However, considering that the clock reduction ratio is N / M, the generated clock signal is repeated in M cycles. , A simple configuration that limits the upper limit of n to M is preferable. The timing of this signal will be described later.

  The short period calculation unit 103 receives the first term aS and the tolerance dS and the base count value M, which are the coefficients, from the coefficient setting unit 101, and receives an input clock signal from a device external to the scan conversion circuit 100 such as a computer or a display device. Receive Cin. The short period calculation unit 103 extracts (transmits) only clock pulses having numbers obtained by substituting the first term aS and the tolerance dS into the above equation (3) among the clock pulses included in the input clock signal Cin. The short clock signal SCK is output. The short clock signal SCK may be newly generated at the same clock pulse interval. In addition, as in the case of the long period calculation unit 102 described above, a simple configuration in which the upper limit value of n is limited to M is preferable. Further, the timing of this signal will be described later.

  The clock signal conversion unit 104 synthesizes the long clock signal LCK received from the long period calculation unit 102 and the short clock signal SCK received from the short period calculation unit 103 (decimates a logical sum), thereby thinning out clock pulses. After that, a conversion clock signal MCK having a clock reduction ratio of N / M and an output clock signal Cout including a pulse in which the latter half of pixel data included in an output image signal Dout described later becomes almost active are generated. .

  Based on the input image signal Din and the converted clock signal MCK received from the clock signal converter 104, the image signal converter 105 generates an output image signal Dout in which pixel data is thinned out. In this manner, the ratio of the number of pixel data of the output image signal Dout to the input image signal Din can be converted (reduced) to N / M times. In the following, the operation of the scan conversion circuit 100 will be described in detail by explaining the timing of these various signals with reference to FIGS.

  FIG. 2 is a diagram for simply explaining the operation of generating the converted clock signal MCK from the input clock signal Cin in the present embodiment. Note that the clock reduction ratio N / M here is set to 2/3. As shown in FIG. 2, when the clock pulse of the input clock signal Cin is C1, C2, C3,..., C9 (C10 and thereafter are omitted in the figure) according to the number (order) ( The clock pulses of the converted clock signal MCK (not thinned out) are C1, C2, C4, C5, C7, C8,..., And the clock pulses C3, C6, C9,. In the figure, the correspondence relationship between clock pulses is indicated by arrows, and the thinned-out relationship is indicated by x. Thus, it can be seen that the ratio of the clock pulse of the converted clock signal MCK to the input clock signal Cin is 2/3 as set.

  As a result of the thinning out of the clock pulses, the converted clock signal MCK is formed with the short period, which is a short clock period, and the long period, which is a long clock period, and the start position of these periods. A clock pulse that rises is included. The clock pulse numbers in each short period and long period are calculated by the long period calculation unit 102 and the short period calculation unit 103 based on the above formulas (2) and (3), as described above. Subsequently, these will be described in detail with reference to FIG.

  FIG. 3 is a diagram illustrating a timing chart of various signals in the present embodiment. As described above, the clock reduction ratio N / M here is 2/3. As shown in FIG. 3, the long clock signal LCK output from the long period calculation unit 102 includes clock pulses C2, C5, C8,... Of the input clock signal Cin. Calculated based on equation (2). Here, the first term aL is set to 2 and the tolerance dL is set to 3 by the coefficient setting unit 101, and the clock pulse numbers (order) are 2, 5, 8, 11,. It becomes.

  Of course, the base count value M, which is the denominator of the clock reduction ratio N / M, is set to 3, and this base count value M is the upper limit value of n in the above equation (2). Of the three clock pulses with the clock pulse numbers 1 to 3 within the range including one clock pulse, the clock pulse with the number 2 is repeatedly output. As shown in FIG. 3, since the denominator M of the clock reduction ratio N / M becomes a repetition cycle of the converted clock signal MCK, the base count value M is used as the upper limit value of n, so that the circuit configuration can be simplified. A long clock signal LCK can be generated from an input clock signal Cin composed of continuous clock pulses.

  The short clock signal SCK output from the short period calculation unit 103 includes clock pulses C1, C4, C7,... Of the input clock signal Cin, and the numbers of these clock pulses are based on the above equation (3). Is calculated. Here, the first term aS is set to 1 and the tolerance dS is set to 3 by the coefficient setting unit 101, and the clock pulse numbers (order) are 1, 4, 7, 10,. It becomes.

  Of course, like the long period calculation unit 102, the clock pulse with the number 1 among the three clock pulses with the clock pulse numbers 1 to 3 in the range including the three clock pulses is actually repeatedly output. Will be. Therefore, the short clock signal SCK can be generated from the input clock signal Cin composed of continuous clock pulses with a simple circuit configuration.

  Next, as shown in FIG. 3, the converted clock signal MCK output from the clock signal converter 104 includes clock pulses C1, C2, C4, C5, C7, C8,... Of the input clock signal Cin. These clock pulses match the clock pulses included in either the long clock signal LCK or the short clock signal SCK. That is, the clock signal conversion unit 104 synthesizes the long clock signal LCK received from the long period calculation unit 102 and the short clock signal SCK received from the short period calculation unit 103 (takes a logical sum), thereby obtaining the input clock. The clock pulse of the signal Cin is appropriately thinned out to generate a conversion clock MCK having a clock reduction ratio of 2/3.

  Further, the clock signal conversion unit 104 generates an output clock signal Cout in which the clock pulse rises (becomes active) at the center position of the long period and the short period. Specifically, the clock signal conversion unit 104 determines whether each clock pulse to be included in the converted clock signal MCK is a clock pulse included in either the long clock signal LCK or the short clock signal SCK. When the clock pulse is included in the long clock signal LCK, a clock pulse having a length of two clocks that rises one clock after the clock pulse falls is generated as the output clock signal Cout. When the clock pulse is included in the short clock signal SCK, a clock pulse of one clock length that rises simultaneously when the clock pulse falls is generated as the output clock signal Cout. With such a configuration, it is possible to easily generate an output clock signal Cout in which a clock pulse rises at the center position of each pixel data D1, D2, D4, D5, D7, D8,... To be included in an output image signal Dout described later. Can do.

  Subsequently, as shown in FIG. 3, the output image signal Dout output from the image signal conversion unit 105 includes pixel data D1, D2, D4, D5, D7, D8,... Of the input image signal Din. It can be seen that these pixel data numbers correspond to the clock pulse numbers included in the converted clock signal MCK. That is, the image signal conversion unit 105 generates the output image signal Dout by thinning out corresponding pixel data from the input image signal Din based on the clock signal MCK received from the clock signal conversion unit 104.

  As described above, the scan conversion circuit 100 calculates the base count value M, which is the denominator when the clock reduction ratio after thinning out the clock pulses is N / M, and the coefficient for calculating the start position of the long period. The output image signal Dout converted into the reduction ratio is output based on setting data that defines the initial term aL and the tolerance dL as the first term and the initial term aS and the tolerance dS as the coefficients for calculating the start position of the short period. To do.

<2. Second Embodiment>
FIG. 4 is a block diagram of a scan conversion circuit according to the second embodiment of the present invention. 4, the scan conversion circuit 200 includes a coefficient setting unit 201 corresponding to the coefficient setting unit 101 illustrated in FIG. 1, a first period calculation unit 202 corresponding to the long period calculation unit 102, Second and third period calculators 203a and 203b corresponding to the short period calculator 103, a clock signal converter 204 corresponding to the clock signal converter 104, and an image signal converter 205 corresponding to the image signal converter 105. With. As will be described later, the second period calculation unit 203a outputs the first short clock signal SCKa, and the third period calculation unit 203b outputs the second short clock signal SCCKb.

  As described above, in the scan conversion circuit 200 according to the present embodiment, the components of the scan conversion circuit 100 according to the first embodiment are substantially the same as the components other than the second and third period calculation units 203a and 203b. Therefore, the description thereof is omitted, and the operation of the scan conversion circuit 200 will be described in detail below by describing the timing of various signals with reference to FIGS.

  FIG. 5 is a diagram for simply explaining the operation of generating the converted clock signal MCK from the input clock signal Cin in the present embodiment. The clock reduction ratio N / M here is set to 7/12. As shown in FIG. 5, when the clock pulse of the input clock signal Cin is C1, C2, C3,..., C12 (C13 and thereafter are omitted in the figure) according to the number (order) ( The clock pulses of the conversion clock signal MCK (not thinned out) are C1, C4, C5, C7, C9, C10, C12,..., And the clock pulses C2, C3, C6, C8, C11,. It has been. In the figure, as in the case of FIG. 2, the correspondence relationship of the clock pulses is indicated by arrows, and the thinned-out is indicated by x. Thus, it can be seen that the ratio of the clock pulse of the converted clock signal MCK to the input clock signal Cin is 7/12 as set.

  Here, as can be seen with reference to FIG. 5 and FIG. 6 described later, in this embodiment, unlike the first embodiment, all clock pulses in the long period are clock pulses included in the long clock signal LCK. The clock pulses in the short period do not all match the clock pulses included in the first or second shot clock signals SCKa and SCCKb.

  In other words, the first period calculation unit 202 here includes a long clock signal including a clock pulse for each predetermined first period, which is a periodic clock pulse interval obtained by thinning out two clock pulses included in the input clock signal Cin. The LCK is generated, and the second period calculation unit 203a generates a first short clock signal SCKa including a clock pulse every predetermined second period that is a periodic clock pulse interval obtained by thinning out three clock pulses. However, it is sufficient for the third period calculation unit 203b to generate the second short clock signal SCKb including a clock pulse for each predetermined third period that is a periodic clock pulse interval obtained by thinning out eleven clock pulses. Included in the resulting conversion clock signal MCK at the start of the long and short periods. Period calculation unit 202,203a clock pulse from the first to the third, or produced by any of 203a is no particular problem.

  Since the above can be similarly applied to the case of the first embodiment, the long period calculation unit 102 according to the first embodiment is a periodic clock obtained by thinning out two clock pulses included in the input clock signal Cin. A long clock signal LCK including a clock pulse is generated every predetermined first period which is a pulse interval, and the short period calculation unit 103 is a periodic clock pulse obtained by thinning out two clock pulses included in the input clock signal Cin. It is sufficient to generate a short clock signal SCK including a clock pulse every predetermined second period which is an interval.

  Note that the long period corresponding to the first period in the first embodiment is set by the tolerance dL, and the short period corresponding to the second period is set by the tolerance dS. As described above, the first start time of the period is set by the first term aL and the first term aS.

  Hereinafter, the operation in the second embodiment will be described in detail with reference to FIG. FIG. 6 is a diagram illustrating a timing chart of various signals in the present embodiment. As shown in FIG. 6, the long clock signal LCK output from the first period calculation unit 202 includes clock pulses C1, C4, C7, C10,... Of the input clock signal Cin. The pulse number is calculated based on the above equation (2). Here, the first term aL is set to 1 and the tolerance dL is set to 3 by the coefficient setting unit 201, and the clock pulse numbers (order) are 1, 4, 7, 10, 13 based on the above equation (2). , ...

  However, here, the base count value M, which is the denominator of the clock reduction ratio N / M, is set to 12, and the clock pulse number within the range including 12 clock pulses is the number among the clock pulses from 1 to 12 , 1, 4, 7, and 10 are repeatedly output. With this configuration, the long clock signal LCK can be generated from the input clock signal Cin composed of continuous clock pulses with a simple circuit configuration. Note that the repetition range here does not necessarily need to have the base count value M as the upper limit. For example, the number is 1 among the clock pulses with clock pulse numbers 1 to 3 within the range including three clock pulses. The configuration may be such that clock pulses are repeatedly output.

Further, the first short clock signal SCKa output from the second period calculation unit 203a includes clock pulses C1, C5, C9,... Of the input clock signal Cin. Calculated based on (4).
an = aS1 + (n−1) × dS1 (4)

  Here, since the first term aS1 is set to 1 and the tolerance dS1 is set to 4 by the coefficient setting unit 201, the number (order) of the clock pulses is 1, 5, 9, 13 based on the above equation (4). , ...

Further, the second short clock signal SCKb output from the third period calculation unit 203b includes clock pulses C12,... Of the input clock signal Cin, and the numbers of these clock pulses are expressed by the following equation (5). Calculated based on
an = aS2 + (n-1) * dS2 (5)

  Here, since the first term aS2 is set to 12 and the tolerance dS2 is set to 12 by the coefficient setting unit 201, the number (order) of the clock pulses is 12, 24, 36,... Based on the above equation (5). It becomes.

  As described above, the present scan conversion circuit includes the second and third period calculation units 203a and 203b in addition to the first period calculation unit 202, so that the first and second series using the arithmetic progression are used. A clock pulse number arrangement as shown in FIG. 6 that cannot be realized by the period calculation unit alone can be realized. For example, when the clock reduction ratio N / M is 11/14, many types of reduction are possible. Conversion corresponding to the ratio can be realized. Further, from this, the number of period calculation units may be four or more.

  Here, as in the first period calculation unit 302, the clock pulses corresponding to the clock pulse numbers within a predetermined range are actually output repeatedly, and thus the continuous clocks with the same simple circuit configuration. The first and second short clock signals SCKa and SCKb can be generated from the input clock signal Cin composed of pulses.

  Next, as shown in FIG. 6, the converted clock signal MCK output from the clock signal converter 204 includes clock pulses C1, C4, C5, C7, C9, C10, C12,... Of the input clock signal Cin. These clock pulses match a clock pulse included in one or more of the long clock signal LCK and the first and second short clock signals SCKa and SCKb. That is, the clock signal conversion unit 204 synthesizes these clock signals (takes a logical sum), so that the clock pulse of the input clock signal Cin is appropriately thinned out so that the clock reduction ratio becomes 7/12. Is generated.

  The clock signal conversion unit 204 is similar to the clock signal conversion unit 104 in the first embodiment, and the output clock signal Cout synchronized with the output image signal Dout so that the clock pulse rises at the center position of the long period and the short period. Is generated. However, unlike the case of the first embodiment, the clock signal conversion unit 204 in this embodiment is such that each clock pulse to be included in the converted clock signal MCK is either the long clock signal LCK or the short clock signal SCK. By determining whether the clock pulse is included, the output clock signal Cout cannot be generated. This is because even if each clock pulse to be included in the converted clock signal MCK is included in the long clock signal LCK, there may be a short period, and vice versa. Therefore, the clock signal conversion unit 204 determines whether the corresponding period is the long period or the short period by calculating the interval between the clock pulses included in the converted clock signal MCK, and outputs the output image based on the determination result. An output clock signal Cout in which a clock pulse rises at the center position of each pixel data D1, D4, D5, D7, D9, D10, D12,... To be included in the signal Dout is generated. Since the configuration of such a clock signal conversion unit 204 is complicated, a scan conversion circuit including a clock signal conversion unit having a simple configuration will be described in the following third embodiment.

  Subsequently, as shown in FIG. 6, the output image signal Dout output from the image signal conversion unit 205 includes pixel data D1, D4, D5, D7, D9, D10, D12,... Of the input image signal Din. These pixel data numbers correspond to the clock pulse numbers included in the converted clock signal MCK. That is, the image signal conversion unit 205 generates the output image signal Dout by thinning out the corresponding pixel data from the input image signal Din based on the clock signal MCK received from the clock signal conversion unit 204.

  As described above, the scan conversion circuit 200 calculates the base count value M, which is a denominator when the clock reduction ratio after thinning out clock pulses is N / M, and the start position in the first period. On the basis of the setting data for determining the initial terms aL and tolerance dL as the coefficients of, and the initial terms aS1 and aS2 and the tolerances dS2 and dS2 as the coefficients for calculating the start positions of the second and third periods, respectively. An output image signal Dout converted into a reduction ratio is output.

<3. Third Embodiment>
As described above, since the configuration of the clock signal conversion unit 204 in the second embodiment is complicated, the scan conversion circuit 300 including the clock signal conversion unit 304 having a simple configuration will be described.

  FIG. 7 is a block diagram of a scan conversion circuit according to the third embodiment of the present invention. As shown in FIG. 7, the scan conversion circuit 300 of the present embodiment is the same as the scan conversion circuit 200 according to the second embodiment shown in FIG. 4 except for the configuration of the clock signal conversion unit 304 and each signal waveform. A coefficient setting unit 301 corresponding to the coefficient setting unit 201 shown in FIG. 4, a first period calculation unit 302 corresponding to the first period calculation unit 202, and a second period calculation unit having the same configuration A second period calculation unit 303a corresponding to 203a, a third period calculation unit 303b corresponding to the third period calculation unit 203b, a clock signal conversion unit 304 corresponding to the clock signal conversion unit 204, and an image signal conversion And an image signal conversion unit 305 corresponding to the unit 205. As will be described later, each signal waveform is different, but the same signal is denoted by the same reference numeral and description thereof is omitted. The description of the same components is also omitted, and the operation of the scan conversion circuit 300 will be described in detail below by describing the timing of various signals with reference to FIGS. 8 and 9.

  FIG. 8 is a diagram for simply explaining the operation of generating the converted clock signal MCK from the input clock signal Cin in the present embodiment. Note that the clock reduction ratio N / M here is set to 7/12 as in the second embodiment. As shown in FIG. 8, when the clock pulse of the input clock signal Cin is C1, C2, C3,..., C12 (C13 and thereafter are omitted in the figure) according to the number (order) ( The clock pulses of the converted clock signal MCK (not thinned out) are C1, C3, C5, C7, C9, C11, C12,..., And the clock pulses C2, C4, C6, C8, C10,. It has been. In the figure, as in the case of FIG. 2, the correspondence relationship of the clock pulses is indicated by arrows, and the thinned-out is indicated by x. Thus, it can be seen that the ratio of the clock pulse of the converted clock signal MCK to the input clock signal Cin is 7/12 as set.

  Here, as can be seen with reference to FIG. 8 and FIG. 9 described later, in this embodiment, as in the case of the first embodiment, all the clock pulses in the long period match the clock pulses included in the long clock signal LCK. In addition, all the clock pulses in the short period coincide with the clock pulses included in the first or second shot clock signals SCKa and SCKb. However, in this embodiment, the short period is slightly different from the case of the first embodiment. A part of the clock pulse in FIG. 4 further matches the clock pulse included in the long clock signal LCK. As described above, when each clock pulse to be included in the converted clock signal MCK is included in one of the first and second short clock signals SCKa and SCCKb, a short period is always required, and in other cases, a long period is always required. Therefore, in this embodiment, as in the case of the first embodiment, it is determined by determining whether each clock pulse to be included in the converted clock signal MCK is a clock pulse included in the short clock signal SCK. The output clock signal Cout can be generated.

  The operation in the third embodiment will be described in detail below with reference to FIG. FIG. 9 is a diagram illustrating a timing chart of various signals in the present embodiment. As shown in FIG. 9, the long clock signal LCK output from the first period calculation unit 302 includes clock pulses C1, C3, C5, C7, C9, C11,... Of the input clock signal Cin. These clock pulse numbers are calculated based on the above equation (2). Here, the first term aL is set to 1 and the tolerance dL is set to 2 by the coefficient setting unit 301, and the clock pulse numbers (order) are 1, 3, 5, 7, 9 based on the above equation (2). , 11, 13,...

  However, here, the base count value M, which is the denominator of the clock reduction ratio N / M, is set to 12, and the clock pulse number within the range including 12 clock pulses is the number among the clock pulses from 1 to 12 , 1, 3, 5, 7, 9, and 11 are repeatedly output. With this configuration, the long clock signal LCK can be generated from the input clock signal Cin composed of continuous clock pulses with a simple circuit configuration.

  The first short clock signal SCKa output from the second period calculation unit 303a includes the clock pulses C11,... Of the input clock signal Cin, and the numbers of these clock pulses are expressed by the above equation (4). Calculated based on Here, since the first term aS1 is set to 11 and the tolerance dS1 is set to 12 by the coefficient setting unit 301, the number (order) of the clock pulses is 11, 23, 35,... Based on the above equation (4). It becomes.

  Further, the second short clock signal SCKb output from the third period calculation unit 303b includes clock pulses C12,... Of the input clock signal Cin, and the numbers of these clock pulses are expressed by the above equation (5). Calculated based on Here, since the first term aS2 is set to 12 and the tolerance dS2 is set to 12 by the coefficient setting unit 301, the number (order) of the clock pulses is 12, 24, 36,... Based on the above equation (5). It becomes.

  Here, as in the first period calculation unit 302, the clock pulses corresponding to the clock pulse numbers within a predetermined range are actually output repeatedly, and thus the continuous clocks with the same simple circuit configuration. The first and second short clock signals SCKa and SCKb can be generated from the input clock signal Cin composed of pulses.

  Next, as shown in FIG. 9, the converted clock signal MCK output from the clock signal converter 304 includes clock pulses C1, C3, C5, C7, C9, C11, C12,... Of the input clock signal Cin. These clock pulses match a clock pulse included in one or more of the long clock signal LCK and the first and second short clock signals SCKa and SCKb. That is, the clock signal conversion unit 304 synthesizes these clock signals (takes a logical sum) so that the clock pulses of the input clock signal Cin are appropriately thinned out so that the clock reduction ratio becomes 7/12. Is generated.

  Here, as in the case of the first embodiment, the clock signal conversion unit 304 generates the output clock signal Cout in which the clock pulse rises (becomes active) at the center position of the long period and the short period. Specifically, the clock signal conversion unit 304 determines whether or not each clock pulse to be included in the converted clock signal MCK is a clock pulse included in the short clock signal SCK. When the clock pulse is included in the short clock signal SCK, a one-clock-long clock pulse that rises simultaneously when the clock pulse falls is generated as the output clock signal Cout. In other cases (that is, when the clock pulse is not included in the short clock signal SCK), the output clock signal Cout is a two-clock long clock pulse that rises one clock after the clock pulse falls. Generate. With such a configuration, an output clock signal Cout in which a clock pulse rises easily at the center position of each pixel data D1, D3, D5, D7, D9, D11, D12,... To be included in an output image signal Dout described later is easily generated. can do.

  9, the output image signal Dout output from the image signal conversion unit 305 includes pixel data D1, D3, D5, D7, D9, D11, D12,... Of the input image signal Din. These pixel data numbers correspond to the clock pulse numbers included in the converted clock signal MCK. That is, the image signal conversion unit 305 generates the output image signal Dout by thinning out the corresponding pixel data from the input image signal Din based on the clock signal MCK received from the clock signal conversion unit 304.

  As described above, the scan conversion circuit 300 calculates the base count value M, which is a denominator when the clock reduction ratio after thinning out clock pulses is N / M, and the start position in the first period. On the basis of the setting data for determining the initial terms aL and tolerance dL as the coefficients of, and the initial terms aS1 and aS2 and the tolerances dS2 and dS2 as the coefficients for calculating the start positions of the second and third periods, respectively. An output image signal Dout converted into a reduction ratio is output.

<4. Effect of each embodiment>
In the first to third embodiments, the base count value M and coefficients for calculating the start positions of the long period and the short period (or the first to third periods) (general terms of the arithmetic progression) are calculated. It is possible to convert an input image signal having various formats into an output image signal corresponding to a display device having various numbers of pixels only by setting an initial term a and a tolerance d) to be obtained. It is possible to provide a scan conversion circuit with a small number of setting data and a small circuit scale.

  In the second embodiment, by providing the second and third period calculation units 203a and 203b, the number arrangement of clock pulses included in the output clock signal Cout (or the converted clock signal MCK) is diversified and various. It is possible to provide a scan conversion circuit that can cope with a small clock reduction ratio.

  Furthermore, in the first and third embodiments, by appropriately setting the setting data given to the coefficient setting unit, each clock pulse to be included in the converted clock signal MCK is short-circuited in the clock signal conversion units 104 and 304. A simple configuration for determining whether or not a clock pulse is included in the clock signal SCK, or a clock in which each clock pulse to be included in the converted clock signal MCK is included in either the long clock signal LCK or the short clock signal SCK. A simple configuration for determining whether it is a pulse, for example, a complicated configuration for determining whether a corresponding period is a long period or a short period by calculating an interval of clock pulses included in the converted clock signal MCK. Each image to be included in the output image signal Dout without taking The output clock signal Cout the clock pulse rises at the center position of the data can be easily generated.

<5. Modified example of each embodiment>
In each of the above embodiments, the long clock signal LCK is generated by the long period calculation unit 102 and the first period calculation units 202 and 302. However, any signal indicating the start position of the long period may be used as the clock signal. For example, numerical data may be used. The same applies to the short period calculation unit 103 and the second and third period calculation units 203a, 203b, 303a, and 303b.

  In each of the embodiments described above, the coefficient setting units 101, 201, and 301 are used to obtain the order indicating the start positions of the long period and the short period (or the first to third periods) from the general terms an of the arithmetic progression, respectively. The first term a and the tolerance d 1 are defined. However, a coefficient or data for determining the order indicating the start position of the period may be determined by other mathematical formulas or tables.

  In each of the above embodiments, in the long period calculation unit 102, the first period calculation units 202 and 302, the short period calculation unit 103, or the second and third period calculation units 203a, 203b, 303a, and 303b, an arithmetic sequence In order to calculate the start position of the long period or the short period (or the period from the first to the third period) by repeatedly increasing n in the general term from 1 to M one by one, the coefficient setting units 101 and 201 , 301, the base count value M is determined. However, the base count value M is not necessarily determined. For example, an appropriate number of repetitions in place of the base count value M may be preset or calculated. .

  In the first or third embodiment, the output clock signal Cout is generated so that the clock pulse rises at the center position of each pixel data to be included in the output image signal Dout. Since it is a clock signal given to the display device together with the image signal Dout and used, it may be a clock signal synchronized with the pixel data included in the output image signal Dout, and at an appropriate predetermined position according to the specifications of the display device. It only needs to include a rising clock pulse.

1 is a block diagram showing a configuration of a scan conversion circuit according to a first embodiment of the present invention. It is a figure for demonstrating simply the operation | movement which produces | generates a conversion clock signal from an input clock signal in the said embodiment. It is a figure which shows the timing chart of the various signals in the said embodiment. It is a block diagram which shows the structure of the scan conversion circuit which concerns on the 2nd Embodiment of this invention. It is a figure for demonstrating simply the operation | movement which produces | generates a conversion clock signal from an input clock signal in the said embodiment. It is a figure which shows the timing chart of the various signals in the said embodiment. It is a block diagram which shows the structure of the scan conversion circuit which concerns on the 3rd Embodiment of this invention. It is a figure for demonstrating simply the operation | movement which produces | generates a conversion clock signal from an input clock signal in the said embodiment. It is a figure which shows the timing chart of the various signals in the said embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100,200,300 ... Scan conversion circuit 101,201,301 ... Coefficient setting part 102 ... Long period calculation part 103 ... Short period calculation part 104,204,304 ... Clock signal conversion part 105,205,305 ... Image signal conversion part 202, 302 ... 1st period calculation part 203a, 303a ... 2nd period calculation part 203b, 303b ... 3rd period calculation part Cin ... Input clock signal Cout ... Output clock signal LCK ... Long clock signal SCK ... Short clock signal MCK ... Conversion clock signal Din ... Input image signal Dout ... Output image signal

Claims (7)

The input image signal given from the outside is set to N / M of the number of pixels in the horizontal direction in the input image signal so that it is equal to the number of display pixels in the horizontal direction in the image to be displayed on the display device (N and M are natural numbers). A scan conversion circuit for converting into an output image signal having a horizontal number of pixels that is doubled,
Based on predetermined setting data given from outside, different predetermined first and second periods, which are periodic clock pulse intervals obtained by thinning out one or more clock pulses included in an input clock signal given from outside, are set. Setting means for determining first and second period setting values for
First period calculating means for calculating a start position of the first period in the input clock signal based on the first period set value and outputting the calculated start position as a first period start signal;
Second period calculating means for calculating a start position of the second period in the input clock signal based on the second period setting value and outputting the calculated start position as a second period start signal;
Clock signal conversion means for outputting a converted clock signal having a clock pulse number that is N / M times the number of clock pulses in the input clock signal based on the first and second period start signals;
A scan conversion circuit comprising: image signal conversion means for converting the input image signal into the output image signal by thinning out pixel data included in the input image signal based on the converted clock signal. The first period calculation means outputs a clock pulse of the input clock signal corresponding to a start position of the first period as the first period start signal,
The second period calculation means outputs a clock pulse of the input clock signal corresponding to a start position of the second period as the second period start signal,
The said clock signal conversion means produces | generates and outputs the said conversion clock signal by synthesize | combining the said 1st period start signal and the said 2nd period start signal, The output of Claim 1 characterized by the above-mentioned. Scan conversion circuit.   The clock signal converting means generates a clock pulse that rises or falls at a predetermined time corresponding to each of the pixel data in synchronization with the pixel data included in the output image signal based on the first and second period start signals. 3. The scan conversion circuit according to claim 1, wherein an output clock signal including the output clock signal is output.   The setting means determines the order of the clock pulses included in the input clock signal based on the setting data and indicating the start position of the first period in the input clock signal. (N is an integer equal to or greater than 0), the initial term aL and the tolerance dL in the equation an = aL + (n−1) × dL are defined as the first period setting values, and the second period The first term aS and the tolerance dS in the equation an = aS + (n−1) × dS are defined as the first period set value when the order indicating the start position is expressed by the general term an in the arithmetic progression. The scan conversion circuit according to any one of claims 1 to 3. The setting means determines the natural number M based on the setting data,
The first period calculation means repeatedly increases n in the general term of the arithmetic progression determined by the first term aL and the tolerance dL, which are the first period setting values, by 1 repeatedly from 1 to M. Calculating the start position of the first period;
The second period calculation means repeatedly increases n in the general term of the arithmetic sequence determined by the first term aS and the tolerance dS, which are the second period setting values, by 1 repeatedly from 1 to M. The scan conversion circuit according to claim 4, wherein a start position of the second period is calculated. A third period calculating means for outputting a predetermined third period start signal;
The setting means has the first and second clock pulse intervals that are periodic clock pulse intervals obtained by thinning out one or more clock pulses included in an input clock signal supplied from the outside based on predetermined setting data supplied from the outside. A third period setting value for setting a third period different from the period is determined,
The third period calculating means calculates a start position of the third period in the input clock signal based on the third period set value, and uses the calculated start position as the third period start signal. Output,
The clock signal conversion means outputs a converted clock signal having a clock pulse number that is N / M times the number of clock pulses in the input clock signal, based on the first to third period start signals. The scan conversion circuit according to claim 5. The input image signal given from the outside is set to N / M of the number of pixels in the horizontal direction in the input image signal so that it is equal to the number of display pixels in the horizontal direction in the image to be displayed on the display device (N and M are natural numbers). A scan conversion method for converting into an output image signal having a horizontal number of pixels that is doubled,
Based on predetermined setting data given from outside, different predetermined first and second periods, which are periodic clock pulse intervals obtained by thinning out one or more clock pulses included in an input clock signal given from outside, are set. A setting step for determining first and second period setting values for
A first period calculating step of calculating a start position of the first period in the input clock signal based on the first period set value and outputting the calculated start position as a first period start signal;
A second period calculating step of calculating a start position of the second period in the input clock signal based on the second period setting value and outputting the calculated start position as a second period start signal;
A clock signal converting step of outputting a converted clock signal having a clock pulse number that is N / M times the number of clock pulses in the input clock signal based on the first and second period start signals;
An image signal conversion step of converting the input image signal into the output image signal by thinning out pixel data included in the input image signal based on the converted clock signal.

Images