JP2006030389A - Information processor, system, display method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an "information processor", a "system", a "display method", and a "program" that can smoothly display an image even when an external synchronization mode is not used. <P>SOLUTION: A display device 3 has a capture circuit 31 which captures input completion information on an externally inputted video signal, a timing determination part 32 which generates a correction value for adjusting the number of display lines of a display image based upon display timing information of the display image signal including a 1st image signal and a 2nd image signal which is put together with the 1st image signal, a display timing generating circuit 33 which generates display timing information of the display image signal based upon the correction value generated by the timing determination part 32, a memory 35 which stores the display image signal, and a display output circuit 34 which reads the display image signal out of the memory 35. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an information processing apparatus, system, display method, and program.

  Conventionally, a display device for displaying a video signal input from the outside such as a TV tuner has been proposed. In such a display device, the synchronization signal is separated from the video signal input from the TV tuner, and the timing of the video signal is adjusted according to the synchronization signal. Also, an apparatus described in Patent Document 1 has been proposed as a general prior art for adjusting the display timing of a video signal.

  Since the apparatus described in Patent Document 1 cannot operate the LCD panel at the CRT timing, the video signal sent from the personal computer is once stored in the frame buffer memory, and is read out and displayed on the LCD panel. Thus, the LCD panel is operated at the display timing of the CRT.

JP-A-5-11720

  However, when a video signal is input from, for example, a TV tuner, the HSYNC signal (horizontal synchronization signal) and the VSYNC signal (vertical synchronization signal) may not be accurately detected if radio wave reception is incomplete. When the display device displays the display image signal at the display timing synchronized with the HSYNC signal and VSYNC signal of the video input source using the external synchronization mode, the display of the menu or the like synthesized with the video signal is also disturbed. .

  Further, when the display device displays the display image signal by combining the image signal such as the menu with the video signal without using the external synchronization mode, the display timing on the display device side is not disturbed. Since the display timing and the input timing of the video input source are asynchronous, the display image gradually shifts. As a result, there are problems that the display frame of the video input screen is dropped or the same input image is displayed twice, and the display image cannot be displayed smoothly. In addition, the apparatus described in Patent Document 1 does not take into account the case where radio wave reception is incomplete.

  Therefore, the present invention has been made to solve these problems, and provides an information processing apparatus, system, display method, and program capable of smoothly displaying a display image even when the external synchronization mode is not used. For the purpose.

  In order to solve the above-described problem, the present invention provides an acquisition unit that acquires the capture completion information of the first image signal input from the outside, the capture completion information of the first image signal, the first image signal, and the And a generation unit that generates a correction value for adjusting the number of display lines of the display image based on display timing information of the display image signal including the second image signal to be combined with the first image signal. This is an information processing apparatus.

  According to the present invention, the first image is generated by generating a correction value for adjusting the number of display lines of the display image based on the first image signal capture completion information and the display timing information of the display image signal. The signal capture timing and the display image signal output timing can be synchronized. Therefore, for example, the display frame of the video input image is not dropped or the same input image is not displayed twice, and the display image is displayed smoothly even when the external synchronization mode is not used.

  In the above-described configuration, the present invention further includes a timing information generation unit that generates display timing information of the display image signal based on the correction value generated by the generation unit. According to the present invention, the display timing information is generated based on the correction value considering the first image signal capture completion information and the display timing information of the display image signal, thereby obtaining the first image signal capture timing, The output timing of the display image signal can be synchronized.

  The present invention is characterized in that, in the above-described configuration, a memory for storing the display image signal is further included.

  According to the present invention, in the above configuration, a timing information generation unit that generates display timing information of the display image signal based on the correction value generated by the generation unit, a memory that stores the display image signal, And a reading unit that reads out the display image signal from the memory based on the display timing information. According to the present invention, a display image signal in which the number of display lines is increased or decreased from the reference value is generated based on display timing information that takes into account the first image signal capture completion information and the display timing information of the display image signal. The first image signal capture timing and the display image signal output timing can be synchronized.

  In the above configuration, the present invention is characterized in that the first image signal capture completion information is a vertical synchronization signal of the first image signal. According to the present invention, a correction value for adjusting the number of display lines of a display image can be generated based on the vertical synchronization signal of the first image signal and the display timing information of the display image signal.

  According to the present invention, in the above configuration, the number of display lines is the number of display lines in a non-display area in the display image signal. According to the present invention, since the number of display lines in the non-display area in the display image signal is adjusted, the display image displayed on the display device is not affected.

  The present invention is a system including a tuner and an information processing device that synthesizes and outputs a second image signal to the first image signal input from the tuner, and the information processing device includes the information processing device. It is a configured system. ADVANTAGE OF THE INVENTION According to this invention, the system which synchronized the taking-in timing of the 1st image signal input from the tuner, and the output timing of the display image signal can be provided. Therefore, for example, the display frame of the video input image is not dropped or the same input image is not displayed twice, and the display image is displayed smoothly.

  The present invention includes a step of acquiring capture completion information of a first image signal input from the outside, a capture completion information of the first image signal, and the first image signal and the first image signal to be combined. And generating a correction value for adjusting the number of display lines of the display image based on display timing information of the display image signal including two image signals.

  According to the present invention, the number of display lines is generated by generating a correction value for adjusting the number of display lines of the display image based on the first image signal capture completion information and the display timing information of the display image signal. The display image signal with increased or decreased can be generated, and the capture timing of the first image signal and the output timing of the display image signal can be synchronized. Therefore, for example, the display frame of the video input image is not dropped or the same input image is not displayed twice, and the display image is displayed smoothly.

  The present invention is characterized in that, in the above configuration, the method further includes generating display timing information of the display image signal based on the correction value. According to the present invention, the number of display lines of the display image is adjusted by generating the display timing information based on the correction value considering the capture completion information of the first image signal and the display timing information of the display image signal. can do.

  According to the present invention, a step of receiving external image input completion information of a first image signal, a second image signal synthesized with the first image signal and the first image signal based on the acquisition completion information of the first image signal. A program for causing a computer to execute a step of generating a correction value for adjusting the number of display lines of a display image including an image signal. According to the present invention, the first image is generated by generating a correction value for adjusting the number of display lines of the display image based on the first image signal capture completion information and the display timing information of the display image signal. The signal capture timing and the display image signal output timing can be synchronized. Therefore, for example, the display frame of the video input image is not dropped or the same input image is not displayed twice, and the display image is displayed smoothly.

  According to the present invention, it is possible to provide an information processing apparatus, system, display method, and program capable of smoothly displaying a display image even when the external synchronization mode is not used.

  Hereinafter, the best mode for carrying out the present invention will be described.

  FIG. 1 is a diagram illustrating an overview of a system 1 according to the present embodiment. As shown in FIG. 1, the system 1 includes a TV tuner 2 and a display device 3. The TV tuner 2 includes an antenna or the like and takes in a video signal. The TV tuner 2 sends the video signal to the display device 3 at 59.9 Hz, for example. The display device 3 combines a video signal from the TV tuner 2 with an image signal such as a menu and displays a display image on the display.

  FIG. 2 is a block diagram of the display device 3 according to the present embodiment. As illustrated in FIG. 2, the display device 3 includes a capture circuit 31, a timing determination unit 32, a display timing generation circuit 33, a display output circuit 34, and a memory 35. The capture circuit 31 captures the video signal (first image signal) from the TV tuner 2, sends this video signal to the memory 35, and captures capture completion information (VSYNC signal: vertical synchronization signal) for one frame of the video signal. The data is sent to the timing determination unit 32. Here, the capture circuit 31 sends the VSYNC signal to the timing determination unit 32 at an interval of 16.7 ms (59.9 Hz), for example. The memory 35 stores a display image signal including a captured video signal (first image signal) input from the outside and an image signal (second image signal) such as a menu to be combined with the video signal. The menu is, for example, a menu for setting a destination in the navigation device.

  The timing determination unit 32 generates a correction value for adjusting the number of display lines of the display image based on the video signal capture completion information from the capture circuit 31 and the display timing information of the display image signal. Here, the display timing information of the display image signal includes the time of the VSYNC signal (vertical synchronization signal) of the display output.

  The timing determination unit 32 generates a correction value that increases the number of display lines of the display image when the display timing of the display image signal is advanced with respect to the video signal capture timing. Conversely, when the display timing of the display image signal is delayed with respect to the video signal capture timing, the timing determination unit 32 generates a correction value that decreases the number of display lines of the display image. The timing determination unit 32 generates, for example, ternary values when the increase amount of the display line does not affect the display screen, and the increase amount, the decrease amount, and nothing. By these three-valued output frequencies, subtle timing shifts that are less than the shift for one display line are corrected. The number of display lines of the display image may be the number of lines in the display area or the number of lines in the non-display area.

  The display timing generation circuit 33 generates display timing information of the display image signal based on the correction value from the timing determination unit 32. The display output circuit 34 generates and generates a display image signal in which the number of display lines is increased or decreased from the reference value based on the display timing information generated by the display timing generation circuit 33 and the display image signal read from the memory 35. The displayed display image signal is output to the display. Thereby, the capture timing of the first image signal and the output timing of the display image signal can be synchronized.

  Next, the operation of the display device 3 will be described. FIG. 3 is an operation flowchart of the display device 3. In step S 1, the video signal is input from the TV tuner 2 to the capture circuit 31. In step S <b> 2, the capture circuit 31 stores the video signal in the memory 35. In step S3, the timing determination unit 32 generates a display timing correction value based on the video signal capture completion information and the display timing information of the display image signal. In step S4, the display timing generation circuit 33 generates display timing information based on the display timing correction value generated by the timing determination unit 32.

  In step S5, the display output circuit 34 generates a display image signal in which the number of display lines is increased or decreased from the reference value based on the display timing information generated by the display timing generation circuit 33, and outputs the display image signal to the display. As a result, the video signal capture completion timing and the display image signal output timing can be synchronized.

  Next, an operation when generating a correction value for adjusting the number of display lines of the display image will be described. FIG. 4 is an operation flowchart for generating a correction value for adjusting the number of display lines of a display image. In step S31, the timing determination unit 32 compares the capture completion information of the video signal and the display timing information of the display image signal. If both are the same, the number of display lines of the display image is changed from the reference value in step S32. A correction value that does not occur is generated. In step S32, the timing determination unit 32 compares the video signal capture completion information with the display timing information of the display image signal, and the display timing of the display image signal is advanced with respect to the video signal capture timing. In step S34, a correction value is generated so that the number of display lines of the display image increases by one line.

  In step S35, the timing determination unit 32 compares the video signal capture completion information with the display timing information of the display image signal, and the display timing of the display image signal is delayed with respect to the video signal capture timing. In step S36, a correction value is generated so that the number of display lines of the display image decreases by one line. Thus, the video signal capture completion timing and the display image signal output timing can be synchronized while adjusting the number of display lines of the display screen signal.

  Next, the display timing of the display device 3 will be described. 5A is a diagram showing capture timing based on capture completion information of the capture circuit 31, and FIG. 5B is a diagram illustrating display timing based on display timing information generated by the display timing generation circuit 33. FIG.

  At the time of (1), as a result of comparing the video signal capture completion information and the display image signal display timing information, the timing determination unit 32 matches the video signal capture timing and the display image signal display timing. The display timing generation circuit 33 generates display timing information based on the display timing correction value generated by the timing determination unit 32, and the display output circuit 34 displays the display timing correction value. Based on the display timing information generated by the timing generation circuit 33, a display image signal is generated by increasing or decreasing the number of display lines from the reference value. At the time (2), the video signal capturing completion timing and the display timing are shifted.

  At the time of (2), as a result of comparing the video signal capture completion information with the display timing information of the display image signal, the timing determination unit 32 has advanced the display timing of the display image signal with respect to the timing of the video signal. The display timing signal is generated based on the correction value generated by the timing determination unit 32. The correction value is generated to increase the number of display lines in the non-display area of the display image signal. The display output circuit 34 generates a display image signal in which the number of display lines is increased from the reference value based on the display timing information generated by the display timing generation circuit 33, and outputs the display image signal to the display. As a result, the display timing of the display image signal can be delayed. Therefore, at the time of (3), the video signal capture completion timing and the display timing of the display image signal approach each other.

  Further, the timing determination unit 32 compares the video signal capture completion information with the display image signal timing information as in the time point (4). As a result, the display timing of the display screen is higher than the video signal capture timing. If it is delayed, a display timing correction value corresponding to this is generated, and the display timing generation circuit 33 generates display timing information based on the display timing correction value generated by the timing determination unit 32 and displays the display timing information. The output circuit 34 generates a display image signal in which the number of display lines is reduced from the reference value based on the display timing information generated by the display timing generation circuit 33, and outputs the generated display image signal to the display. Thereby, as shown in time (5), the display timing of a display image can be advanced.

  In this way, the average display timing is made to coincide with the video input timing by dynamically increasing or decreasing the number of display lines of the display image. Further, by setting the range of increase / decrease within a range where the display of the display device 3 is not disturbed, it is possible to realize a display that is not affected by the disturbance of the video input.

  As described above, according to this embodiment, the correction value for adjusting the number of display lines of the display image is generated based on the video signal capture completion information and the display timing information of the display image signal, thereby By increasing or decreasing the number of display lines, the video signal capture timing and the display image signal output timing can be synchronized. As a result, the display frame is not dropped or the same input image is not displayed twice, and the display is smoothed. Moreover, since the timing determination unit 32 is realized by software, additional hardware is not used, so that the cost can be kept low.

  The display device 3 is realized using, for example, a central processing unit (CPU), a read only memory (ROM), a random access memory (RAM), and the like, and the program is stored in a hard disk device, a CD-ROM, a DVD, or a flexible disk. The function of the timing determination unit 32 and the steps of the display method according to the present invention are realized by installing the program from a portable storage medium or the like or downloading the program from a communication circuit and executing the program by the CPU. A step of receiving a first image signal capture completion information input from the outside by a predetermined program; a second image signal to be combined with the first image signal and the first image signal based on the first image signal capture completion information; The function of the timing determination unit 32 can be realized by causing the CPU to execute a step of generating a correction value for adjusting the number of display lines of the display image including the. Note that the function of the timing determination unit 32 may be realized by hardware instead of software.

  In this embodiment, a video signal input from the TV tuner 2 is described as an example of an image input from the outside. However, the present invention is not limited to this, and for example, from a digital camera or a personal computer. It may be an image signal sent. The image input from the outside may be either a moving image or a still image. The display device 3 is incorporated in, for example, a personal computer or a navigation device.

  The capture circuit 31, the timing determination unit 32, the display timing generation circuit 33, the display output circuit 34, the TV tuner 2, and the display device 3 are the acquisition unit, generation unit, timing information generation unit, readout unit, and tuner in the claims. , Corresponding to each information processing apparatus.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

It is a figure which shows the outline | summary of the system 1 which concerns on a present Example. It is a block diagram of the display apparatus 3 which concerns on a present Example. 4 is an operation flowchart of the display device 3. It is an operation | movement flowchart at the time of producing | generating the correction value for adjusting the display line number of a display image. (A) is a figure which shows the capture timing based on the capture completion information of the capture circuit 31, (b) is a figure which shows the display timing based on the display timing information which the display timing generation circuit 33 produces | generates.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 System 2 TV tuner 3 Display apparatus 31 Capture circuit 32 Timing determination part 33 Display timing generation circuit 34 Display output circuit 35 Memory

Claims (10)

An acquisition unit that acquires capture completion information of the first image signal input from the outside;
The display line of the display image is based on the capture completion information of the first image signal and display timing information of the display image signal including the first image signal and the second image signal combined with the first image signal. An information processing apparatus comprising: a generation unit that generates a correction value for adjusting the number. The information processing apparatus according to claim 1, further comprising a timing information generation unit that generates display timing information of the display image signal based on the correction value generated by the generation unit. . The information processing apparatus according to claim 1, further comprising a memory for storing the display image signal. The information processing apparatus further includes a timing information generation unit that generates display timing information of the display image signal based on the correction value generated by the generation unit;
A memory for storing the display image signal;
The information processing apparatus according to claim 1, further comprising: a reading unit that reads the display image signal from the memory based on the display timing information. 5. The information processing apparatus according to claim 1, wherein the capture completion information of the first image signal is a vertical synchronization signal of the first image signal. 6. The information processing apparatus according to claim 1, wherein the number of display lines is the number of display lines in a non-display area in the display image signal. A system comprising: a tuner; and an information processing apparatus that synthesizes and outputs a second image signal to the first image signal input from the tuner,
The said information processing apparatus is a system which is an information processing apparatus as described in any one of Claims 1-6. Obtaining capture completion information of the first image signal input from the outside;
Display of the display image based on the capture completion information of the first image signal and display timing information of a display image signal including the first image signal and the second image signal combined with the first image signal And a step of generating a correction value for adjusting the number of lines. 9. The display method according to claim 8, further comprising the step of generating display timing information of the display image signal based on the correction value. Receiving the first image signal input completion information input from the outside;
Based on the capture completion information of the first image signal, a correction value for adjusting the number of display lines of the display image including the first image signal and the second image signal to be combined with the first image signal is generated. A program that causes a computer to execute steps.

Images