JP2008160410A - Transmitter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem: a conventional technique in which an error compensation quantity is controlled with a fixed step is not suitable for a broadcast transmitter requiring detailed error compensation quantity control, in a transmitter for broadcasting because the tremendous number of steps are required. <P>SOLUTION: In a loopback signal, the sum of symmetrical sub-carriers away from each other by a first frequency and the sum of symmetrical sub-carriers away from each other by a second frequency are calculated. Both the sum signals are each divided into a real part and an imaginary part, both the real parts are used to estimate two components of amplitude-phase error and both the imaginary parts are used to estimate the two residual components of the amplitude-phase error. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a quadrature error compensation technique for a quadrature modulator.

In a wireless communication system, a quadrature modulator used to modulate a baseband signal and convert it to an RF (Radio Frequency) signal includes a quadrature error (amplitude error and phase error). As a method, a method of estimating and compensating for an error using an input and an output of a quadrature modulator has been proposed (see, for example, Patent Document 1). By doing so, it was possible to perform communication while maintaining a certain modulation accuracy.
Japanese Patent No. 3037213

  However, since the technique described in Patent Document 1 controls the error compensation amount in a fixed step, the number of steps becomes enormous when fine error compensation amount control is required as in a broadcasting transmission apparatus. Not suitable.

  The present invention has been made to solve the above-described problems of the prior art, and an object thereof is to provide a quadrature error compensation method for a quadrature modulator suitable for fine compensation.

  According to the present invention, among the components included in the signal to be compensated, the first frequency component separated by + k1 from the center frequency of the signal to be compensated and the second frequency component separated by -k1 are to be compensated. A first frequency component extraction unit for extracting a third frequency component separated by + k2 from the center frequency of the signal and a fourth frequency component separated by -k2, and a real part of each of the first to fourth frequency components A matrix generation unit that generates a matrix from the imaginary part and a quadrature modulation signal generated by modulating the orthogonality-compensated signal by the orthogonal modulator, and the first frequency separated from the center frequency of the loopback signal by the loopback signal. A second frequency component extraction unit that extracts a frequency component of 5 and a sixth frequency component separated by k2, a real part and an imaginary part of the fifth frequency component, and a sixth real part and an imaginary part. including A vector generation unit that generates a spectrum, and a calculation unit that calculates a compensation value for compensating the signal to be compensated from the matrix and the vector so as to cancel the orthogonal error generated in the orthogonal modulation unit. It is characterized by.

  In the present invention, the first frequency component separated by + k1 from the center frequency of the signal to be compensated and the second frequency component separated by -k1 among the components included in the signal to be compensated are compensated. A first frequency component extraction unit for extracting a third frequency component separated by + k2 from the center frequency of the power signal and a fourth frequency component separated by -k2, and the first frequency component and the second frequency A first adder that calculates a first sum that is a sum of components and a second sum that is the sum of the third frequency component and the fourth frequency component; and A first real part that is the real part of the sum and a first imaginary part that is the imaginary part; a second real part that is the real part of the second sum; and a second imaginary part that is the imaginary part; A first separation unit that extracts the first real part, the first imaginary part, the second real part, and the A matrix generation unit that generates a matrix including two imaginary parts, and the center frequency of the loopback signal obtained by looping back the orthogonal modulation signal generated by the orthogonal modulator modulating the orthogonality compensated signal; The fifth frequency component, the sixth frequency component separated by −k1, the seventh frequency component separated by + k2 (where | k1 | ≠ | k2 |) from the center frequency of the loopback signal, and the −k2 A second frequency component extraction unit for extracting the eighth frequency component that is distant, a third sum that is the sum of the fifth frequency component and the sixth frequency component, and the seventh frequency A second summing unit that calculates a fourth sum that is a sum of a component and the eighth frequency component, a third real part that is a real part of the third sum, and a first part that is an imaginary part The fourth imaginary part and the fourth real part of the fourth sum A second separator for extracting a real part and a fourth imaginary part which is an imaginary part; a real vector generator for generating a real vector including the third real part and the fourth real part; Generating an imaginary vector generating unit that generates an imaginary vector including the third imaginary part and the fourth imaginary part; and generating a signal to be compensated so as to cancel an orthogonal error generated in the orthogonal modulation unit A first arithmetic unit for calculating a first compensation value from the matrix and the real vector, and a second compensation value among the compensation values from the matrix and the imaginary vector. And a second arithmetic unit.

  According to the present invention, the quadrature error compensation of the quadrature modulator can be performed finely.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram of transmitting apparatus 100 according to the present embodiment.

  The configuration of the transmission device 100 will be described separately for the analog unit 200 and the digital unit 400.

(Configuration of analog unit 200)
The analog unit 200 includes a DAC (Digital-Analog Converter) 201, a BB (Base Band) filter 203, a quadrature modulator 205, a PA (Power Amplifier: power amplifier) 208, an antenna 209, and switches 210 and 211. , Quadrature demodulator 213, BB filter 215, ADC (Analog-Digital Converter) 217, LO (Local signal Oscillator) 219, down converter 220, IF (Intermediate Frequency) filter 222, ADC2 24 Is provided.

The digital quadrature baseband signals I ₀ and Q ₀ are processed by the digital unit 400 and supplied to the DAC 201 as I ₂ and Q ₂ , respectively.

The DAC 201 converts I ₂ and Q ₂ into analog signals and supplies them to the quadrature modulator 205 through the BB filter 203.

The quadrature modulator 205 modulates I ₂ and Q ₂ converted into analog signals to an RF frequency using a signal LO 0 output from the LO 219.

The PA 208 amplifies the addition signal with I ₃ and Q ₃ that are the outputs of the quadrature modulator 205, and outputs an amplified modulated signal.

  The antenna 209 emits an amplified modulated signal.

  The switch 210 connects / disconnects the output of the quadrature modulator 205 and the down converter 220.

  The switch 211 connects / disconnects the output of the PA 208 and the quadrature demodulator 213.

The quadrature demodulator 213 receives the amplified modulated signal that is the output of the PA 208 via the switch 211. The quadrature demodulator 213 outputs signals I ₄ and Q _{4 obtained} by demodulating the amplified modulated signal using LO 0.

The ADC 217 converts I ₄ and Q ₄ that have passed through the BB filter 215 into digital signals and supplies them to the digital unit 400.

The downconverter 220 receives the output of the quadrature modulator 205 via the switch 210. The down-converter 220 outputs signals I ₆ and Q ₆ obtained by down-converting the output of the quadrature modulator 205 to the IF frequency using LO0.

The ADC 224 converts I ₆ and Q ₆ that have passed through the IF filter 222 into digital signals and supplies them to the digital unit 400.

In order to avoid the need to use a high-cost configuration with a high sampling rate as the ADC 224, the center frequencies (IF frequencies) of the signals I ₆ and Q ₆ are smaller than the sampling rate of the ADC 217, for example, as shown in FIG. The sampling rate may be set to be larger than half of the sampling rate. In order to set the IF frequency to a frequency different from the RF frequency, a configuration such as a frequency divider for dividing LO0 is provided between the LO 219 and the down-converter 220, if necessary for such setting. Alternatively, a down conversion signal may be obtained from a local signal oscillator separately from LO 219.

(Configuration of digital unit 400)
The digital unit 400 includes a digital modulation unit 406, a PA compensation unit 401, an orthogonal modulation error compensation unit 402, an orthogonal demodulation error compensation unit 404, and a control unit 405.

The digital modulation unit 406 modulates a bit sequence whose value is represented by 0 or 1 according to a specified rule, and generates orthogonal baseband signals I ₀ and Q ₀ representing data to be transmitted. In this embodiment, OFDM modulation is used as a conversion rule, but it goes without saying that the scope of application of the present invention is not limited to this.

The PA compensation unit 401 outputs I ₁ and Q ₁ obtained by performing nonlinear distortion compensation on the orthogonal baseband signals I ₀ and Q ₀ . As the PA compensation unit 401, for example, a nonlinear distortion compensation technique described in Japanese Patent No. 3198864 can be used.

The quadrature baseband signals I ₀ and Q ₀ that are outputs of the digital modulation unit 406 and I ₁ and Q ₁ that have been subjected to nonlinear distortion compensation are not subjected to compensation processing for the quadrature error generated by the quadrature modulation unit 205. The signal to be compensated for.

  Each of the orthogonal modulation error compensation unit 402 and the orthogonal demodulation error compensation unit 404 corrects the orthogonality of the input baseband orthogonal digital signal. That is, the quadrature modulation error compensation unit 402 and the quadrature demodulation error compensation unit 404 have two signals (a real part and an imaginary part corresponding to the amplitude, phase, and DC offset) of both components of the input baseband quadrature digital signal ( (Orthogonality compensated signal) is output. The input / output relationship is obtained and set from the orthogonal error detected in the error estimation mode. The compensation value set in the orthogonal modulation error compensation unit 402 and the compensation value set in the orthogonal demodulation error compensation unit 404 are obtained in the error estimation mode.

  The control unit 405 performs control of a sequence, which will be described later using a flowchart, and various calculations.

  FIG. 3 is a flowchart relating to the order of error estimation in the error estimation mode.

First, parameters used for quadrature error compensation of the quadrature modulation error compensation unit 402 are estimated (step 1). At this time, the switch 210 is connected, and the signal passing through the path from the digital modulation unit 406 to the quadrature modulator 205 is looped back to the quadrature modulation error compensation unit 402 via the down converter 220. Note that the switch 211 may be in a disconnected state. The orthogonal baseband signals I ₀ and Q ₀ output from the digital modulation unit 406 during the error estimation mode may be constant signals. In addition, any parameters may be set as appropriate in the PA compensation unit 401 and the orthogonal demodulation error compensation unit 404.

  Then, the estimated parameter is set in the quadrature modulation error compensation unit 402 (step 2), and the switch 210 is turned off so that the output of the subsequent quadrature modulation error compensation unit 402 is subjected to quadrature error compensation.

  Next, a parameter used for quadrature error compensation of the quadrature demodulation error compensation unit 404 is estimated (step 3). At this time, the switch 211 is connected, and the signal passing through the path from the digital modulation unit 406 to the quadrature modulator 205 is looped back to the quadrature demodulation error compensation unit 404 via the quadrature demodulator 213. Note that the switch 210 may be disconnected. For the PA compensation unit 401, for example, an arbitrary parameter may be set as appropriate, such as the value set in step 1. Since the quadrature error generated in the path from the digital modulation unit 406 to the quadrature modulator 205 is already compensated in step 2 by the quadrature modulation error compensation unit 402, the path from the PA 208 to the PA compensation unit 401 through the quadrature demodulator 213 is already compensated. The orthogonal error can be estimated accurately.

  Then, the estimated parameters are set in the quadrature modulation error compensation unit 402 (step 4) so that the subsequent output of the quadrature modulation error compensation unit 402 is subjected to quadrature error compensation.

  Next, a parameter used for nonlinear compensation of the PA compensation unit 401 is estimated (step 5). At this time, the switch 211 is set in the connected state so that the signal passing through the path from the digital modulation unit 406 to the quadrature modulator 205 is looped back to the PA compensation unit 401 via the quadrature demodulator 213 and the quadrature demodulation error compensation unit 404. To do. Note that the switch 210 may be disconnected. Since the orthogonal error of the path for looping back the signal to the PA compensation unit 401 has already been compensated in Step 2 and Step 4, the nonlinear distortion generated in the PA 208 can be accurately estimated.

  Then, the estimated parameter is set in the PA compensation unit 401 (step 6) so that the output of the subsequent PA compensation unit 401 is subjected to nonlinear distortion compensation.

  As described above, after obtaining the parameters used for the compensation of the orthogonal modulation error compensation unit 402, the orthogonal demodulation error compensation unit 404, and the PA compensation unit 401, the error estimation mode is terminated.

  In this way, parameters are set in the respective compensation units so that orthogonal errors and nonlinear distortion are compensated with high accuracy, and actually significant data is transmitted in the communication mode. In the communication mode, both the switches 210 and 211 may be disconnected.

  Although the control unit 405 controls the connection / disconnection of the switches 210 and 211 here, the configuration is not limited to this, and the operation / pause of the down converter 220 and the quadrature demodulator 213 is replaced with the switches 210 and 211. It is good also as a structure to perform.

(Configuration of Quadrature Modulation Error Compensator 402)
(Embodiment 1)
First, orthogonal error compensation will be described using the model shown in FIG.

  This model is represented by a combination of filter blocks 101 and 104, local signal oscillation block 102, modulation blocks 103 and 106, phase shift block 105, and addition block 107.

  The filter blocks 101 and 104 correspond to the BB filter 203, the local signal oscillation block 102 and the phase shift block 105 correspond to the LO 219, and the modulation blocks 103 and 106 and the addition block 107 correspond to the quadrature modulator 205.

Original signals (baseband signals modulated by the data modulation unit 406, corresponding to I ₁ and Q ₁₎ input to the filter blocks 101 and 104. However, if the PA compensation unit 401 is not provided, I ₀ and Q ₀ are used. S _I (n) and s _Q (n), respectively, are the outputs of the quadrature modulator model and are loopback signals (corresponding to I ₆ and Q ₆₎ that are looped back to the compensation unit 2 for quadrature error compensation. If each of them is x _I (n) and x _Q (n), the amplitude / phase error of the quadrature modulator is given by the following equation.

In the case of the model of FIG. 4, when α is a relative amplitude error between I and Q and Δθ is a relative phase error between I and Q, the following equation can be obtained.

  The theory of orthogonal error compensation for this model is described below.

  FIG. 5 is an example of a block diagram when the orthogonal error compensation method is implemented in the orthogonal modulation error compensator. The orthogonal modulation error compensation unit 402 includes a compensation unit 2, DFT (Discrete Fourier Transform) units 4 and 5, a matrix generation unit 8, a vector generation unit 9, a least square calculation unit 10, and a compensation amount update unit 11. Is provided.

The compensation unit 2 outputs I ₂ and Q ₂ obtained by multiplying I ₁ and Q ₁ by the inverse characteristic of the orthogonal error estimated value based on the orthogonal error estimated value calculated by the compensation amount updating unit 11 described later. . Thus, multiplying the inverse characteristics of the orthogonal error in advance is called orthogonal error compensation. The compensated signal is input to the quadrature modulator 205 and modulated to generate an RF signal and an IF signal. If quadrature error compensation is appropriately performed, an RF signal and IF signal with high modulation accuracy can be obtained at the output of the quadrature modulator.

The original signal is input to the DFT unit 4 (first frequency component extraction unit) and converted into a frequency domain signal. Similarly, the loopback signal is input to the DFT unit 5 and converted into a frequency domain signal. Here, the frequency k component of the loopback signal is given by the following equation.

As can be seen from this equation, four orthogonal error elements h ₁₁ , h ₁₂ , h ₂₁ , and h ₂₂ contribute to each component of I and Q.

The original signal converted into the frequency domain signal is input to the matrix generation unit 8 to generate a matrix R given by the following equation.

The loopback signal converted into the frequency domain signal is input to the vector generation unit 9 to generate a vector v given by the following equation.

The generated matrix and vector are input to the least square calculation unit 10, and the estimated values H ₁₁ , H ₁₂ , H ₂₁ , and H ₂₂ of the four orthogonal error elements are estimated at a time as given by the following equation. .

  This means that a 4 × 4 inverse matrix is being calculated.

  As described above, since the four orthogonal error elements contribute to the frequency k component of the loopback signal, the orthogonal modulation error compensator 402 performs the operation of the 4 × 4 inverse matrix and minimizes the minimum of the four orthogonal error elements. The square solution is calculated at once. In order to obtain the 4 × 4 inverse matrix, a signal processing algorithm that performs repetitive operations such as a discharge method can be used.

In the case of the orthogonal error model shown in FIG. 4, H ₁₁ should be 1, but in reality, it does not become 1 due to the influence of gain fluctuation caused by an analog filter or the like. Therefore, as shown in the following equation, the effects of gain fluctuations are removed by normalizing H ₁₂ and H ₂₂ with H ₁₁ .

The compensation amount updating unit 11 calculates the estimated value A of the amplitude error and the estimated value ΔΘ of the phase error as follows using H ₁₂ and H ₂₂ .

An equation for updating the correction amount using the estimated values of the amplitude error and the phase error is given by the following equation.

As processing in the compensation unit 2, correction to the original signal using the updated amplitude error estimated value and phase error estimated value is given by the following equation.

Needless to say, S ′ _I (n) and S ′ _Q (n) correspond to I ₁ and Q ₁ , and S _I (n) and S _Q (n) correspond to I ₂ and Q ₂ .

  As described above, orthogonal error compensation is performed.

(Embodiment 2)
When implementing the above theory, rather than using a signal processing algorithm that calculates four elements at once by performing repeated operations such as the spout method, it is better to adopt an algorithm that calculates two elements as described below. Can be used, and the accuracy can be further improved, and mounting on an FPGA (Field Programmable Gate Array) is facilitated.

  With reference to FIG. 6, it will be described that a signal processing algorithm for calculating four elements at a time can be replaced with an algorithm for calculating two elements. Signals of frequencies −k and + k that are symmetric with respect to a certain frequency c are hereinafter referred to as symmetric subcarriers.

Of the four orthogonal error elements h ₁₁ , h ₁₂ , h ₂₁ , and h ₂₂ of the original signal, two elements contribute to the opposite sign for each of the symmetric subcarriers. Two elements are offset and only the remaining two elements contribute.

  Therefore, the sum of the symmetric subcarriers separated from each other by the first frequency and the sum of the symmetric subcarriers separated from each other by the second frequency of the loopback signal are calculated. And estimate both the amplitude and phase error using both real parts (ie, I signal component) and estimate the remaining part of amplitude and phase error using both imaginary parts (ie, Q signal component). . That is, instead of calculating four elements at a time, two elements are calculated.

  FIG. 7 shows a block diagram according to the form of the quadrature modulation error compensation unit 402 implemented as described above.

  The quadrature modulation error compensation unit 402 includes a compensation unit 2, DFT units 4 and 5, a first addition unit 20, a second addition unit 21, a first real / imaginary separation unit 22, a second real / imaginary separation unit 23, and matrix generation. Unit 24, real vector generation unit 25, imaginary vector generation unit 26, least square calculation units 27 and 28, and compensation amount update unit 11.

The compensation unit 2 outputs I ₂ and Q ₂ obtained by multiplying I ₁ and Q ₁ by the inverse characteristic of the orthogonal error estimated value based on the orthogonal error estimated value calculated by the compensation amount updating unit 11 described later. .

  The original signal is input to the DFT unit 4 (first frequency component extraction unit) and converted into a frequency domain signal. The DFT unit 4 includes symmetric subcarriers S (+ k1) and S (−k1) whose frequencies are separated by ± k1 from a certain frequency c among the original signals converted into frequency domain signals, and ± k2 from the certain frequency c (however, Symmetric subcarriers S (+ k2) and S (−k2) separated in frequency by | k1 | <| k2 |) are output.

  The first adder 20 calculates the sum of symmetric subcarriers, that is, S (+ k1) + S (−k1) and S (+ k2) + S (−k2).

  The first real / imaginary separation unit 22 includes a real part (I component) and an imaginary part (Q component) of S (+ k1) + S (−k1), and a real part (I component) of S (+ k2) + S (−k2). ) And imaginary part (Q component).

The matrix generation unit 24 generates a matrix R given by the following equation based on the output of the first real / imaginary separation unit 22.

  On the other hand, the loopback signal is input to the DFT unit 5 (second frequency component extraction unit) and converted into a frequency domain signal. The DFT unit 5 includes symmetric subcarriers X (+ k1) and X (−k1) whose frequencies are separated by ± k1 from a certain frequency c in the original signal converted into a frequency domain signal, and ± k2 from the certain frequency c (however, Symmetric subcarriers X (+ k2) and X (−k2) that are separated in frequency by | k1 | <| k2 |) are output.

The second adder 21 calculates the sum of symmetric subcarriers, that is, X (+ k1) + X (−k1) and X (+ k2) + X (−k2). These can be expressed as:

  As can be seen from this equation, each sum signal contributes only two orthogonal error elements.

  The second real / imaginary separation unit 23 includes a real part (I component) and an imaginary part (Q component) of X (+ k1) + X (−k1), and a real part (I component) of X (+ k2) + X (−k2). ) And imaginary part (Q component) are extracted and output.

The real vector generator 25 generates a real vector V _I given by the following equation from both real parts.

Imaginary vector generation unit 26 generates an imaginary vector V _Q from both the imaginary part is given by the following equation.

The least square calculation unit 27 (first calculation unit) uses the matrix R generated by the matrix generation unit 24 and the real vector V _I generated by the real vector generation unit 25 to use two orthogonal error elements h ₁₁ and h _12. Is calculated.

The least square operation unit 28 (second operation unit) uses the matrix R generated by the matrix generation unit 24 and the imaginary vector V _Q generated by the imaginary vector generation unit 26 to use two orthogonal error elements h ₂₁ and h _22. Is calculated.

  Thus, the target of the inverse matrix calculation included in the calculations performed by the real vector generation unit 25 and the imaginary vector generation unit 26 can be a 2 × 2 inverse matrix. Since there is a mathematical formula for the calculation of the 2 × 2 inverse matrix, a special signal processing algorithm is not required, and there is no accumulation of quantization errors, and calculation can be performed with high accuracy. In addition, mounting with FPGA becomes easy.

  Although two symmetrical subcarriers ± k1 and ± k2 are used here, three or more symmetrical subcarriers may be used.

  In that case, rows of matrices and vectors can be increased. When the number of symmetric subcarriers to be used is increased, the orthogonal error estimated value can be calculated with higher accuracy.

  Alternatively, the average value of a plurality of symmetric subcarriers may be used as ± k1 or ± k2 without increasing the number of rows of matrices and vectors. In this case as well, in addition to improving the estimation accuracy, the number of matrix and vector rows does not increase, so the number of multiplications in the matrix operation does not increase and the circuit scale does not need to be increased.

For the four orthogonal error elements h ₁₁ , h ₁₂ , h ₂₁ , and h ₂₂ calculated as described above, the compensation amount update unit 11 normalizes as in the following equation (7) and influences the gain variation. Remove.

Further, the compensation amount update unit 11 calculates the estimated value A of the amplitude error and the estimated value ΔΘ of the phase error as follows using h ₁₂ and h ₂₂ .

  An equation for updating the correction amount using the estimated values of the amplitude error and the phase error is given by the above equation (9). As a method for ensuring the stability of the operation when the correction amount is updated, the estimated values of the amplitude error and the phase error may be averaged and substituted as an updated value. Further, when the estimated value exceeds the threshold value, for example, the amplitude error threshold is ± 0.5 dB and the phase error threshold is ± 5 degrees with respect to the amplitude error and the phase error, the estimated value is discarded. This method may be adopted.

  Further, as processing in the compensation unit 2, the correction for the original signal using the updated amplitude error estimated value and phase error estimated value is given by the above-described equation (10).

  As described above, orthogonal error compensation is performed.

The quadrature demodulation error compensation unit 404 may have the same configuration as the quadrature modulation error compensation unit 402. That is, the quadrature demodulation error compensation unit 404 receives I ₄ and Q ₄ instead of I ₁ and Q ₁ . Also, I ₅ and Q ₅ are output instead of I ₂ and Q ₂ .

(Embodiment 3)
The quadrature modulation error compensation unit 402 may be configured as shown in the block diagram of FIG. The quadrature modulation error compensation unit 402 includes a frequency offset compensation unit 37, correlation calculation units 38 and 39, a phase estimation unit 40, and a phase calculation unit 41 instead of the DFT units 4 and 5.

The frequency offset compensation unit 37 performs the following calculation using x _I (n) and x _Q (n) which are input loopback signals (corresponding to I ₆ and Q ₆ ), and outputs x ′ _I ( n) and x ′ _Q (n).

Here, Δk _IF is a frequency corresponding to the sampling interval of the ADC 224, and N is the number of data points sampled by the ADC 224 during one period of the IF signal.

  In the above calculation, the relationship between the center frequency of the IF signal and the sampling rate of the ADC 224 is not 1: 1, which is an irrational number. This is to improve accuracy.

The correlation calculation unit 39 performs a correlation calculation on x ′ _I (n) and x ′ _Q (n) according to the following equation, and converts both values into frequency domain values X _I (k) and X _Q (k). To do.

  In the discrete Fourier transform, N-point frequency signals are calculated from N-sample signals, but only a specific frequency point signal needs to be calculated in the above manner, and the amount of calculation is small.

Similarly, the correlation calculation unit 38 calculates the correlation between the original signals s _I (n) and s _Q (n) (baseband signals, corresponding to I ₁ and Q ₁ ) according to the following equation, Convert to values S _I (k) and S _Q (k).

Phase estimating unit 40, to the _{I 1} and _{Q 1, I 6} and the time period until the two signals come back to the orthogonal modulation correction unit 2 and DAC201 and analog unit 200 quadrature modulator error compensating portion 402 through the estimating a shift of Q ₆ (i.e. delay). Hereinafter, this delay will be described.

When the amplitude error and phase error of the quadrature modulator 205 are not so large, the original signals X _{IF_I} (k) and X _{IF_Q} (k) in the frequency domain and the loopback signals Q _{IF_I} (k−k _IF ) and Q _{IF_Q} (k -K _IF ) in the frequency domain can be expressed by the following equation.

Here, φ is the amount of phase rotation when the amount of delay in the time domain is expressed in the frequency domain. Under the assumption that the above equation holds, the outputs S _I (k) and S _Q (k) of the correlation calculation unit 38 related to the original signal and the outputs X _I (k) and X _Q ( k) is used to estimate the phase rotation amount φ.

The phase rotation amount φ can be expressed by a linear function (linear approximation) of the frequency k, and the least square solution of the phase rotation amount is given by the following equation.

here

And further

Ie

It is. Note that k _p is the frequency of the original signal from equation (25) to equation (28) described later. Also

It is. Here, φ (k _p ) is a frequency rotation amount at the frequency k = k _IF + k _p and can be expressed by the following equation.

As described above, φ does not include a dynamic value, that is, a value to be measured and does not change. That is, assuming that the component of the frequency k _p of the original signal corresponds to the component of the frequency k _IF + k _p of the loopback signal, the correspondence may be fixed, and the delay amount is set in advance by a register. It's good. When the spectrum is inverted with respect to the original signal depending on the frequency conversion method, the frequency k _IF + k _p component of the loopback signal may be associated with the frequency −k _p component of the original signal.

  The phase calculation unit 41 corrects the delay of the loopback signal using the above-described delay amount set by the phase estimation unit 40.

The second adder 21 calculates the sum of the symmetrical subcarriers of the delay-corrected loopback signal output from the phase calculator 41 according to the following equation.

  This equation has the same form as equation (12), and the subsequent processing may be performed in the same manner as in the embodiment shown in FIG.

  The DC offset riding on the loopback signal by the various components of the analog unit 200 can be estimated as follows.

The estimated values dc _I and dc _Q of the DC offset are h ₁₁ , h ₁₂ , h ₂₁ , h ₂₂ calculated when the amplitude error and phase error of the quadrature modulator 205 are estimated earlier, and the DC component of the original signal (that is, Component of frequency k = 0) and the center frequency component of the loopback IF signal (that is, the component of frequency k = k _IF ) is given by the following equation.

An equation for updating the correction amount using the estimated DC offset is given by the following equation.

Using the value updated by the compensation amount update unit 11 as described above, the compensation unit 2 performs correction on the original signal as follows.

Although the configuration of the quadrature modulation error compensation unit 402 has been described in detail so far, I ₁ and Q ₁ , I ₂ and Q ₂ , I ₆ and Q _6, which are inputs and outputs of the quadrature modulation error compensation unit 402, are respectively ₄ and Q ₄ , I ₅ and Q ₅ , I _1, and Q ₁ can be applied to the quadrature demodulation error compensator 404 by reading as ₄ and Q ₄ .

  The present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

The block diagram of the transmitter which concerns on 1st Embodiment. The figure which shows the relationship between the sampling rate of ADC and IF frequency. The flowchart which concerns on the order of the error estimation in error estimation mode. The figure which shows an example of the orthogonal error model of an orthogonal modulator. The block diagram which shows an example of an orthogonal modulation error compensation part. The figure which shows the relationship between the orthogonal error of an original signal, and a loopback signal. The block diagram which shows another example of an orthogonal modulation error compensation part. The block diagram which shows another example of a quadrature modulation error compensation part.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Transmission apparatus, 200 ... Analog part, 201 ... DAC, 203 ... BB filter, 205 ... Quadrature modulator, 208 ... PA, 209 ... Antenna, 210, 211 ... Switch, 213 ... Quadrature demodulator, 215 ... BB filter, 217 ... ADC, 219 ... LO, 220 ... Down converter, 222 ... IF filter, 224 ... ADC 400 ... Digital part 401 ... PA compensation part 402 ... Quadrature modulation error compensation part 404 ... Quadrature demodulation error compensation part 405 ... Control part 406 ... Digital modulation Department.

Claims (10)

An orthogonal modulation unit that generates an orthogonal modulation signal, a compensation unit that cancels an orthogonal error generated in the orthogonal modulation unit, a signal generation unit that generates a signal to be compensated, and a transmission unit that amplifies and transmits the orthogonal modulation signal A transmission device comprising:
A first frequency component separated by + k1 from the center frequency of the signal to be compensated, a second frequency component separated by -k1, a third frequency component separated by + k2 from the center frequency of the signal to be compensated, and- a first frequency component extraction unit that extracts a fourth frequency component separated by k2,
A matrix generation unit that generates a matrix from a real part and an imaginary part of each of the first to fourth frequency components;
A second frequency component for extracting a fifth frequency component separated by k1 and a sixth frequency component separated by k2 from a center frequency of a loopback signal obtained by looping back the orthogonal modulation signal toward the compensation unit. An extractor;
A vector generation unit that generates a vector including a real part and an imaginary part of the fifth frequency component and a sixth real part and an imaginary part;
An arithmetic unit that calculates a compensation value used to cancel an orthogonal error generated in the orthogonal modulation unit using the matrix and the vector, and supplies the compensation value to the compensation unit;
A transmission device comprising: An orthogonal modulation unit that generates an orthogonal modulation signal, a compensation unit that cancels an orthogonal error generated in the orthogonal modulation unit, a signal generation unit that generates a signal to be compensated, and a transmission unit that amplifies and transmits the orthogonal modulation signal In a transmission device comprising:
A first frequency component separated by + k1 from the center frequency of the signal to be compensated, a second frequency component separated by -k1, a third frequency component separated by + k2 from the center frequency of the signal to be compensated, and- a first frequency component extraction unit that extracts a fourth frequency component separated by k2,
A first sum that is the sum of the first frequency component and the second frequency component, and a second sum that is the sum of the third frequency component and the fourth frequency component are calculated. A first adder that
A first real part that is a real part of the first sum and a first imaginary part that is an imaginary part; a second real part that is a real part of the second sum; and a second part that is an imaginary part. A first separation unit for extracting an imaginary part;
A matrix generator that generates a matrix including the first real part, the first imaginary part, the second real part, and the second imaginary part;
The fifth frequency component separated by + k1 and the sixth frequency component separated by -k1 from the center frequency of the loopback signal obtained by looping back the orthogonal modulation signal toward the compensation unit, and the center of the loopback signal A second frequency component extraction unit that extracts a seventh frequency component separated from the frequency by + k2 (where | k1 | ≠ | k2 |) and an eighth frequency component separated by -k2;
A third sum that is the sum of the fifth frequency component and the sixth frequency component, and a fourth sum that is the sum of the seventh frequency component and the eighth frequency component are calculated. A second adder that
A third real part that is a real part of the third sum and a third imaginary part that is an imaginary part; a fourth real part that is a real part of the fourth sum; and a fourth part that is an imaginary part. A second separation unit for extracting an imaginary part;
A real vector generation unit that generates a real vector including the third real part and the fourth real part;
An imaginary vector generation unit that generates an imaginary vector including the third imaginary part and the fourth imaginary part;
A first arithmetic unit that uses the matrix and the real vector to calculate a first compensation value that is used to cancel the quadrature error that occurs in the quadrature modulation unit, and supplies the first compensation value to the compensation unit When,
A second arithmetic unit that calculates a second compensation value used to cancel the quadrature error generated in the quadrature modulation unit using the matrix and the imaginary vector, and supplies the second compensation value to the compensation unit When,
A transmission device comprising:   The transmission apparatus according to claim 2, wherein the first calculation unit calculates the first compensation value by a least square method using the matrix and the real vector as coefficients.   The transmission apparatus according to claim 2, wherein the second calculation unit calculates the second compensation value by a least square method using the matrix and the imaginary vector as coefficients.   The transmission apparatus according to claim 2, further comprising a down converter that down-converts the quadrature modulation signal and outputs the loopback signal. An A / D converter for A / D converting the loopback signal;
The down-converter down-converts the quadrature modulation signal to a frequency lower than the sampling rate of the A / D converter and higher than half of the sampling rate. Transmitter device. The first frequency component extraction unit extracts the first to fourth frequency components by performing a discrete Fourier transform on the signal to be compensated,
3. The transmission apparatus according to claim 2, wherein the second frequency component extraction unit extracts the fifth to eighth frequency components by subjecting the loopback signal to discrete Fourier transform. The first frequency component extraction unit extracts the first to fourth frequency components by correlating the signal to be compensated with a complex sine wave having the same frequency as the center frequency of the signal to be compensated. And
The second frequency component extraction unit extracts the fifth to eighth frequency components by correlating the loopback signal with a complex sine wave having the same frequency as the center frequency of the loopback signal. The transmission device according to claim 2. An orthogonal demodulator for demodulating the orthogonal modulation signal into a demodulated signal;
A demodulation error compensator that compensates for an orthogonal error of the demodulated signal to generate an orthogonal error compensation signal;
A nonlinear distortion compensation unit that performs nonlinear distortion compensation on the signal to be compensated using a nonlinear distortion compensation value calculated based on the orthogonal error compensation signal;
The transmission apparatus according to claim 2, further comprising:   The first computing unit is configured to calculate the first compensation value, the first compensation value is set in the compensating unit, and the second computing unit is configured to calculate the second compensation value. The compensation value of 2 is set in the compensation unit, and then the demodulation error compensation unit is caused to calculate a set value for compensating for the orthogonal error of the demodulated signal, and the set value is set in the demodulation error compensation unit, The transmission apparatus according to claim 9, further comprising a control unit that causes the nonlinear distortion compensation unit to calculate the nonlinear distortion compensation value and sets the nonlinear distortion compensation value in the nonlinear distortion compensation unit.

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