WO2009011071A1 - Amplifier device with nonlinear-distortion compensation - Google Patents

Amplifier device with nonlinear-distortion compensation Download PDF

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WO2009011071A1
WO2009011071A1 PCT/JP2007/064624 JP2007064624W WO2009011071A1 WO 2009011071 A1 WO2009011071 A1 WO 2009011071A1 JP 2007064624 W JP2007064624 W JP 2007064624W WO 2009011071 A1 WO2009011071 A1 WO 2009011071A1
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signal
delay
input signal
estimator
amplified
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PCT/JP2007/064624
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French (fr)
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Alexander N. Lozhkin
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Fujitsu Limited
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3247Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits

Abstract

An input signal is amplified by an amplifier unit to obtain an amplified signal and delayed by a delay amount to obtain a delayed signal. A nonlinear distortion in the amplified signal is compensated for based on the amplified signal and the delayed signal. A signal delay according to the amplifier unit is estimated and the delay amount for the input signal is controlled based on an estimated signal delay.

Description

DESCRIPTION

AMPLIFIER DEVICE WITH NONLINEAR-DISTORTION COMPENSATION

Technical Field

The present invention relates to an amplifier device for adaptively compensating for a nonlinear distortion in the amplified signal.

Background Art

High power amplifiers (HPAs) for third-generation (3G) wireless communication systems and wireless local area network (WLAN) like IEEE811.X or IEEE816.X need high linearity at the HPA output, to achieve a high adjacent channel leakage ratio (ACLR) and low error vector magnitude (EVM) . In addition, high efficiency is desirable. However, when operating with high efficiency, HPAs are the most non-linear . Digital predistortion (DPD) is an efficient cost-effective means of compensating for HPA nonlinearity and retaining high efficiency. The DPD reference design (see non-patent document 1) implements an adaptive lookup table (LUT) and applies correction values from the LUT to the incoming stream of samples. It also compares the measured output with the input, and uses this measurement to update the LUT, making the system adaptive. For 3G and WLAN systems the DPD reference design can operate on up to four universal mobile telecommunication systems (UMTS) channels and correct 3rd and 5th order intermodulation products.

DPD is commonly used to linearize HPAs. Ideal HPAs are perfectly linear. Denoting input and output amplitude and a coefficient by VIN, VOUT and k, respectively, their response can be described with the following equation (see line 101 in Fig. 1).

V0OT = k-ViH (1) However, real HPAs as used in wireless system exhibit some nonlinearities and eventually reach saturation. This nonlinearity can be expressed as follows by adding the term fNL into the equation (1), where fNL is used to describe the nonlinearity (see curve 102 in Fig. 1) .

Figure imgf000003_0001

The nonlinearity adversely affects the overall performance of a wireless system. It causes in-band distortion, which degrades the performance of the receiver, and out-of-band distortion, which degrades the performance of receivers in adjacent channels. The task of the predistorter is to add predistortion before the power amplifier, which is exactly the inverse of the distortion caused by the power amplifier i.e. equals fui,"1- When combining the predistorter with the power amplifier, the terms fNL and fNL ^1 cancel out, and the overall system can be described by the ideal HPA equation (1) .

The nonlinearity of the HPA is affected by ageing and changes in the operating environment, in particular the temperature. For this reason, the nonlinearity changes over time, and the solution should be made adaptive such that the predistorter tracks the changes in behavior of HPA.

Fig. 2 describes the basic algorithm implemented in the reference design. The incoming complex samples, in in-phase (I) and quadrature (Q) signals, have correction factors applied from LUT 206 at mixers 201 and 202 and then sent to the radio frequency (RF) I-Q modulator 203. The addresses for the LUT 206 are derived from the input power by address calculator 205. The LUT 206 must contain two values for each location - the I and Q correction factors.

In the RF I-Q modulator 203, samples are up-converted and sent to HPA 204. The HPA output is down-converted in RF I-Q Demodulator 210, which allows us to measure the error, i.e., the difference between the input phase and magnitude, and the measured phase and magnitude at the HPA output . Obviously, delay units 207 and 208 ensure that the input is compared to the correct output value by subtractors 211 and 212. The error signals output from the subtractors 211 and 212 are used by update unit 209 to update the values currently stored in the LUT 206.

The input data signals are fed into the address calculator 205, which determines the address of the LUT values. This LUT values modify the input data signals. In the design shown in Fig. 2, only power indexing is used.

The delay units 207 and 208 delay the input I and Q signals and output the delayed signals to the subtractors 211 and 212. This delay compensates for the delay of the predistorted signal traveling to the HPA 204 and then the HPA output making its way back to the feedback processing at the subtractors 211 and 212. To synchronize the feedback HPA output with the delayed input, an elaborate delay matching scheme is reguired.

In a synchronization scheme with discrete multitone transmission described in non-patent document 2, a receiver estimates a delay and splits the delay into an integer part J-TSAMPL and its fractional part Δ where J and TSAMPIl represent an integer and a sample period, respectively. The first delay J- T5AMPL can be estimated with coarse synchronization technigue based on the periodic cyclic prefix property. Thus generally- speaking, the synchronization is performed as follows: a timing unit adjusts the sampling clock phase over Δ. In addition, input data signals are delayed by J sampling clocks. Therefore there is a problem how to estimate the integer part J-TSAMPL- The simplest approach for coarse integer part of delay estimation is implementation of correlator based on the cyclic prefix properties. Thus the integer part estimation with a non-data-aided maximum likelihood (ML) -based evaluation can be implemented. Because of the cyclic prefix properties this algorithm correlates the received sample sequence with a shifted version over 2N samples of that sequence, where N represents the size of a fast Fourier transform.

Fig. 3 shows an integer part ML estimator according to such an approach. The grey area in each symbol corresponds to a cyclic prefix. This non-coherent estimator includes multipliers 301 and 302 and integrator 303, and computes correlation values between the received sample sequence and the shifted sequence for different values of J as estimation result 304. The value of J which produces the maximum correlation value results in an estimation of J.

The most problem with such an estimator is that an autocorrelation function of an orthogonal frequency division multiplexing (OFDM) signal is relatively flat. This problem becomes more serious for the oversampled OFDM signal, where the flat region of the autocorrelation function is extended over oversampled symbols. Another problem with an autocorrelation is the significant level of sidelobe because of a high peak-to-average power ratio. The significant level of sidelobe can cause a "false locking" during estimations. Patent Document 1 relates to a delay circuit for adjusting a time difference between an input signal and an output signal of an electronic device. In the delay circuit, either one of the signal of a real number value and the signal of an imaginary number value of a coefficient corresponding to the output signal and the input signal is selected, whether to invert the sign of the selected signal and output it or to output it with the sign as is is selected, and the signal of the average value of the selected value is outputted as the time difference signal.

Patent Document 1: Japanese Patent Application Publication No. 2004-172913

Non-patent Document 1: "Digital Predistortion Reference Design," [online], [Searched June 11, 2007], Internet <URL: http: //www. altera. com/literature/an/an314.pdf > Non-patent Document 2: T. Pollet and M. Peeters, "Synchronization with DMT Modulation, " IEEE Communications Magazine, pp. 80-86, April 1999.

Disclosure of Invention An object of the present invention is to synchronize a feedback signal from an amplifier output with a delayed input signal and compensate for a nonlinear distortion in the amplifier output precisely based on the feedback signal and the delayed input signal in an adaptive manner. An amplifier device according to the present invention comprises an amplifier unit, a variable delay unit, a compensator and an estimator. The amplifier unit amplifies an input signal and outputs an amplified signal . The variable delay unit delays the input signal by a delay amount and outputs a delayed signal. The compensator compensates for a nonlinear distortion in the amplified signal based on the amplified signal and the delayed signal. The estimator estimates a signal delay according to the amplifier unit and controls the delay amount of the variable delay unit based on an estimated signal delay. The amplifier unit, the variable delay unit and the compensator provides a modified DPD scheme with an adjustable delay amount, which is controlled by the estimator based on the estimated signal delay. According to such an amplifier device, the amplified signal which is fed back from the amplifier unit can be synchronized more precisely with the delayed signal delayed by the delay unit. Therefore, a superior compensation in the DPD reference design is performed for the nonlinear distortion.

Brief Description of Drawings

Fig . lisa graph showing a typical HPA AM-AM performances ; Fig. 2 is a configuration diagram showing a DPD reference design;

Fig.3 is a circuit diagram showing a non-coherent integer part estimator; Fig. 4 is a configuration diagram showing a HPA device according to an embodiment of the present invention;

Fig.5 is a block diagram showing a part of a DLL estimator;

Fig. 6 is a configuration diagram showing a correlator; Fig. 7 is a circuit diagram showing a phase removing circuit;

Fig. 8 is a configuration diagram showing an all-positive to bipolar converter; and

Fig. 9 is a graph showing simulation results of delay estimation for an OFDM signal.

Best Mode of Carrying Out the Invention

A best mode for carrying out the present invention is hereinafter described in detail with reference to the drawings. Fig. 4 shows a configuration of a HPA device according to an embodiment of the present invention. This HPA device has a configuration where delay units 207 and 208 are replaced with variable delay units 401 and 402 in the configuration shown in Fig. 2 and a Delay-Locked Loop (DLL) estimator 403 is added. The HPA device is used as an OFDM transmitter in a wireless communication system and receives a reference complex signal including OFDM symbols. However, the application target of the HPA device is not limited to OFDM signal and includes signals modulated by other types of modulation method. The DLL estimator 403 estimates a delay of the predistorted signals traveling from the mixers 201 and 202 to the HPA 204 and the HPA output signals traveling to the subtractors 211 and 212. More specifically, the DLL estimator 403 splits the delay into an integer part J-TSAMPL and its fractional part Δ, adjusts the sampling clock phase over Δ and estimates the integer J to control the delay amount of the variable delay units 401 and 402 based on the estimated value of J.

A non-coherent integer part estimator provided in the DLL estimator 403 is realized by such a configuration shown in Fig. 5. Variable delay unit 503 delays i-th OFDM symbol in the reference complex signal by i clocks and controller 502 changes the delay amount by one clock from one OFDM symbol to the next OFDM symbol until i reaches the maximum value M (i = 0, ..., M) . In this case, the maximum possible integer delay of the delay unit 503 is represented by M-TSAMPL-

Correlator 501 calculates the mutual correlation between the delayed signal with a delay amount of i clocks and a HPA output signal for each input reference signal, and outputs the obtained correlation value Corr (i) to the controller 502. Thus, after all M+l measurements, correlation values Corr (0) through Corr (M) are available at the controller 502. According to ML approach, the controller 502 determines a value of i corresponding to the maximum value of Corr(i) as the most reliable estimation result for J.

MAXOVERALL i ( Corr ( i ) , i ) ≡ i * J ( 3 )

The controller 502 outputs a control signal which sets the delay amount of the delay units 401 and 402 to the estimated value.

Fig. 6 shows a configuration example of the correlator 501. This correlator includes phase removing circuits 601 and 607, subtracters 602 and 608, constant generators 603 and 609, comparators 604 and 610, multiplier 605 and integrator 606. The main idea behind this embodiment is to make the delay estimation less complex i.e. to exclude from the calculation all resource-consuming operations like multiplication and square root calculations. Therefore, such a circuit as shown in Fig. 7 is proposed for phase removing circuits 601 and 607.

This phase removing circuit comprises modulus operation circuits 701 and 702 and adder 703. In this example, the possible approximation A = (X2+Y2)1/2 « |X| + |Y| has been employed for removing the phase dependence from the OFDM signals, where X and Y represents in-phase and quadrature signals, respectively. The modulus operation circuits 701 and 702 output modulus |X| and |Y|, respectively and the adder 703 outputs a sum of |X| and I Y I .

The subtractor 602 subtracts from the output of the phase removing circuit 601 a constant generated by the constant generator 603. The comparator 604 compares the subtraction result with zero and generates a signal indicating a sign of the subtraction result. This comparison operation is realized by a sign extraction circuit 801 as shown in Fig. 8. The sign extraction circuit 801 extracts the sign bit from a bipolar signal output from the subtractor 602 and output it to the multiplier 605.

The subtraction of the constant with the following sign extraction operation has two purposes: (1) Making from the all-positive signal after the modulus operation a bipolar signal at the sign extraction circuit input; and (2) Removing the amplitude modulation.

Thus, after the sign extraction operation, the new bipolar signal has a constant amplitude. Extracting the signal's sign bit make it possible to replace the multiplier 605 with a simpler logical AND circuit.

Let' s see more details about these purposes and the effect of the correlator. The amplitude of OFDM signal is an all-positive random variable with a non-zero average . According to the configuration shown in Fig. 6, in order to obtain the delay estimation result the input signal amplitude (all-positive value) has to be multiplied by the amplitude (all-positive value) of the reference signal delayed by i clocks . Multiplication itself is a very computing resource consuming operation, thus it is desirable to replace it with an alternative less complex operation, for example a logical AND. The logical AND can not operate with all-positive values, meanwhile it works well with bipolar values. Therefore, a circuit that produces a bipolar signal from the all-positive signal is necessary.

The implementation of the circuit shown in Fig. 6 makes it possible to replace multiplication with a logical AND operation. The circuit shown in Fig. 8 represents such an "All-positive to Bipolar" converter which is a part of the circuit shown in Fig. 6.

By selecting the constant equal to the OFDM signal average amplitude, the subtractor 602 can convert the all-positive amplitude of the original OFDM signal into the bipolar signal with the zero average. The following sign extraction circuit 801 converts input all-positive input signal into the bipolar pseudo-noise like signal with constant amplitude and a sharp autocorrelation function. In fact, the sharp autocorrelation function provides the better estimation abilities. Note that after the average removing from the original signal, amplitude of the newly obtained signal is still a random variable.

The operations of the phase removing circuit 607, the subtractor 608, the constant generator 609 and the comparator 610 is same as those of the phase removing circuit 601, the subtractor 602, the constant generator 603 and the comparator 604. The multiplier 605 computes 1-bit quantization value as a logical AND between signs of the bipolar signals output from the comparators 604 and 610. The integrator 606 computes a correlation value Corr(i) by summing the logical AND values output from the multiplier 605 for a sample sequence of the i-th OFDM symbol.

As mentioned above, the sign extraction operation produces the bipolar zero-average constant amplitude signal from the original signal. This bipolar signal is very close to the pseudo-noise signal of M-sequence that amplitude has only +1 or -1 value. Because this signal is very similar to the M-sequence, such pseudo-noise like signal has a very sharp autocorrelation function. Therefore, a good integer part estimation performance is possible even without amplitude information. Additionally, removing the amplitude modulation from the input signal significantly reduces the autocorrelation function sidelobe levels. The Non-coherent estimator based on a cyclic prefix correlation, shown in Fig. 3, is suffering from false locking. This is because the cyclic prefix is typically less than 25% of a symbol and the only cyclic prefix (small input signal portion) is used for the correlation operation in this estimator. In contrast, in the proposed estimator the whole energy of input signal can be used for the correlation operation. Therefore, the probability of the "false locking" decreases gradually.

Fig. 9 shows simulation results of delay estimation for an OFDM signal with 1024 subcarriers. horizontal and vertical axes represent the actual and estimated delay values, respectively and 12 represents an oversampling ratio (12 = 1, 2, 4). According to the simulation results, the proposed low-complexity integer part delay estimator has linear discrimination characteristic which is linear in a wide range of input integer delays. Additionally, there is no false locking that can distort the estimator's discrimination characteristic.

Claims

1. An amplifier device, comprising: an amplifier unit operable to amplify an input signal and output an amplified signal; a variable delay unit operable to delay the input signal by a delay amount and output a delayed signal; a compensator operable to compensate for a nonlinear distortion in the amplified signal based on the amplified signal and the delayed signal; and an estimator operable to estimate a signal delay according to the amplifier unit and control the delay amount of the variable delay unit based on an estimated signal delay.
2. The amplifier device according to claim 1, wherein the compensator applies predistortion according to the input signal to the input signal before input to the amplifier unit and updates a value of the predistortion based on the amplified signal and the delayed signal, and" the estimator estimates the signal delay of the input signal traveling from the compensator to the amplifier unit and coming back to the compensator as the amplified signal.
3. The amplifier device according to claim 1 or 2, wherein " the estimator removes phase dependence in the input signal and the amplified signal by a modulus operation and computes a correlation between the input signal and the amplified signal after the modulus operation to estimate the signal delay.
4. The amplifier device according to claim 3, wherein the estimator computes a first sum of modulus of an in-phase signal and a quadrature signal included in the input signal and a second sum of modulus of an in-phase signal and a quadrature signal included in the amplified signal and computes the correlation using the first and second sums.
5. The amplifier device according to claim 4, wherein the estimator subtracts a constant from each of the first and second sums to generate first and second subtraction results, respectively, extracts a sign from each of the first and second subtraction results to generate first and second sign information, respectively and computes the correlation using the first and second sign information.
6. The amplifier device according to claim 5, wherein the estimator computes a logical AND value between the first and second sign information and obtains the correlation by summing logical AND values for a sample sequence included in the input signal.
7. The amplifier device according to claim 5 or 6, wherein the estimator uses an average of amplitude of the input signal as the constant.
8. The amplifier device according to claim 1 or 2, wherein the estimator removes amplitude modulation from the input signal and the amplified signal and computes a correlation between the input signal and the amplified signal where the amplitude modulation is removed to estimate the signal delay.
9. A method of compensating for a nonlinear distortion in an output signal of an amplifier unit, comprising: amplifying an input signal by the amplifier unit to obtain an amplified signal; delaying the input signal by a delay amount to obtain a delayed signal; compensating for a nonlinear distortion in the amplified signal based on the amplified signal and the delayed signal; estimating a signal delay according to the amplifier unit ; and controlling the delay amount based on an estimated signal delay.
PCT/JP2007/064624 2007-07-19 2007-07-19 Amplifier device with nonlinear-distortion compensation WO2009011071A1 (en)

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EP2254240A1 (en) * 2009-05-21 2010-11-24 Fujitsu Limited Distortion compensation apparatus
CN102143097A (en) * 2010-11-04 2011-08-03 华为技术有限公司 Method and device for correcting delay difference of polar coordinate transmitter, and communication system
CN102291154A (en) * 2011-09-23 2011-12-21 电子科技大学 Polar transmitter
CN101800517B (en) 2009-02-05 2013-03-27 富士通株式会社 Predistorter and distortion compensation method

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EP1089428A2 (en) * 1999-09-30 2001-04-04 Kabushiki Kaisha Toshiba Nonlinear compensator
EP1511181A1 (en) * 2002-05-31 2005-03-02 Fujitsu Limited Distortion compenasator
US20040196922A1 (en) * 2003-04-03 2004-10-07 Andrew Corporation Independence between paths that predistort for memory and memory-less distortion in power amplifiers
US20050001675A1 (en) * 2003-07-03 2005-01-06 Icefyre Semiconductor Corporation Adaptive predistortion for a transmit system with gain, phase and delay adjustments
US20050184803A1 (en) * 2004-02-25 2005-08-25 Nobuo Hirose Distortion compensation circuit, power amplifier using distortion compensation circuit, and distortion compensation signal generating method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101800517B (en) 2009-02-05 2013-03-27 富士通株式会社 Predistorter and distortion compensation method
EP2254240A1 (en) * 2009-05-21 2010-11-24 Fujitsu Limited Distortion compensation apparatus
US7973601B2 (en) 2009-05-21 2011-07-05 Fujitsu Limited Distortion compensation apparatus
CN102143097A (en) * 2010-11-04 2011-08-03 华为技术有限公司 Method and device for correcting delay difference of polar coordinate transmitter, and communication system
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CN102143097B (en) 2010-11-04 2013-11-06 华为技术有限公司 Method and device for correcting delay difference of polar coordinate transmitter, and communication system
CN102291154A (en) * 2011-09-23 2011-12-21 电子科技大学 Polar transmitter
CN102291154B (en) 2011-09-23 2014-01-22 电子科技大学 Polar transmitter

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