JP5141694B2 - Amplifier with nonlinear distortion compensation - Google Patents

Description

  The present invention relates to an amplifying apparatus that adaptively compensates for nonlinear distortion of an amplified signal.

  Third generation (3G) wireless communication system and IEEE811. x and IEEE816. In high power amplifiers (HPA) for wireless local area networks (WLAN) such as x, high linearity to HPA output to achieve high adjacent channel leakage power ratio (ACLR) and low error vector amplitude (EVM) Sex is required. Furthermore, high efficiency is desirable. However, when operating at high efficiency, HPA is most nonlinear. Digital predistortion (DPD) is an efficient and cost effective means of ensuring high efficiency by compensating for the nonlinearity of HPA.

  The DPD reference design (see Non-Patent Document 1) implements an adaptive reference table (LUT) and applies correction values from the LUT to the input sample stream. The DPD reference design also adapts the system by comparing the measured output with the input and using the measurement result to update the LUT.

  For 3G and WLAN systems, the DPD reference design can operate on up to four universal mobile telecommunication systems (UMTS) channels and can correct third and fifth order intermodulation products.

In general, DPD is used to linearize HPA. The ideal HPA is completely linear. When the input amplitude, output amplitude, and coefficient are denoted as V _IN , V _OUT , and k, respectively, the response can be described by the following equations (see the straight line 101 in FIG. 1).
V _OUT = k · V _IN (1)

However, actual HPAs show some non-linearity in the wireless system and eventually reach saturation. This nonlinearity can be expressed as follows by adding the term f _{NL to} the equation (1) (see the curve 102 in FIG. 1).
V _OUT = f _NL · k · V _IN (2)

  This non-linearity adversely affects the overall performance of the wireless system. This results in in-band distortion that degrades the performance of the receiver and out-of-band distortion that degrades the performance of the receiver in the adjacent channel.

The role of the predistorter is to add a predistortion equal to the reciprocal of the distortion caused by the power amplifier, ie, a predistortion equal to f _NL ⁻¹ , in front of the power amplifier. By combining the predistorter with the power amplifier, the f _NL term and the f _NL ⁻¹ term cancel each other, and the entire system can be described by the ideal HPA equation (1).

  The non-linearity of HPA is affected by aging and changes in operating environment, particularly temperature changes. For this reason, since the non-linearity changes with time, the solution should be adapted so that the predistorter follows the operational changes of the HPA.

  FIG. 2 shows the basic algorithm implemented in the reference design. A correction factor is applied from the LUT 206 in the mixers 201 and 202 to the complex samples input as an in-phase (I) signal and a quadrature (Q) signal, and sent to the radio frequency (RF) IQ modulator 203. The address of the LUT 206 is derived from the input power by the address calculator 205. The LUT 206 must contain two values for each position: an I correction factor and a Q correction factor.

  The RFI-Q modulator 203 up-converts the sample and sends it to the HPA 204. The HPA output is down-converted by the RFI-Q demodulator 210, which makes it possible to measure the error, ie the difference between the input phase and amplitude and the phase and amplitude measured at the HPA output. Obviously, the delay units 207 and 208 ensure that the inputs are compared with the correct output values by the subtractors 211 and 212. The error signals output from the subtracters 211 and 212 are used for updating the value currently stored in the LUT 206 by the updating unit 209.

  The input data signal is supplied to the address calculator 205, which determines the address of the LUT value. This LUT value changes the input data signal. In the design shown in FIG. 2, only the power index is used.

  The delay units 207 and 208 delay the input I signal and Q signal, and output the delayed signal to the subtracters 211 and 212. This delay compensates for the delay until the predistortion signal propagates to the HPA 204 and the HPA output returns to the feedback processing at the subtractors 211 and 212. In order to synchronize this feedback HPA output with the delayed signal, a precise delay matching scheme is required.

In the synchronization scheme based on discrete multitone transmission described in Non-Patent Document 2, the receiver estimates the delay, J and T _SAMPL are an integer and a sample period, respectively, and the delay is an integer part J · T _SAMPL and its fraction part. Separated into Δ. The first delay J · T _SAMPL can be estimated by a coarse synchronization technique based on the cyclic prefix periodicity. Therefore, generally speaking, synchronization is performed as follows. The timing unit adjusts the phase of the sampling clock with respect to Δ. Further, the input data signal is delayed by J sampling clocks. Therefore, how to estimate the integer part J · T _SAMPL is a problem.

  The simplest approach to the coarse integer part of the delay estimate is to implement a correlator based on the characteristics of the cyclic prefix. Therefore, integer part estimation by evaluation based on non-data support maximum likelihood (ML) can be implemented. Due to the nature of the cyclic prefix, this algorithm correlates the received sample sequence with the sequence shifted by 2N samples, where N is the size of the fast Fourier transform.

  FIG. 3 shows an integer part ML estimator according to such an approach. The gray area of each symbol corresponds to a cyclic prefix. This non-coherent estimator includes multipliers 301 and 302 and an accumulator 303, and calculates a correlation value between a received sample sequence and a shifted sequence as an estimation result 304 for different values of J. The value of J that generates the maximum correlation value is the estimated value of J.

  The biggest problem with such an estimator is that the autocorrelation function of the orthogonal frequency division multiplexing (OFDM) signal is relatively flat. In oversampled OFDM signals, this problem is exacerbated because the flat area of the autocorrelation function is expanded for oversampled symbols. Another problem with autocorrelation is that the side lobe is at a significant level due to the high peak-to-average power ratio. Significant levels of side lobes cause “false locks” during estimation.

  Patent Document 1 relates to a delay circuit that adjusts a time difference between an input signal and an output signal of an electronic device. In this delay circuit, either the real value signal or the imaginary value signal of the coefficient corresponding to the output signal and the input signal is selected, and the selected signal is inverted and output, or the sign Whether to output the signal as it is is selected, and an average value signal of the selected values is output as a time difference signal.

JP 2004-172913 A

“Digital Predistortion Reference Design”, [online], [searched on June 11, 2007], Internet <URL: http://www.altera.com/literature/an/an314.pdf> T. Pollet and M. Peeters, “Synchronization with DMT Modulation,” IEEE Communications Magazine, pp. 80-86, April 1999.

  It is an object of the present invention to synchronize the feedback signal from the amplifier output with the delayed input signal and accurately compensate for non-linear distortion at the amplifier output in an adaptive manner based on the feedback signal and the delayed input signal.

  The amplification device of the present invention includes an amplification unit, a variable delay unit, a compensator, and an estimator. The amplifying unit amplifies the input signal and outputs the amplified signal. The variable delay unit delays the input signal by a delay amount and outputs a delay signal. The compensator compensates for nonlinear distortion of the amplified signal based on the amplified signal and the delayed signal. The estimator estimates the signal delay by the amplification unit, and controls the delay amount of the variable delay unit based on the estimated signal delay.

  The amplifier, variable delay, and compensator provide an improved DPD scheme with an adjustable amount of delay that is controlled by the estimator based on the estimated signal delay. According to such an amplifying device, the amplified signal fed back from the amplifying unit can be more accurately synchronized with the delayed signal delayed by the delay unit. Therefore, better compensation in the DPD reference design is provided for non-linear distortion.

It is a graph which shows the AM-AM performance of HPA. It is a block diagram which shows DPD reference design. It is a circuit diagram which shows a non-coherent integer part estimator. It is a block diagram which shows the HPA apparatus of embodiment of this invention. It is a block diagram which shows a part of DLL estimator. It is a block diagram which shows a correlator. It is a circuit diagram which shows a phase removal circuit. It is a block diagram which shows an all positive-bipolar converter. It is a graph which shows the simulation result of the delay estimation with respect to an OFDM signal.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings.
FIG. 4 shows the configuration of the HPA apparatus according to the embodiment of the present invention. This HPA apparatus has a configuration in which the delay units 207 and 208 are replaced with variable delay units 401 and 402 in the configuration shown in FIG. 2, and a delay lock loop (DLL) estimator 403 is added. This HPA apparatus is used as an OFDM transmitter in a wireless communication system, and receives a reference complex signal including an OFDM symbol. However, the application target of the HPA device is not limited to the OFDM signal, but includes a signal modulated by another type of modulation scheme.

The DLL estimator 403 estimates the delay of the predistortion signal propagating from the mixers 201 and 202 to the HPA 204 and the HPA output propagating to the subtractors 211 and 212. More specifically, the DLL estimator 403 separates the delay into an integer part J · T _SAMPL and its fractional part Δ, adjusts the phase of the sampling clock with respect to Δ, estimates the integer J, Based on the estimated value of J, the delay amount of the variable delay units 401 and 402 is controlled.

The non-coherent integer part estimator provided in the DLL estimator 403 is realized by the configuration shown in FIG. The variable delay unit 503 delays the i-th OFDM symbol in the reference complex signal by i clocks, and the controller 502 performs one operation until i reaches the maximum value M (i = 0,..., M). The delay amount is changed by one clock from the OFDM symbol to the next OFDM symbol. In this case, the maximum possible integer delay of the delay unit 503 is represented by M · T _SAMPL .

The correlator 501 calculates the cross-correlation between the delay signal having a delay amount of i clocks and the HPA output signal for each input reference signal, and sends the obtained correlation value Corr (i) to the controller 502. Output. Thus, when all the M + 1 measurements are completed, the controller 502 can use the correlation values from Corr (0) to Corr (M). Controller 502 determines the value of i corresponding to the maximum value of Corr (i) as the most reliable estimation result for J by the ML approach.

  The controller 502 outputs a control signal that sets the delay amount of the delay units 401 and 402 to the estimated value.

  FIG. 6 shows a configuration example of the correlator 501. The correlator includes phase removal circuits 601 and 607, subtracters 602 and 608, constant generators 603 and 609, comparators 604 and 610, a multiplier 605, and an accumulator 606. The main idea behind this embodiment is to make delay estimation simpler, i.e. to eliminate all resource consuming operations such as multiplication and square root calculations from the calculation. Therefore, as the phase removal circuits 601 and 607, a circuit as shown in FIG. 7 is proposed.

This phase removal circuit includes absolute value calculation circuits 701 and 702 and an adder 703. In this example, assuming that X and Y represent in-phase and quadrature signals, respectively, as an approximation that can be considered to remove phase dependence from the OFDM signal,
Is adopted. Absolute value calculation circuits 701 and 702 output absolute values | X | and | Y |, respectively, and an adder 703 outputs the sum of | X | and | Y |.

  The subtractor 602 subtracts the constant generated by the constant generator 603 from the output of the phase removal circuit 601. The comparator 604 compares the subtraction result with zero and generates a signal indicating the sign of the subtraction result. This comparison operation is realized by a code extraction circuit 801 as shown in FIG. The code extraction circuit 801 extracts a sign bit from the bipolar signal output from the subtractor 602 and outputs it to the multiplier 605.

For constant subtraction and subsequent sign extraction operation,
(1) generating a bipolar signal at the input of the sign extraction circuit from all positive signals after the absolute value calculation;
(2) There are two purposes of removing amplitude modulation.

  Thus, the new bipolar signal after the code extraction calculation has a constant amplitude. By extracting the sign bit of the signal, the multiplier 605 can be replaced with a simpler logical AND circuit.

  We discuss these objectives and the effect of correlators in more detail. The amplitude of the OFDM signal is a fully positive random variable with a non-zero mean. According to the configuration shown in FIG. 6, in order to obtain a delay estimation result, the amplitude of the input signal (total positive value) must be multiplied by the amplitude of the reference signal (total positive value) delayed by i clocks. Don't be. Since multiplication itself is an operation that consumes a lot of computational resources, it is desirable to replace it with a simpler operation such as a logical AND. Although logical AND cannot be performed with all positive values, it works well with bipolar values. Therefore, a circuit that generates a bipolar signal from all positive signals is required.

  By implementing the circuit shown in FIG. 6, the multiplication can be replaced with a logical AND circuit. The circuit shown in FIG. 8 represents such an “all positive-bipolar” converter that is part of the circuit shown in FIG.

  By selecting a constant equal to the average amplitude of the OFDM signal, the subtractor 602 can convert the total positive amplitude of the original OFDM signal into a bipolar signal with an average of zero. The subsequent code extraction circuit 801 converts the input positive input signal into a bipolar pseudo-noise-like signal having a constant amplitude and a sharp autocorrelation function. In fact, a sharp autocorrelation function gives a better estimation capability. Note that the newly obtained signal after removing the average from the original signal is still a random variable.

  The operations of the phase removal circuit 607, the subtractor 608, the constant generator 609, and the comparator 610 are the same as the operations of the phase removal circuit 601, the subtractor 602, the constant generator 603, and the comparator 604. The multiplier 605 calculates a 1-bit quantized value as a logical AND between the signs of the bipolar signals output from the comparators 604 and 610. The accumulator 606 adds the logical AND value output from the multiplier 605 to the sample sequence of the i-th OFDM symbol, and calculates the correlation value Corr (i).

  As described above, according to the code extraction calculation, a bipolar signal having an average of zero and a constant amplitude is generated from the original signal. This bipolar signal is very close to an M-sequence pseudo noise signal having an amplitude of +1 or -1. Since this signal is very similar to the M sequence, such a pseudo-noise-like signal has a very sharp autocorrelation function. Therefore, good integer part estimation performance can be obtained without amplitude information.

  Further, by removing amplitude modulation from the input signal, the sidelobe level of the autocorrelation function is significantly reduced. The non-coherent estimator based on the cyclic prefix correlation shown in FIG. 3 has a weakness of false lock. This is because the cyclic prefix is typically less than 25% of the symbols, and this estimator uses only the cyclic prefix for the correlation operation. On the other hand, the proposed estimator can use the total energy of the input signal for the correlation calculation. Therefore, the probability of “false lock” gradually decreases.

  FIG. 9 shows a simulation result of delay estimation for an OFDM signal having 1024 subcarriers. The horizontal and vertical axes represent the actual delay value and the estimated delay value, respectively, and I2 represents the oversampling rate (I2 = 1, 2, 4). According to this simulation result, the proposed low complexity integer part delay estimator has a linear discriminant characteristic that is linear in a wide range of input integer delays. Furthermore, there are no false locks that can distort the discriminating characteristics of the estimator.

Claims (7)

An amplification unit operable to amplify an input signal and output an amplified signal;
A variable delay unit operable to delay the input signal by a delay amount and output a delayed signal;
A compensator operable to compensate for non-linear distortion of the amplified signal based on the amplified signal and the delayed signal;
An estimator operable to estimate a signal delay by the amplification unit and control the delay amount of the variable delay unit based on the estimated signal delay ;
The compensator applies predistortion due to the input signal to the input signal before input to the amplification unit, and updates the value of the predistortion based on the amplified signal and the delayed signal,
The estimator calculates the absolute value of the in-phase signal and the quadrature signal included in the input signal, and the absolute value calculation using the absolute value of the in-phase signal and the quadrature signal included in the amplified signal. The phase dependency of the amplified signal is removed, the correlation between the input signal after the absolute value calculation and the amplified signal is calculated, and the input signal is propagated from the compensator to the amplifying unit to be amplified. An amplifier that estimates the signal delay until it returns to the compensator . The estimator uses a first sum of absolute values of the in-phase signal and the quadrature signal included in the input signal and a second sum of absolute values of the in-phase signal and the quadrature signal included in the amplified signal. The amplifying apparatus according to claim 1, wherein phase dependency between the input signal and the amplified signal is removed by absolute value calculation . The estimator calculates a first sum of absolute values of the in-phase signal and the quadrature signal included in the input signal and a second sum of absolute values of the in-phase signal and the quadrature signal included in the amplified signal. The amplification device according to claim 1 , wherein the correlation is calculated using the first and second sums. The estimator subtracts a constant from each of the first and second sums to generate first and second subtraction results, respectively, and extracts a sign from each of the first and second subtraction results Generating first and second code information respectively, and calculating the correlation using the first and second code information,
The amplification device according to claim 3 . The estimator, the logical AND value between the first and second code information is calculated to determine the correlation by adding the logical AND value for the sample sequence included in the input signal, according to claim 4, wherein Amplification device. The estimator removes amplitude modulation from the input signal and the amplified signal, and calculates a correlation between the input signal from which the amplitude modulation has been removed and the amplified signal to estimate the signal delay. 1 Symbol placing the amplifying device. Compensating for non-linear distortion of the output signal of the amplifying unit,
Amplifying the input signal by the amplification unit to obtain an amplified signal,
Delay the input signal by a delay amount to obtain a delayed signal;
By applying a predistortion due to the input signal to the input signal before input to the amplification unit by a compensator, and updating the value of the predistortion based on the amplified signal and the delayed signal, Compensate for nonlinear distortion of the amplified signal;
Phase dependence of the input signal and the amplified signal by the absolute value calculation using the absolute value of the in-phase signal and the quadrature signal included in the input signal and the absolute value of the in-phase signal and the quadrature signal included in the amplified signal And calculating the correlation between the input signal after the absolute value calculation and the amplified signal, so that the input signal propagates from the compensator to the amplifying unit and is used as the amplified signal. Estimate the signal delay before returning to
A method of controlling the delay amount based on an estimated signal delay.