JP2008158955A5 - - Google Patents

Download PDF

Info

Publication number
JP2008158955A5
JP2008158955A5 JP2006349753A JP2006349753A JP2008158955A5 JP 2008158955 A5 JP2008158955 A5 JP 2008158955A5 JP 2006349753 A JP2006349753 A JP 2006349753A JP 2006349753 A JP2006349753 A JP 2006349753A JP 2008158955 A5 JP2008158955 A5 JP 2008158955A5
Authority
JP
Japan
Prior art keywords
blocks
cell
flash memory
storage layers
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006349753A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008158955A (ja
JP4563992B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2006349753A priority Critical patent/JP4563992B2/ja
Priority claimed from JP2006349753A external-priority patent/JP4563992B2/ja
Publication of JP2008158955A publication Critical patent/JP2008158955A/ja
Priority to US12/495,078 priority patent/US20090262577A1/en
Publication of JP2008158955A5 publication Critical patent/JP2008158955A5/ja
Application granted granted Critical
Publication of JP4563992B2 publication Critical patent/JP4563992B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2006349753A 2006-12-26 2006-12-26 多値フラッシュメモリおよび多値フラッシュメモリへのデータ書き込み方法 Active JP4563992B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006349753A JP4563992B2 (ja) 2006-12-26 2006-12-26 多値フラッシュメモリおよび多値フラッシュメモリへのデータ書き込み方法
US12/495,078 US20090262577A1 (en) 2006-12-26 2009-06-30 Multi-level cell flash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006349753A JP4563992B2 (ja) 2006-12-26 2006-12-26 多値フラッシュメモリおよび多値フラッシュメモリへのデータ書き込み方法

Publications (3)

Publication Number Publication Date
JP2008158955A JP2008158955A (ja) 2008-07-10
JP2008158955A5 true JP2008158955A5 (enExample) 2009-11-05
JP4563992B2 JP4563992B2 (ja) 2010-10-20

Family

ID=39659766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006349753A Active JP4563992B2 (ja) 2006-12-26 2006-12-26 多値フラッシュメモリおよび多値フラッシュメモリへのデータ書き込み方法

Country Status (2)

Country Link
US (1) US20090262577A1 (enExample)
JP (1) JP4563992B2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8537613B2 (en) 2011-03-31 2013-09-17 Sandisk Technologies Inc. Multi-layer memory system
US8755226B2 (en) 2012-08-07 2014-06-17 Kabushiki Kaisha Toshiba Storage device and control method of nonvolatile memory
US9348746B2 (en) 2012-12-31 2016-05-24 Sandisk Technologies Method and system for managing block reclaim operations in a multi-layer memory
US9734050B2 (en) 2012-12-31 2017-08-15 Sandisk Technologies Llc Method and system for managing background operations in a multi-layer memory
US9734911B2 (en) 2012-12-31 2017-08-15 Sandisk Technologies Llc Method and system for asynchronous die operations in a non-volatile memory
US9336133B2 (en) 2012-12-31 2016-05-10 Sandisk Technologies Inc. Method and system for managing program cycles including maintenance programming operations in a multi-layer memory
US8873284B2 (en) 2012-12-31 2014-10-28 Sandisk Technologies Inc. Method and system for program scheduling in a multi-layer memory
US9465731B2 (en) 2012-12-31 2016-10-11 Sandisk Technologies Llc Multi-layer non-volatile memory system having multiple partitions in a layer
US9223693B2 (en) 2012-12-31 2015-12-29 Sandisk Technologies Inc. Memory system having an unequal number of memory die on different control channels
CN103257928B (zh) * 2013-04-16 2016-01-13 深圳市江波龙电子有限公司 闪存设备数据管理方法和系统
KR102272228B1 (ko) * 2014-05-13 2021-07-06 삼성전자주식회사 불휘발성 메모리 장치, 그것을 포함하는 저장 장치 및 그것의 동작 방법
US10133490B2 (en) 2015-10-30 2018-11-20 Sandisk Technologies Llc System and method for managing extended maintenance scheduling in a non-volatile memory
US10042553B2 (en) 2015-10-30 2018-08-07 Sandisk Technologies Llc Method and system for programming a multi-layer non-volatile memory having a single fold data path
US10120613B2 (en) 2015-10-30 2018-11-06 Sandisk Technologies Llc System and method for rescheduling host and maintenance operations in a non-volatile memory
US9778855B2 (en) 2015-10-30 2017-10-03 Sandisk Technologies Llc System and method for precision interleaving of data writes in a non-volatile memory

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0546494A (ja) * 1991-08-19 1993-02-26 Toshiba Corp メモリチエツク方式
JP3268130B2 (ja) * 1994-07-20 2002-03-25 株式会社東芝 フラッシュｅｅｐｒｏｍを用いたデータ処理装置
US6847550B2 (en) * 2002-10-25 2005-01-25 Nexflash Technologies, Inc. Nonvolatile semiconductor memory having three-level memory cells and program and read mapping circuits therefor
US6831865B2 (en) * 2002-10-28 2004-12-14 Sandisk Corporation Maintaining erase counts in non-volatile storage systems
US7177977B2 (en) * 2004-03-19 2007-02-13 Sandisk Corporation Operating non-volatile memory without read disturb limitations
US7308525B2 (en) * 2005-01-10 2007-12-11 Sandisk Il Ltd. Method of managing a multi-bit cell flash memory with improved reliablility and performance
US7275140B2 (en) * 2005-05-12 2007-09-25 Sandisk Il Ltd. Flash memory management method that is resistant to data corruption by power loss

Similar Documents

Publication Publication Date Title
JP2008158955A5 (enExample)
WO2008098363A8 (en) Non-volatile memory with dynamic multi-mode operation
JP2013522776A5 (enExample)
JP2011522301A5 (enExample)
DE60214023D1 (de) Selektiver betrieb eines nichtflüchtigen mehrzustands-speichersystems in einem binärmodus
WO2007130615A3 (en) A method for reading a multilevel cell in a non-volatile memory device
WO2007133645A3 (en) Nand architecture memory devices and operation
EP1892721A3 (en) Method of programming a multi-bit non-volatile memory device and multi-bit non-volatile memory device
TW200617962A (en) Multi-purpose non-volatile memory card
WO2008026204A3 (en) Logical super block mapping for nand flash memory
WO2011130013A3 (en) Multi-port memory having a variable number of used write ports
WO2012174216A3 (en) Block management schemes in hybrid slc/mlc memory
WO2012134864A3 (en) Memory system with three memory layers having different bit per cell storage capacities
JP2010535395A5 (enExample)
WO2008094899A3 (en) Memory device architectures and operation
WO2004059651A3 (en) Nonvolatile memory unit with specific cache
TW200834304A (en) Non-volatile semiconductor memory system and data write method thereof
SG135056A1 (en) Data storage device using two types of storage medium
WO2009013879A1 (ja) メモリーコントローラ、及びこれを用いた不揮発性記憶装置
JP2010287303A5 (enExample)
JP2010503929A5 (enExample)
EP1947652A8 (en) Phase-change memory device with error correction capability
JP2005259334A5 (enExample)
JP2007087526A5 (enExample)
WO2011062680A3 (en) Memory device and method thereof