JP2008153580A5 - - Google Patents
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- JP2008153580A5 JP2008153580A5 JP2006342472A JP2006342472A JP2008153580A5 JP 2008153580 A5 JP2008153580 A5 JP 2008153580A5 JP 2006342472 A JP2006342472 A JP 2006342472A JP 2006342472 A JP2006342472 A JP 2006342472A JP 2008153580 A5 JP2008153580 A5 JP 2008153580A5
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- JP
- Japan
- Prior art keywords
- layer
- resin
- insulating
- forming
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 229920005989 resin Polymers 0.000 claims 23
- 239000011347 resin Substances 0.000 claims 23
- 210000003491 Skin Anatomy 0.000 claims 6
- 238000004519 manufacturing process Methods 0.000 claims 6
- -1 alicyclic olefin Chemical class 0.000 claims 5
- 229920000642 polymer Polymers 0.000 claims 5
- 239000000853 adhesive Substances 0.000 claims 4
- 230000001070 adhesive Effects 0.000 claims 4
- 150000001875 compounds Chemical class 0.000 claims 3
- 239000004020 conductor Substances 0.000 claims 3
- 239000002184 metal Substances 0.000 claims 3
- 239000007800 oxidant agent Substances 0.000 claims 3
- 230000001590 oxidative Effects 0.000 claims 3
- 230000000149 penetrating Effects 0.000 claims 3
- 238000007747 plating Methods 0.000 claims 3
- 239000003822 epoxy resin Substances 0.000 claims 1
- 229920000647 polyepoxide Polymers 0.000 claims 1
Claims (6)
第１絶縁層上の第１配線層上にビルドアップ多層配線の絶縁層形成用の絶縁樹脂から成る樹脂主層を形成する工程、
上記樹脂主層上に、脂環式オレフィン重合体から成る樹脂表皮層を形成し、該樹脂表皮層に金属配位能を有する化合物を接触させた後、樹脂主層および樹脂表皮層を硬化して両者の積層体としての第２絶縁層を形成させる工程、
上記第２絶縁層を貫通して上記第１配線層の上面に達するビア穴を形成する工程、
酸化剤により上記ビア穴のデスミア処理を行う工程、および
上記第２絶縁層上にめっき法により第２配線層用の導体層を形成する工程
を含むことを特徴とする多層配線基板の製造方法。 A method of manufacturing a multilayer wiring board in which wiring layers and insulating layers are alternately laminated,
Forming a resin main layer made of an insulating resin for forming an insulating layer of a build-up multilayer wiring on the first wiring layer on the first insulating layer;
A resin skin layer made of an alicyclic olefin polymer is formed on the resin main layer, and after contacting the compound having a metal coordination ability with the resin skin layer, the resin main layer and the resin skin layer are cured. Forming a second insulating layer as a laminate of the two,
Forming a via hole penetrating the second insulating layer and reaching the upper surface of the first wiring layer;
A method for manufacturing a multilayer wiring board, comprising: a step of performing desmearing of the via hole with an oxidant; and a step of forming a conductor layer for a second wiring layer on the second insulating layer by a plating method.
第１絶縁層上の第１配線層上にビルドアップ多層配線の絶縁層形成用の絶縁樹脂から成る樹脂主層を形成する工程、
上記樹脂主層を硬化する工程、
上記硬化後の樹脂主層上に、脂環式オレフィン重合体から成る樹脂表皮層を形成し、該樹脂表皮層に金属配位能を有する化合物に接触させる工程、
上記樹脂表皮層を硬化して上記樹脂主層と一体の積層体としての第２絶縁層を形成させる工程、
上記第２絶縁層を貫通して上記第１配線層の上面に達するビア穴を形成する工程、
酸化剤により上記ビア穴のデスミア処理を行う工程、および
上記第２絶縁層上にめっき法により第２配線層用の導体層を形成する工程
を含むことを特徴とする多層配線基板の製造方法。 A method of manufacturing a multilayer wiring board in which wiring layers and insulating layers are alternately laminated,
Forming a resin main layer made of an insulating resin for forming an insulating layer of a build-up multilayer wiring on the first wiring layer on the first insulating layer;
Curing the resin main layer,
Forming a resin skin layer composed of an alicyclic olefin polymer on the cured resin main layer, and contacting the resin skin layer with a compound having metal coordination ability;
Curing the resin skin layer to form a second insulating layer as a laminate integral with the resin main layer;
Forming a via hole penetrating the second insulating layer and reaching the upper surface of the first wiring layer;
A method for manufacturing a multilayer wiring board, comprising: a step of performing desmearing of the via hole with an oxidant; and a step of forming a conductor layer for a second wiring layer on the second insulating layer by a plating method.
第１絶縁層上の第１配線層上に、高耐熱性接着剤の層を形成する工程、
上記高耐熱性接着剤層上に、脂環式オレフィン重合体から成る樹脂層を形成し、該樹脂層に金属配位能を有する化合物を接触させた後、高耐熱性接着剤層および樹脂層を硬化して両者の積層体としての第２絶縁層を形成させる工程、
上記第２絶縁層を貫通して上記第１配線層の上面に達するビア穴を形成する工程、
酸化剤により上記ビア穴のデスミア処理を行う工程、および
上記第２絶縁層上にめっき法により第２配線層用の導体層を形成する工程
を含むことを特徴とする多層配線基板の製造方法。 A method of manufacturing a multilayer wiring board in which wiring layers and insulating layers are alternately laminated,
Forming a high heat-resistant adhesive layer on the first wiring layer on the first insulating layer;
A resin layer composed of an alicyclic olefin polymer is formed on the high heat resistant adhesive layer, and a compound having a metal coordination ability is brought into contact with the resin layer, and then the high heat resistant adhesive layer and the resin layer are contacted. Curing the step of forming a second insulating layer as a laminate of both,
Forming a via hole penetrating the second insulating layer and reaching the upper surface of the first wiring layer;
A method for manufacturing a multilayer wiring board, comprising: a step of performing desmearing of the via hole with an oxidant; and a step of forming a conductor layer for a second wiring layer on the second insulating layer by a plating method.
第１絶縁層上の第１配線層上に第２絶縁層が設けられており、 A second insulating layer is provided on the first wiring layer on the first insulating layer;
上記第２絶縁層は、ビルドアップ多層配線基板用の絶縁層形成用の樹脂層と、該樹脂層上の脂環式オレフィン重合体からなる樹脂層とからなる積層体であり、 The second insulating layer is a laminate composed of a resin layer for forming an insulating layer for a build-up multilayer wiring board and a resin layer made of an alicyclic olefin polymer on the resin layer,
上記第２絶縁層にはビア穴が設けられ、ビア穴の底には上記第１配線層が露出し、その上に第２配線層が形成されている The second insulating layer is provided with a via hole, the first wiring layer is exposed at the bottom of the via hole, and the second wiring layer is formed thereon.
ことを特徴とする多層配線基板。A multilayer wiring board characterized by that.
第１絶縁層上の第１配線層上に第２絶縁層が設けられており、 A second insulating layer is provided on the first wiring layer on the first insulating layer;
上記第２絶縁層は、高耐熱性接着剤の層と、該層上の脂環式オレフィン重合体からなる樹脂層とからなる積層体であり、 The second insulating layer is a laminate composed of a high heat-resistant adhesive layer and a resin layer made of an alicyclic olefin polymer on the layer,
上記第２絶縁層にはビア穴が設けられ、ビア穴の底には上記第１配線層が露出し、その上に第２配線層が形成されている The second insulating layer is provided with a via hole, the first wiring layer is exposed at the bottom of the via hole, and the second wiring layer is formed thereon.
ことを特徴とする多層配線基板。A multilayer wiring board characterized by that.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006342472A JP4895795B2 (en) | 2006-12-20 | 2006-12-20 | Manufacturing method of multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006342472A JP4895795B2 (en) | 2006-12-20 | 2006-12-20 | Manufacturing method of multilayer wiring board |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008153580A JP2008153580A (en) | 2008-07-03 |
| JP2008153580A5 true JP2008153580A5 (en) | 2009-10-22 |
| JP4895795B2 JP4895795B2 (en) | 2012-03-14 |
Family
ID=39655401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006342472A Active JP4895795B2 (en) | 2006-12-20 | 2006-12-20 | Manufacturing method of multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4895795B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5322531B2 (en) * | 2008-05-27 | 2013-10-23 | 新光電気工業株式会社 | Wiring board manufacturing method |
| JP5298740B2 (en) * | 2008-09-30 | 2013-09-25 | 富士通株式会社 | Multilayer circuit board manufacturing method |
| TWI490120B (en) * | 2011-09-30 | 2015-07-01 | Zeon Corp | Insulating film, prepreg, laminate, hardened, and composite |
| JP6057641B2 (en) | 2012-09-20 | 2017-01-11 | 新光電気工業株式会社 | Wiring board and manufacturing method thereof |
| JP2015138922A (en) * | 2014-01-24 | 2015-07-30 | 日本ゼオン株式会社 | Substrate for electronic material and manufacturing method thereof |
| JP2015138921A (en) * | 2014-01-24 | 2015-07-30 | 日本ゼオン株式会社 | Substrate for electronic material |
| JP2016051756A (en) * | 2014-08-29 | 2016-04-11 | 日本ゼオン株式会社 | Multilayer printed wiring board and method of manufacturing the same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4291469B2 (en) * | 1999-09-29 | 2009-07-08 | イビデン株式会社 | Multilayer printed wiring board and manufacturing method thereof |
| JP2001284821A (en) * | 2000-03-30 | 2001-10-12 | Nippon Zeon Co Ltd | Multilayer circuit board |
| WO2004086833A1 (en) * | 2003-03-27 | 2004-10-07 | Zeon Corporation | Printed wiring board, its manufacturing method, and curing resin molded article with support |
| JP2006278922A (en) * | 2005-03-30 | 2006-10-12 | Nippon Zeon Co Ltd | Manufacturing method for multilayer circuit board |
-
2006
- 2006-12-20 JP JP2006342472A patent/JP4895795B2/en active Active
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