JP2008147510A - Flip-chip mounting method - Google Patents

Flip-chip mounting method Download PDF

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JP2008147510A
JP2008147510A JP2006334587A JP2006334587A JP2008147510A JP 2008147510 A JP2008147510 A JP 2008147510A JP 2006334587 A JP2006334587 A JP 2006334587A JP 2006334587 A JP2006334587 A JP 2006334587A JP 2008147510 A JP2008147510 A JP 2008147510A
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circuit board
resin composition
semiconductor chip
sealing filler
printed circuit
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JP4876882B2 (en
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Osamu Matsuzaka
治 松坂
Takemi Okubo
健実 大久保
Rieishi Hayashi
理英子 林
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Resonac Corp
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Hitachi Chemical Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

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  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flip-chip mounting method for eliminating voids generated in a heat bonding process by overheating a semiconductor device for which bonding is completed altogether again. <P>SOLUTION: In the flip-chip mounting method, a semiconductor chip 10 and a wiring circuit board 1 are bonded by heating and press-fixing the bump 12 of the semiconductor chip 10 and metal plating 3 which is the electrode of the wiring circuit board 1 and they are sealed by resin compositions 6, 6A and 6B for a sealing filler interposed between them. Then, by heating at least a part of the semiconductor chip 10 and the wiring circuit board 1 to such a temperature that the resin compositions 6, 6A and 6B for the sealing filler, the voids inside the resin compositions 6, 6A and 6B for the sealing filler are eliminated. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

本発明は、半導体素子をフェイスダウン方式で配線回路基板に実装する半導体素子のフリップチップ実装方法に関する。   The present invention relates to a flip-chip mounting method for a semiconductor element in which a semiconductor element is mounted on a printed circuit board in a face-down manner.

電子機器の小型化、軽量化や薄型化が進み、それに伴い半導体素子及び配線回路基板の小型化、軽量化及び薄型化も求められている。一般的に、半導体素子は配線回路基板上に実装される。半導体素子を配線回路基板上に実装する方法として、半導体素子のバンプと配線回路基板の電極とを、半田や共晶金属を用いて接合させて導通させるフリップチップ実装方法が用いられている。また、配線回路基板の小型化、軽量化及び薄型化のために、配線回路基板材料はガラスエポキシのようなリジッドな材料からポリイミドフィルムなどのフレキシブルな材料へと移行している。   As electronic devices become smaller, lighter, and thinner, semiconductor devices and printed circuit boards are required to be smaller, lighter, and thinner. Generally, a semiconductor element is mounted on a printed circuit board. As a method of mounting a semiconductor element on a printed circuit board, a flip chip mounting method is used in which bumps of the semiconductor element and electrodes of the printed circuit board are joined and connected using solder or a eutectic metal. Further, in order to reduce the size, weight, and thickness of the printed circuit board, the printed circuit board material has shifted from a rigid material such as glass epoxy to a flexible material such as polyimide film.

前記フリップチップ実装方法では、半導体素子と配線回路基板の線膨張係数の差から熱衝撃に対する接続信頼性に問題があり、この改善のため半導体素子と配線回路基板の間に封止充填材を用いるのが一般的である。この封止充填材により、接合部分に発生する応力を緩和し接続信頼性を高めている。   In the flip chip mounting method, there is a problem in connection reliability against thermal shock due to the difference in coefficient of linear expansion between the semiconductor element and the printed circuit board. To improve this, a sealing filler is used between the semiconductor element and the printed circuit board. It is common. With this sealing filler, stress generated at the joint is relaxed and connection reliability is improved.

従来の封止充填材をフリップチップ実装時に形成する方法は、半導体素子と配線回路基板を高温度で接合した後に、その間隙を低粘度の熱硬化性液状樹脂組成物を毛細管現象により注入、充填し、熱硬化する方法が用いられていた。しかしこの方法では、配線間隙や半導体素子と配線基板との間隙がさらに狭まると(ファインピッチ化)、作業効率の低下や、充填が困難になるという問題があった。   A conventional method of forming a sealing filler at the time of flip-chip mounting is to join a semiconductor element and a printed circuit board at a high temperature, and then inject and fill a gap with a low-viscosity thermosetting liquid resin composition by capillary action. However, a method of thermosetting has been used. However, this method has a problem that if the wiring gap or the gap between the semiconductor element and the wiring board is further narrowed (fine pitch), the working efficiency is lowered and filling becomes difficult.

そのため、接合直前に予め熱硬化性液状樹脂組成物を半導体素子又は配線回路基板の所定の位置に塗布、又は貼付けしておき、その後に半導体素子の電極と配線回路基板の電極とを加熱圧着することにより間隙を封止充填する方法が検討されている。   Therefore, a thermosetting liquid resin composition is previously applied or pasted to a predetermined position of a semiconductor element or a printed circuit board immediately before bonding, and then the electrode of the semiconductor element and the electrode of the printed circuit board are thermocompression bonded. Thus, a method for sealing and filling the gap has been studied.

この方法に好適に用いられる封止充填材には、塗布、貼付け時に適度な厚みを保持できること、加熱接合する際に適度な流れ性を持って半導体素子と配線回路基板の間隙を隙間無く充填できること、接合時の加熱による分解や発泡がないこと、適当な温度及び速度で固化すること、固化した時に電気絶縁性が高く、配線回路基板上の電極への腐食要因を有しないこと、配線回路基板、半導体素子、ソルダレジストなどの周辺部材間の応力緩和のため弾性率が小さいことが求められている。   The sealing filler suitably used in this method can maintain an appropriate thickness during application and pasting, and can fill the gap between the semiconductor element and the printed circuit board without gaps with an appropriate flowability when heated and bonded.・ No decomposition or foaming due to heating at the time of joining, solidification at an appropriate temperature and speed, high electrical insulation when solidified, no corrosive factor to the electrodes on the wiring circuit board, wiring circuit board In order to relieve stress between peripheral members such as semiconductor elements and solder resists, a low elastic modulus is required.

このような封止充填材としては、エポキシ樹脂系熱硬化性樹脂が好適に用いられており、弾性率を下げる試みがなされている(特許文献1)。また、熱硬化性樹脂フィルムを用いる試みもなされている(特許文献2)。   As such a sealing filler, an epoxy resin-based thermosetting resin is suitably used, and attempts have been made to lower the elastic modulus (Patent Document 1). Attempts have also been made to use thermosetting resin films (Patent Document 2).

このように、予め封止充填材を配置しておくフリップチップ実装方法では、半導体素子と配線回路基板とを加熱接合、超音波接合する際に発生するボイドが問題とされた。ボイドは、接続信頼性や絶縁信頼性など、半導体装置の信頼性に不利な影響を及ぼすことがわかっている。これを抑制するため、加熱接合時に樹脂を含む半導体装置を冷却して圧力を開放することによりボイドを抑制するフリップチップ実装方法が提案されている(特許文献3)。また、硬化をほぼ完全に終了させ、樹脂を固化してから圧力を開放する方法も提案されている(特許文献4、特許文献5)。   As described above, in the flip chip mounting method in which the sealing filler is disposed in advance, a void generated when the semiconductor element and the printed circuit board are bonded by heat bonding or ultrasonic bonding has been a problem. It has been found that voids adversely affect the reliability of semiconductor devices such as connection reliability and insulation reliability. In order to suppress this, there has been proposed a flip chip mounting method that suppresses voids by cooling a semiconductor device containing a resin during heat bonding and releasing the pressure (Patent Document 3). There has also been proposed a method in which the curing is almost completely completed and the pressure is released after the resin is solidified (Patent Documents 4 and 5).

特開2004−10810号公報JP 2004-10810 A 特開2005−112916号公報JP 2005-112916 A 特許第3646056号明細書Japanese Patent No. 3646056 特開平11−282547号公報JP-A-11-282547 特開2005−48054号公報JP 2005-48054 A

予め封止充填材を配置しておくフリップチップ実装方法において、封止充填材中に生じるボイドはこれまでの文献の多くの場合、水分や樹脂中に内在する気泡、又は接合時に巻き込む気泡が原因とされてきた。しかしながら、本発明者の調査によれば、これらの気泡はほぼ接合時に充填材の流れにより排除でき、排除できないボイドの原因の多くは、バンプと配線を加熱加圧接合させた際、封止充填材が液状の状態のまま圧力を開放する際に発生するものであることが明らかとなった。   In the flip chip mounting method in which the sealing filler is arranged in advance, the voids generated in the sealing filler are often caused by bubbles contained in moisture or resin, or bubbles entrained during bonding. It has been said. However, according to the inventor's investigation, these bubbles can be almost eliminated by the flow of the filler at the time of joining. Many of the voids that cannot be eliminated are sealed and filled when the bump and the wiring are joined by heating and pressurizing. It was found that this occurs when the pressure is released while the material is in a liquid state.

本発明者の調査によれば、発生するボイドは封止充填材を固化させた状態で、接合時の圧力を開放すれば抑制できることがわかっている。すなわち、前述の特許文献3、4及び5では、その工程をボイド発生原因を知らずして行っていたと言うことになる。特許文献3、4及び5に記載されている方法では、ボイドを抑制できるものの接合時の温度制御に多大な時間を要し、生産性が低下するという課題があった。   According to the inventor's investigation, it has been found that the generated void can be suppressed by releasing the pressure at the time of joining in a state where the sealing filler is solidified. That is, in the above-mentioned Patent Documents 3, 4 and 5, the process is performed without knowing the cause of the void generation. In the methods described in Patent Documents 3, 4 and 5, although voids can be suppressed, temperature control at the time of joining requires a lot of time, and there is a problem that productivity is lowered.

本発明は、上記課題に鑑み、フリップチップ実装における半導体装置の製造効率を改善するため、加熱接合工程で発生したボイドを、接合完了した半導体装置を一括して再過熱して消滅させる半導体装置の製造方法として、フリップチップ実装方法を提供することを目的とするものである。   In order to improve the manufacturing efficiency of a semiconductor device in flip-chip mounting, the present invention is directed to a semiconductor device that eliminates voids generated in a heat bonding process by reheating and heating the semiconductor devices that have been bonded together. An object of the present invention is to provide a flip chip mounting method as a manufacturing method.

すなわち、本発明によるフリップチップ実装方法は、半導体チップ及び配線回路基板の間隙を封止充填剤用樹脂組成物で封止し、次いで、前記封止充填剤用樹脂組成物を溶融し得る温度に前記半導体チップ及び前記配線回路基板の少なくとも一部を加熱することにより、前記封止充填剤用樹脂組成物内のボイドを消失させることを特徴とする。   That is, in the flip chip mounting method according to the present invention, the gap between the semiconductor chip and the printed circuit board is sealed with the sealing filler resin composition, and then the sealing filler resin composition is melted. By heating at least a part of the semiconductor chip and the printed circuit board, voids in the resin composition for sealing filler are eliminated.

また、本発明によるフリップチップ実装方法にあっては、前記半導体チップ及び前記配線回路基板の少なくとも一方の対向面に前記封止充填剤用樹脂組成物を介在させ、前記半導体チップのバンプと前記配線回路基板の電極とを加熱圧着して前記半導体チップ及び前記配線回路基板を接合することにより、前記半導体チップ及び前記配線回路基板の間隙を前記封止充填剤用樹脂組成物で封止することを特徴とする。   Further, in the flip chip mounting method according to the present invention, the resin composition for sealing filler is interposed on at least one facing surface of the semiconductor chip and the printed circuit board, and the bump of the semiconductor chip and the wiring Sealing the gap between the semiconductor chip and the wired circuit board with the resin composition for sealing filler by bonding the electrodes of the circuit board by thermocompression bonding to the semiconductor chip and the wired circuit board. Features.

また、本発明によるフリップチップ実装方法にあっては、半導体ウエハ上に封止充填剤用樹脂組成物を塗布又は貼り付け、前記半導体ウエハをダイシングして半導体チップを作製し、前記封止充填剤用樹脂組成物が塗布又は貼り付けられた面の前記半導体チップを配線回路基板に対向させて積層し、前記半導体チップのバンプと前記配線回路基板の電極とを加熱圧着して前記半導体チップ及び前記配線回路基板を接合し、前記半導体チップ及び前記配線回路基板の間隙を前記封止充填剤用樹脂組成物で封止し、次いで、前記封止充填剤用樹脂組成物を溶融し得る温度に前記半導体チップ及び前記配線回路基板の少なくとも一部を加熱することにより、前記封止充填剤用樹脂組成物内のボイドを消失させることを特徴とする。   Further, in the flip chip mounting method according to the present invention, a resin composition for a sealing filler is applied or pasted on a semiconductor wafer, the semiconductor wafer is diced to produce a semiconductor chip, and the sealing filler The semiconductor chip on the surface to which the resin composition for application or application is applied is laminated so as to face the wiring circuit board, and the bumps of the semiconductor chip and the electrodes of the wiring circuit board are heat-pressed to bond the semiconductor chip and the semiconductor chip. Bonding the printed circuit board, sealing the gap between the semiconductor chip and the printed circuit board with the resin composition for sealing filler, and then to a temperature at which the resin composition for sealing filler can be melted By heating at least a part of the semiconductor chip and the printed circuit board, voids in the resin composition for sealing filler are eliminated.

また、本発明によるフリップチップ実装方法にあっては、前記半導体チップ及び前記配線回路基板の少なくとも一部を加熱する温度が、100℃〜350℃であることを特徴とする。   In the flip chip mounting method according to the present invention, the temperature for heating at least a part of the semiconductor chip and the printed circuit board is 100 ° C. to 350 ° C.

また、本発明によるフリップチップ実装方法にあっては、前記半導体チップ及び前記配線回路基板の少なくとも一部を加熱する時間が、2分〜360分であることを特徴とする。   In the flip chip mounting method according to the present invention, the time for heating at least a part of the semiconductor chip and the printed circuit board is 2 minutes to 360 minutes.

また、本発明によるフリップチップ実装方法にあっては、前記配線回路基板がフレキシブルプリント基板であることを特徴とする。   In the flip chip mounting method according to the present invention, the printed circuit board is a flexible printed board.

また、本発明によるフリップチップ実装方法にあっては、前記封止充填剤用樹脂組成物が、熱可塑性樹脂を含むことを特徴とする。   In the flip chip mounting method according to the present invention, the sealing filler resin composition contains a thermoplastic resin.

また、本発明によるフリップチップ実装方法にあっては、前記熱可塑性樹脂が、ポリオレフィン系熱可塑性樹脂であることを特徴とする。   The flip chip mounting method according to the present invention is characterized in that the thermoplastic resin is a polyolefin-based thermoplastic resin.

本発明によれば、封止充填剤用樹脂組成物を溶融し得る温度に半導体チップ及び配線回路基板の少なくとも一部を加熱することにより、封止充填剤用樹脂組成物内のボイドを消失させるので、短時間でボイドを消失させることができ、ボイドレスの半導体装置の製造効率を向上することができるという効果を奏する。   According to the present invention, voids in the resin composition for sealing filler are eliminated by heating at least a part of the semiconductor chip and the printed circuit board to a temperature at which the resin composition for sealing filler can be melted. Therefore, the void can be eliminated in a short time, and the manufacturing efficiency of the voidless semiconductor device can be improved.

以下、図面に基づき、本発明によるフリップチップ実装方法をその好適な実施の形態に即して詳細に説明する。なお、本発明は以下の実施の形態に限定されるものではない。   Hereinafter, a flip chip mounting method according to the present invention will be described in detail with reference to the drawings in accordance with a preferred embodiment. Note that the present invention is not limited to the following embodiments.

[実施の形態1]
図1〜図7は、配線回路基板上に封止充填剤用樹脂組成物を介在させ半導体チップ及び配線回路基板を接合する、実施の形態1によるフリップチップ実装方法のプロセスを説明する概略断面図である。なお、各図中、同一符号は同一又は相当部分を示す。
[Embodiment 1]
1 to 7 are schematic cross-sectional views illustrating a process of a flip chip mounting method according to the first embodiment in which a semiconductor chip and a printed circuit board are bonded to each other with a resin composition for sealing filler interposed on the printed circuit board. It is. In addition, in each figure, the same code | symbol shows the same or equivalent part.

図1に示すように、配線回路基板として例えばフィルム状基材1の上面には、半導体チップが実装される部分等を除いて銅配線2が形成されており、この銅配線2上の所定部分にはすず又は金などの金属めっき3が施されている。配線回路基板は、フィルム状基材1に限らず、種々の回路基板を使用することができる。また、金属めっき3としては、すず又は金めっきを好適に使用できるが、他の金属のめっきであっても良く、同様に使用できる。さらに、接合部分以外のパターンなどの保護膜として、耐熱性コーティング材であるソルダーレジスト4が銅配線2上に形成されている。   As shown in FIG. 1, a copper wiring 2 is formed on a top surface of a film-like base material 1 as a wiring circuit board, excluding a portion where a semiconductor chip is mounted, and a predetermined portion on the copper wiring 2. Is provided with a metal plating 3 such as tin or gold. The printed circuit board is not limited to the film-like substrate 1, and various circuit boards can be used. Further, as the metal plating 3, tin or gold plating can be suitably used, but plating of other metals may be used and can be used in the same manner. Further, a solder resist 4 that is a heat-resistant coating material is formed on the copper wiring 2 as a protective film such as a pattern other than the joint portion.

一般的な滴下、塗布法としてはディスペンスが挙げられ、塗布前の封止充填剤用樹脂組成物を溶融温度まで加温して液状にすることで塗布が可能となる。加熱温度としては、140℃〜250℃が好ましく、160℃〜220℃がより好ましい。   Dispensing is mentioned as a general dripping and application method, and application is possible by heating the resin composition for sealing filler before application to the melting temperature to make it liquid. As heating temperature, 140 to 250 degreeC is preferable and 160 to 220 degreeC is more preferable.

例えば、図2に示すように、フィルム状基材1の半導体チップが実装される実装位置5を覆って、ディスペンサノズル100により液状の封止充填剤用樹脂組成物6を滴下する。封止充填剤用樹脂組成物6は、半導体チップとフィルム状基材1との距離、半導体チップの大きさなどに応じて、所望の厚さ、形状で滴下することができる。   For example, as shown in FIG. 2, a liquid resin composition 6 for sealing filler is dropped by a dispenser nozzle 100 so as to cover the mounting position 5 where the semiconductor chip of the film-like substrate 1 is mounted. The resin composition 6 for sealing filler can be dripped with a desired thickness and shape according to the distance between the semiconductor chip and the film-like substrate 1, the size of the semiconductor chip, and the like.

或いは、図3及び図4に示すように、シート状の封止充填剤用樹脂組成物6Aを貼り付け、ローラー200により仮圧着することにより、封止充填剤用樹脂組成物6Aを所定の実装位置5に配置することができる。ここで、封止充填剤用樹脂組成物6Aの貼り付け性を良好にするために、仮圧着時に適度な熱を加えてもよい。さらに、図5に示すように、例えばフィルム状基材1の半導体チップが実装される実装位置5に、ペレット状の封止充填剤用樹脂組成物6Bを配置することも可能である。図2に示した液状の封止充填剤用樹脂組成物6や、図5に示したペレット状の封止充填剤用樹脂組成物6Bは、必要に応じて押圧部材(図示しない)により図4に示すように平坦にする工程を含んでもよい。なお、封止充填剤用樹脂組成物の塗布、滴下、貼り付けなどの方法や条件は、特に限定されず、種々の方法を採用することができる。また、フィルム状基材1と半導体チップ10との間に介在させる封止充填剤用樹脂組成物6、6A、6Bの厚さは、一般的に配線の高さ等に依存するが、約50〜150μmである。   Alternatively, as shown in FIGS. 3 and 4, the sealing filler resin composition 6 </ b> A is mounted in a predetermined manner by sticking a sheet-like sealing filler resin composition 6 </ b> A and temporarily pressing the roller 200 with the resin composition 6 </ b> A. It can be placed at position 5. Here, in order to improve the sticking property of the sealing filler resin composition 6A, moderate heat may be applied at the time of provisional pressure bonding. Furthermore, as shown in FIG. 5, it is also possible to arrange | position the pellet-shaped resin composition 6B for sealing fillers in the mounting position 5 in which the semiconductor chip of the film-form base material 1 is mounted, for example. The liquid sealing filler resin composition 6 shown in FIG. 2 and the pellet-shaped sealing filler resin composition 6B shown in FIG. 5 are pressed by a pressing member (not shown) as needed. The step of flattening may be included as shown in FIG. In addition, the method and conditions, such as application | coating of a resin composition for sealing fillers, dripping, and affixing, are not specifically limited, A various method is employable. Further, the thickness of the resin composition 6, 6A, 6B for sealing filler interposed between the film-like substrate 1 and the semiconductor chip 10 generally depends on the height of the wiring, etc., but is about 50. ~ 150 μm.

半導体チップ10には、図6に示すように、その下面にメタルポスト11を介してバンプ12が形成されている。バンプ12が形成されている半導体チップ10の下面を、封止充填剤用樹脂組成物6、6A、6Bが配置され金属めっき3が形成されているフィルム状基材1の上面に対向させ、所定温度で加熱しながらこれらの半導体チップ10とフィルム状基材1とを押圧装置15によって押圧する。この時、超音波などを印加して接合しても良く、このような超音波接合によって均一な封止充填剤用樹脂組成物6、6A、6Bの層が形成され、実装状態のバラツキを抑えることができる。   As shown in FIG. 6, the semiconductor chip 10 has bumps 12 formed on its lower surface via metal posts 11. The lower surface of the semiconductor chip 10 on which the bumps 12 are formed is opposed to the upper surface of the film-like substrate 1 on which the resin composition 6, 6 </ b> A, 6 </ b> B for sealing filler is disposed and the metal plating 3 is formed. The semiconductor chip 10 and the film-like substrate 1 are pressed by the pressing device 15 while being heated at a temperature. At this time, an ultrasonic wave or the like may be applied for bonding, and a uniform layer of the resin composition for sealing filler 6, 6A, 6B is formed by such ultrasonic bonding, and variation in mounting state is suppressed. be able to.

以上のようにして、図7に示すように、半導体チップ10のバンプ12とフィルム状基材1の金属めっき3とが接合され、かつバンプ12と金属めっき3との接合部の近傍を封止充填剤用樹脂組成物6、6A、6Bが充填、封止されたフリップチップ実装品20を製造することができる。   As described above, as shown in FIG. 7, the bump 12 of the semiconductor chip 10 and the metal plating 3 of the film-like substrate 1 are bonded, and the vicinity of the bonding portion between the bump 12 and the metal plating 3 is sealed. The flip chip mounting product 20 filled and sealed with the resin composition for filler 6, 6A, 6B can be manufactured.

続いて、封止充填剤用樹脂組成物6、6A、6Bを溶融し得る温度に半導体チップ及び配線回路基板の少なくとも一部を加熱すること(以下、加熱工程とする)により、封止充填剤用樹脂組成物内のボイドを消失させる工程を行う。   Subsequently, the sealing filler is heated by heating at least a part of the semiconductor chip and the printed circuit board to a temperature at which the resin composition for sealing filler 6, 6A, 6B can be melted (hereinafter referred to as a heating step). A step of eliminating voids in the resin composition for use.

封止充填材樹脂組成物を予め配置しておくフリップチップ実装方法においては、加熱接合時にかかる圧力が、封止充填剤用樹脂組成物が溶融した状態で開放されることにより、半導体素子と配線基板の間にスプリングバックによるボイドが生じる。発生したボイドは、外部より侵入した空気等を原因とするものではなく、内部より発生する真空のボイドである。   In the flip chip mounting method in which the sealing filler resin composition is preliminarily disposed, the pressure applied during the heat bonding is released in a state where the sealing filler resin composition is melted, so that the semiconductor element and the wiring A void caused by springback occurs between the substrates. The generated void is not caused by air or the like entering from the outside, but is a vacuum void generated from the inside.

本発明は、加熱接合工程で発生したボイドを、接合完了した半導体装置(半導体チップ及び配線回路基板)の少なくとも一部を一括して再過熱することにより、消滅させるものである。すなわち、半導体チップ及び配線回路基板を接合した後に、半導体チップを搭載した配線回路基板全体又は一部を加熱する工程を設けて、半導体装置中の封止充填材樹脂組成物を溶融させることにより、ボイドを消失させることが可能となる。   The present invention eliminates voids generated in the heat bonding step by collectively reheating at least part of the semiconductor devices (semiconductor chip and wiring circuit board) that have been bonded together. That is, after bonding the semiconductor chip and the printed circuit board, by providing a step of heating the whole or a part of the printed circuit board on which the semiconductor chip is mounted, by melting the sealing filler resin composition in the semiconductor device, It becomes possible to eliminate voids.

本発明における加熱工程の加熱は、100℃〜350℃の範囲の温度で行う。さらに、加熱温度は120℃〜300℃が好ましく、150℃〜250℃がより好ましく、180℃〜220℃が特に好ましい。加熱温度が100℃未満では、ボイドの消失が十分ではなく、350℃を超えると封止充填剤用樹脂組成物が流れ出す可能性があるので好ましくない。   Heating in the heating step in the present invention is performed at a temperature in the range of 100 ° C to 350 ° C. Furthermore, the heating temperature is preferably 120 ° C to 300 ° C, more preferably 150 ° C to 250 ° C, and particularly preferably 180 ° C to 220 ° C. When the heating temperature is less than 100 ° C., void disappearance is not sufficient, and when it exceeds 350 ° C., the resin composition for sealing filler may flow out, which is not preferable.

また、加熱工程における加熱時間は、封止充填剤用樹脂組成物に用いる樹脂の融点にもよるが、2分間〜360分間が好ましく、5分間〜120分間がより好ましく、10分〜60分間が特に好ましい。加熱時間が2分間未満では、ボイドの消失が十分ではなく、360分間を超えることなくボイドは消失させることができるので、実装時間を短縮するために360分間以内とすることが好ましい。   Moreover, although the heating time in a heating process is based also on melting | fusing point of resin used for the resin composition for sealing fillers, 2 minutes-360 minutes are preferable, 5 minutes-120 minutes are more preferable, 10 minutes-60 minutes are Particularly preferred. If the heating time is less than 2 minutes, voids are not sufficiently lost, and voids can be eliminated without exceeding 360 minutes. Therefore, in order to shorten the mounting time, it is preferable that the voids be within 360 minutes.

以上のような加熱工程によって、接合信頼性や絶縁信頼性など半導体装置の信頼性に不利な影響を及ぼすボイドを除去することが可能となる。従って、信頼性の高い半導体装置を製造することが可能となる。   By the heating process as described above, it is possible to remove voids that adversely affect the reliability of the semiconductor device, such as bonding reliability and insulation reliability. Therefore, a highly reliable semiconductor device can be manufactured.

本発明に用いる封止充填剤用樹脂組成物としては、熱可塑性樹脂を含むことが好ましい。熱可塑性樹脂としては、例えば、ポリオレフィン、ポリフッ化ビニリデン、ポリエステル、ポリアクリロニトリル、ポリスチレン、ポリアミド、ポリイミド、ポリフェニレン等が挙げられるが、半導体装置の耐熱温度以下で溶融する樹脂であれば、その種類を問わない。これらの熱可塑性樹脂は、使用条件、例えば、使用温度に合わせて、一種を単独で又は二種以上を組み合わせて用いることができる。熱可塑性樹脂は安定性に優れるため、配線回路基板又は半導体チップに予め封止充填材樹脂組成物を塗布、滴下、貼り付けした後、加熱接合までの放置時間に制限はない。   The resin composition for sealing filler used in the present invention preferably contains a thermoplastic resin. Examples of the thermoplastic resin include polyolefin, polyvinylidene fluoride, polyester, polyacrylonitrile, polystyrene, polyamide, polyimide, polyphenylene, and the like. Any resin can be used as long as it melts at a temperature lower than the heat resistance temperature of the semiconductor device. Absent. These thermoplastic resins can be used individually by 1 type or in combination of 2 or more types according to use conditions, for example, use temperature. Since the thermoplastic resin is excellent in stability, there is no limitation on the standing time until the heat bonding after the sealing filler resin composition is applied, dropped, and pasted to the printed circuit board or the semiconductor chip in advance.

また、本発明に用いる封止充填材樹脂組成物には、耐熱安定性等の特性をさらに向上させるため、多種の添加剤を配合することができる。このような添加剤としては、例えば、消泡剤、シランカップリング剤、無機あるいは有機フィラー、顔料等が挙げられる。   Moreover, in order to further improve characteristics, such as heat-resistant stability, the sealing filler resin composition used for this invention can be mix | blended with various additives. Examples of such additives include antifoaming agents, silane coupling agents, inorganic or organic fillers, and pigments.

一般に、電気絶縁性は交流絶縁の場合、樹脂の誘電率との相関があり、封止充填材用樹脂組成物には極性の低い樹脂を用いることが好ましい。また、高温高湿下での連続電圧印加試験における配線回路基板の電極腐食は、封止充填材用樹脂組成物の吸水性、等湿度との相関があるため、水分との親和性が低い極性基の少ない樹脂を用いることが好ましい。   Generally, in the case of AC insulation, the electrical insulation has a correlation with the dielectric constant of the resin, and it is preferable to use a resin having a low polarity for the resin composition for sealing filler. In addition, the electrode corrosion of the printed circuit board in the continuous voltage application test under high temperature and high humidity has a correlation with the water absorption and isohumidity of the resin composition for the sealing filler, and therefore has a low affinity for moisture. It is preferable to use a resin having a small number of groups.

[実施の形態2]
図8〜図12は、半導体チップに封止充填剤用樹脂組成物を配置して半導体チップ及び配線回路基板を接合する実施の形態2によるフリップチップ実装方法のプロセスを説明する概略断面図である。
[Embodiment 2]
8 to 12 are schematic cross-sectional views for explaining a process of the flip chip mounting method according to the second embodiment in which the resin composition for the sealing filler is arranged on the semiconductor chip and the semiconductor chip and the printed circuit board are bonded together. .

実施の形態1では、封止充填剤用樹脂組成物を配線回路基板上に配置して半導体チップ及び配線回路基板を接合する場合について説明したが、実施の形態2では、ダイシングを行う前の半導体ウエハ例えばシリコンウエハに封止充填剤用樹脂組成物を配置する場合について説明する。   In the first embodiment, the case where the resin composition for the sealing filler is disposed on the wiring circuit board and the semiconductor chip and the wiring circuit board are joined is described. In the second embodiment, the semiconductor before dicing is performed. The case where the resin composition for sealing fillers is arrange | positioned to a wafer, for example, a silicon wafer is demonstrated.

まず、図8に示すように、シリコンウエハ50上にシート状の封止充填剤用樹脂組成物6Cを例えばラミネータ(図示しない)により貼り付ける。また、液状の封止充填剤用樹脂組成物6Dをシリコンウエハ50上に塗布する場合には、図9に示すように、回転しているシリコンウエハ50上にスピンコートノズル300から液状の封止充填剤用樹脂組成物6Dを滴下することにより、均一な膜状の封止充填剤用樹脂組成物6Dを塗布することができる。   First, as shown in FIG. 8, a sheet-like resin composition 6C for sealing filler is affixed on the silicon wafer 50 using, for example, a laminator (not shown). Further, when the liquid sealing filler resin composition 6D is applied onto the silicon wafer 50, as shown in FIG. 9, the liquid sealing is applied from the spin coat nozzle 300 onto the rotating silicon wafer 50. By dropping the resin composition for filler 6D, a uniform film-like resin composition for sealing filler 6D can be applied.

次に、図10に示すように、ダイシングによりシリコンウエハ50を多数の半導体チップ10に切り分け、図11に示すように、各半導体チップ10に封止充填剤用樹脂組成物6C、6Dが塗布又は貼り付けられた状態となる。なお、図11では、半導体チップ10に設けられたメタルポスト11やバンプ12は、図示を省略している。   Next, as shown in FIG. 10, the silicon wafer 50 is cut into a large number of semiconductor chips 10 by dicing, and as shown in FIG. 11, the resin compositions 6C and 6D for sealing filler are applied to each semiconductor chip 10 or It will be in the pasted state. In FIG. 11, illustration of the metal posts 11 and the bumps 12 provided on the semiconductor chip 10 is omitted.

次いで、図12に示すように、バンプ12が形成され封止充填剤用樹脂組成物6C、6Dが塗布又は貼り付けられた半導体チップ10の下面を、金属めっき3が形成されているフィルム状基材1の上面に対向させ、所定温度で加熱しながらこれらの半導体チップ10とフィルム状基材1とを押圧装置15によって押圧する。この時、超音波などを印加して接合しても良い点は、実施の形態1と同様である。   Next, as shown in FIG. 12, the lower surface of the semiconductor chip 10 on which the bumps 12 are formed and the sealing filler resin compositions 6C and 6D are applied or pasted is formed on the film-like substrate on which the metal plating 3 is formed. The semiconductor chip 10 and the film-like substrate 1 are pressed by the pressing device 15 while facing the upper surface of the material 1 and heating at a predetermined temperature. At this time, it is the same as in Embodiment 1 that ultrasonic waves may be applied for bonding.

以上のようにして、半導体チップ10のバンプ12とフィルム状基材1の金属めっき3とが接合され、かつバンプ12と金属めっき3との接合部の近傍を封止充填剤用樹脂組成物6C、6Dで充填、封止されたフリップチップ実装品30を製造することができる。   As described above, the bump 12 of the semiconductor chip 10 and the metal plating 3 of the film-like substrate 1 are bonded, and the vicinity of the bonding portion between the bump 12 and the metal plating 3 is sealed with a resin composition 6C for sealing filler. The flip chip mounting product 30 filled and sealed with 6D can be manufactured.

続いて、封止充填剤用樹脂組成物6C、6Dを溶融し得る温度に半導体チップ及び配線回路基板の少なくとも一部を加熱する加熱工程により、封止充填剤用樹脂組成物6C、6D内のボイドを消失させる工程を行う。加熱工程は、加熱温度や加熱時間など実施の形態1と同様な条件で行うことができるので、説明は省略する。また、封止充填剤用樹脂組成物や他の添加剤についても、実施の形態1と同様な材料を使用することができるので、説明を省略する。   Subsequently, the sealing filler resin compositions 6C and 6D are heated by heating at least a part of the semiconductor chip and the printed circuit board to a temperature at which the sealing filler resin compositions 6C and 6D can be melted. A step of eliminating voids is performed. Since the heating step can be performed under the same conditions as in the first embodiment, such as the heating temperature and the heating time, description thereof is omitted. Moreover, since the same material as Embodiment 1 can be used also about the resin composition for sealing fillers and another additive, description is abbreviate | omitted.

実施の形態2では、半導体ウエハに予め封止充填剤用樹脂組成物を塗布又は貼り付けるので、半導体ウエハに一括して封止充填剤用樹脂組成物を配置することができるので、実装作業を効率的に行うことができる。   In Embodiment 2, since the sealing filler resin composition is applied or pasted to the semiconductor wafer in advance, the sealing filler resin composition can be collectively disposed on the semiconductor wafer, so that the mounting operation is performed. Can be done efficiently.

以下に、本発明を実施例に基づいてさらに具体的に説明する。ただし、本発明は実施例により何ら限定されるものではない。   Hereinafter, the present invention will be described more specifically based on examples. However, the present invention is not limited to the examples.

(実装試験片作製法)
試験用フレキシブル基板JKIT COF TEG 30−A(株式会社日立超LSIシステムズ製、ソルダレジスト:日立化成株式会社製、商品名:SN−9000塗布品)に、封止充填材樹脂組成物を塗布、又は貼付けし、専用のTEGチップJTEG Phase6 30を、熱超音波併用フリップチップボンダーで、ヘッド温度200℃、ステージ温度80℃、圧力180N/チップの条件で、1.5秒間加熱圧着した。なお、上記封止充填剤用樹脂組成物は、後述する封止充填剤用樹脂組成物A〜D(以下、組成物A〜Dとする)を使用した。その後、さらに0.5秒間振幅3μmで超音波接合して、実装した試験用半導体装置のサンプル(試験片)を作製した。
(Mounting specimen preparation method)
Apply a sealing filler resin composition to a flexible substrate for testing JKIT COF TEG 30-A (manufactured by Hitachi ULSI Systems Co., Ltd., solder resist: manufactured by Hitachi Chemical Co., Ltd., product name: SN-9000 coated product), or A special TEG chip, JTEG Phase630, was bonded by thermo-compression using a thermal ultrasonic combined flip chip bonder for 1.5 seconds under the conditions of a head temperature of 200 ° C., a stage temperature of 80 ° C., and a pressure of 180 N / chip. In addition, the resin composition for sealing fillers to be described later was used as the resin composition for sealing fillers (hereinafter referred to as compositions A to D). Thereafter, ultrasonic bonding was performed with an amplitude of 3 μm for 0.5 seconds to prepare a sample (test piece) of the mounted test semiconductor device.

続いて、作製したサンプルを下記の条件a〜dによりホットプレート上で加熱処理した。
条件a:200℃、30分
条件b:175℃、60分
条件c:250℃、20分
条件d:加熱処理なし
Subsequently, the prepared sample was heat-treated on a hot plate under the following conditions a to d.
Condition a: 200 ° C., 30 minutes Condition b: 175 ° C., 60 minutes Condition c: 250 ° C., 20 minutes Condition d: No heat treatment

組成物A
上記封止充填剤用樹脂組成物として、ポリプロピレン−テルペン樹脂系熱可塑性樹脂組成物(日立化成ポリマー株式会社製、商品名:ハイボンYH171−7P)を用いて上記評価用試験片を作製した。
Composition A
As the sealing filler resin composition, a polypropylene-terpene resin-based thermoplastic resin composition (manufactured by Hitachi Chemical Polymer Co., Ltd., trade name: Hibon YH171-7P) was used to prepare the test piece for evaluation.

組成物B
上記封止充填剤用樹脂組成物として、ポリアミド系熱可塑性樹脂組成物(日立化成ポリマー株式会社製、商品名:ハイボンXH055−6)を用いて、上記評価用試験片を作製した。
Composition B
The test piece for evaluation was prepared using a polyamide-based thermoplastic resin composition (manufactured by Hitachi Chemical Co., Ltd., trade name: Hibon XH055-6) as the resin composition for sealing filler.

組成物C
上記封止充填剤用樹脂組成物として、スチレン−ブタジエン系ゴム熱可塑性樹脂組成物(日立化成ポリマー株式会社製、商品名:ハイボン9610)を用いて、上記評価用試験片を作製した。
Composition C
As the sealing filler resin composition, a styrene-butadiene rubber thermoplastic resin composition (manufactured by Hitachi Chemical Polymer Co., Ltd., trade name: Hibon 9610) was used to prepare the test piece for evaluation.

組成物D
上記封止充填剤用樹脂組成物として、エポキシ系熱硬化性樹脂組成物封止充填材(日立化成株式会社製、商品名:RC281C)を用いて上記評価用試験片を作製した。
Composition D
The test piece for evaluation was prepared using an epoxy thermosetting resin composition sealing filler (trade name: RC281C, manufactured by Hitachi Chemical Co., Ltd.) as the sealing filler resin composition.

(ボイド消滅の評価)
ボイド消滅の評価は、各サンプルを裏面から倍率100倍の顕微鏡を用いて観察し、ボイドの発生状況をそれぞれ二度評価した。ボイドの観察結果を表1に示す。表1中、3μm以上のボイドが観察されたものを×、3μm以上のボイドが観察されなかったものを○とした。
(Evaluation of void disappearance)
For evaluation of void disappearance, each sample was observed from the back surface using a microscope with a magnification of 100 times, and the occurrence of voids was evaluated twice. The observation results of voids are shown in Table 1. In Table 1, those in which voids of 3 μm or more were observed were evaluated as “×”, and those in which voids of 3 μm or more were not observed were evaluated as “◯”.

Figure 2008147510
Figure 2008147510

表1から明らかなように、実験例1〜3において、熱可塑性樹脂組成物を使用した封止充填剤用樹脂組成物では、200℃で30分の加熱処理によりボイドが消失した。これに対して、実験例4において、エポキシ系熱硬化性樹脂組成物を使用した封止充填剤用樹脂組成物では、200℃で30分の加熱処理によりボイドが消失しなかった。   As is clear from Table 1, in Experimental Examples 1 to 3, the voids disappeared in the sealing filler resin composition using the thermoplastic resin composition by heat treatment at 200 ° C. for 30 minutes. On the other hand, in Experimental Example 4, in the sealing filler resin composition using the epoxy thermosetting resin composition, voids did not disappear by heat treatment at 200 ° C. for 30 minutes.

以上のように、本発明よるフリップチップ実装方法は、封止充填剤用樹脂組成物を溶融し得る温度に半導体チップ及び配線回路基板の少なくとも一部を加熱することにより、封止充填剤用樹脂組成物内のボイドを消失させるので、ボイドレスの半導体装置の製造効率を向上することができる。また、接合信頼性や絶縁信頼性など信頼性の高い半導体装置の製造に適している。   As described above, the flip chip mounting method according to the present invention heats at least a part of the semiconductor chip and the printed circuit board to a temperature at which the resin composition for the sealing filler can be melted. Since voids in the composition are eliminated, the manufacturing efficiency of the voidless semiconductor device can be improved. Further, it is suitable for manufacturing a semiconductor device with high reliability such as bonding reliability and insulation reliability.

実施の形態1において、封止充填剤用樹脂組成物を塗布するフリップチップ実装方法のプロセスを説明する配線回路基板の概略断面図である。In Embodiment 1, it is a schematic sectional drawing of the wiring circuit board explaining the process of the flip-chip mounting method which apply | coats the resin composition for sealing fillers. 図1の配線回路基板に液状の封止充填剤用樹脂組成物を滴下した状態を示す概略断面図である。It is a schematic sectional drawing which shows the state which dripped the liquid resin composition for sealing fillers to the printed circuit board of FIG. 図1の配線回路基板にシート状の封止充填剤用樹脂組成物を貼り付けた状態を示す概略断面図である。It is a schematic sectional drawing which shows the state which affixed the sheet-like resin composition for sealing fillers on the printed circuit board of FIG. 図1の配線回路基板に封止充填剤用樹脂組成物を仮圧着した状態を示す概略断面図である。It is a schematic sectional drawing which shows the state which pressure-bonded the resin composition for sealing fillers to the printed circuit board of FIG. 図1の配線回路基板にペレット状の封止充填剤用樹脂組成物を配置した状態を示す概略断面図である。It is a schematic sectional drawing which shows the state which has arrange | positioned the pellet-form resin composition for sealing fillers to the printed circuit board of FIG. 半導体チップと配線回路基板とを封止充填剤用樹脂組成物を間に介在させて加熱圧着する状態を示す概略断面図である。It is a schematic sectional drawing which shows the state which heat-presses a semiconductor chip and a wiring circuit board by interposing the resin composition for sealing fillers in between. 半導体チップと配線回路基板とを封止充填剤用樹脂組成物で封止したフリップチップ実装品を示す概略断面図である。It is a schematic sectional drawing which shows the flip chip mounting goods which sealed the semiconductor chip and the wiring circuit board with the resin composition for sealing fillers. 実施の形態2において、シリコンウエハ上にシート状の封止充填剤用樹脂組成物を貼り付ける状態を示す概略斜視図である。In Embodiment 2, it is a schematic perspective view which shows the state which affixes the sheet-like resin composition for sealing fillers on a silicon wafer. シリコンウエハ上に液状の封止充填剤用樹脂組成物をスピンコートする状態を示す概略斜視図である。It is a schematic perspective view which shows the state which spin-coats the resin composition for liquid sealing fillers on a silicon wafer. 封止充填剤用樹脂組成物が貼り付け又は塗布されたシリコンウエハをダイシングする状態を示す概略斜視図である。It is a schematic perspective view which shows the state which dices the silicon wafer to which the resin composition for sealing fillers was affixed or apply | coated. 半導体チップを示す概略斜視図である。It is a schematic perspective view which shows a semiconductor chip. 半導体チップと配線回路基板とを封止充填剤用樹脂組成物で封止したフリップチップ実装品を示す概略断面図である。It is a schematic sectional drawing which shows the flip chip mounting goods which sealed the semiconductor chip and the wiring circuit board with the resin composition for sealing fillers.

符号の説明Explanation of symbols

1 フィルム状基材
2 銅配線
3 金属めっき
4 ソルダーレジスト
5 半導体チップの実装位置
6、6A〜6D 封止充填剤用樹脂組成物
10 半導体チップ
11 メタルポスト
12 バンプ
15 押圧装置
20、30 フリップチップ実装品
50 シリコンウエハ
100 ディスペンサノズル
200 ローラー
300 スピンコートノズル300
DESCRIPTION OF SYMBOLS 1 Film-like base material 2 Copper wiring 3 Metal plating 4 Solder resist 5 Semiconductor chip mounting position 6, 6A-6D Resin composition for sealing filler 10 Semiconductor chip 11 Metal post 12 Bump 15 Press device 20, 30 Flip chip mounting Product 50 Silicon wafer 100 Dispenser nozzle 200 Roller 300 Spin coat nozzle 300

Claims (8)

半導体チップ及び配線回路基板の間隙を封止充填剤用樹脂組成物で封止し、次いで、前記封止充填剤用樹脂組成物を溶融し得る温度に前記半導体チップ及び前記配線回路基板の少なくとも一部を加熱することにより、前記封止充填剤用樹脂組成物内のボイドを消失させることを特徴とするフリップチップ実装方法。   The gap between the semiconductor chip and the printed circuit board is sealed with a resin composition for sealing filler, and then at least one of the semiconductor chip and the printed circuit board at a temperature at which the resin composition for sealing filler can be melted. The void in the resin composition for sealing fillers is eliminated by heating a part, The flip chip mounting method characterized by the above-mentioned. 前記半導体チップ及び前記配線回路基板の少なくとも一方の対向面に前記封止充填剤用樹脂組成物を介在させ、前記半導体チップのバンプと前記配線回路基板の電極とを加熱圧着して前記半導体チップ及び前記配線回路基板を接合することにより、前記半導体チップ及び前記配線回路基板の間隙を前記封止充填剤用樹脂組成物で封止することを特徴とする請求項1に記載のフリップチップ実装方法。   The resin composition for sealing filler is interposed between at least one opposing surface of the semiconductor chip and the printed circuit board, and the semiconductor chip and the bump of the semiconductor chip and the electrode of the wired circuit board are thermocompression bonded. 2. The flip chip mounting method according to claim 1, wherein the gap between the semiconductor chip and the wired circuit board is sealed with the resin composition for sealing filler by bonding the wired circuit board. 半導体ウエハ上に封止充填剤用樹脂組成物を塗布又は貼り付け、前記半導体ウエハをダイシングして半導体チップを作製し、前記封止充填剤用樹脂組成物が塗布又は貼り付けられた面の前記半導体チップを配線回路基板に対向させて積層し、前記半導体チップのバンプと前記配線回路基板の電極とを加熱圧着して前記半導体チップ及び前記配線回路基板を接合し、前記半導体チップ及び前記配線回路基板の間隙を前記封止充填剤用樹脂組成物で封止し、次いで、前記封止充填剤用樹脂組成物を溶融し得る温度に前記半導体チップ及び前記配線回路基板の少なくとも一部を加熱することにより、前記封止充填剤用樹脂組成物内のボイドを消失させることを特徴とするフリップチップ実装方法。   A semiconductor composition for sealing filler is applied or pasted on a semiconductor wafer, a semiconductor chip is manufactured by dicing the semiconductor wafer, and the surface of the surface on which the resin composition for sealing filler is coated or pasted A semiconductor chip is stacked opposite to a wiring circuit board, and bumps of the semiconductor chip and electrodes of the wiring circuit board are thermocompression bonded to bond the semiconductor chip and the wiring circuit board, and the semiconductor chip and the wiring circuit The gap between the substrates is sealed with the resin composition for sealing filler, and then at least a part of the semiconductor chip and the printed circuit board is heated to a temperature at which the resin composition for sealing filler can be melted. By this, the void in the said resin composition for sealing fillers is lose | disappeared, The flip-chip mounting method characterized by the above-mentioned. 前記半導体チップ及び前記配線回路基板の少なくとも一部を加熱する温度は、100℃〜350℃であることを特徴とする請求項1から請求項3のうち、いずれか1項に記載のフリップチップ実装方法。   4. The flip-chip mounting according to claim 1, wherein a temperature for heating at least a part of the semiconductor chip and the printed circuit board is 100 ° C. to 350 ° C. 5. Method. 前記半導体チップ及び前記配線回路基板の少なくとも一部を加熱する時間は、2分〜360分であることを特徴とする請求項1から請求項4のうち、いずれか1項に記載のフリップチップ実装方法。   The flip chip mounting according to any one of claims 1 to 4, wherein a time for heating at least a part of the semiconductor chip and the printed circuit board is 2 minutes to 360 minutes. Method. 前記配線回路基板は、フレキシブルプリント基板であることを特徴とする請求項1から請求項5のうち、いずれか1項に記載のフリップチップ実装方法。   The flip-chip mounting method according to claim 1, wherein the printed circuit board is a flexible printed circuit board. 前記封止充填剤用樹脂組成物は、熱可塑性樹脂を含むことを特徴とする請求項1から請求項6のうち、いずれか1項に記載のフリップチップ実装方法。   The flip-chip mounting method according to claim 1, wherein the sealing filler resin composition includes a thermoplastic resin. 前記熱可塑性樹脂は、ポリオレフィン系熱可塑性樹脂であることを特徴とする請求項7に記載のフリップチップ実装方法。   The flip-chip mounting method according to claim 7, wherein the thermoplastic resin is a polyolefin-based thermoplastic resin.
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