JP2008147278A - Field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor capable of suppressing failure such as deterioration in output characteristics and obtaining good reliability. <P>SOLUTION: The field effect transistor includes an operating region 2 formed on a compound semiconductor substrate 1; gate electrodes 3 formed on the operating region 2; source electrodes 4 and drain electrodes 5 alternately formed on the operating region 2 with the gate electrode 3 sandwiched; a source pad 8 and a drain pad 9 to be used for connection to an external circuit; an air bridge 10 for connecting the source electrodes 4, electrodes 5, the source pad 8 and the drain pad 9; and slits 11 formed in the longitudinal direction of the source electrode 4 or the drain electrode 5 at least on the operating region side of the source electrode 4 or the drain electrode 5. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a compound semiconductor device such as GaAs, for example, and relates to a field effect transistor having an air bridge structure.

  In recent years, with higher functionality of inverter circuits and switching elements, field effect transistors (hereinafter referred to as Field Effect Transistors: FETs) are required to further improve high-frequency characteristics and reliability.

  For example, in an interdigital structure GaAsFET in which source electrodes and drain electrodes are alternately arranged, a gate wiring connected to a plurality of gate electrodes formed so as to cross the operation region and formed in parallel with the operation region, and an operation Source / drain wirings connecting the source electrode or drain electrode formed on the region and the bonding pad are formed. At this time, the gate wiring and the source / drain wiring cross each other. In order to insulate them, an air bridge structure in which an upper wiring is formed through a gap is adopted (for example, see Patent Document 1).

  In such an air bridge structure, an ohmic contact is formed as a source / drain electrode with a metal layer such as Pt / AuGe on the operation region, and then a metal layer such as Au / Pt / Ti is stacked thereon. Then, for example, an Au single layer plating layer is formed on the entire surface of the metal layer, the source / drain bonding pads, and the region connecting them. Since the Au constituting the air bridge formed in this way has a larger coefficient of thermal expansion than the GaAs substrate, it is possible to change from the plating temperature (for example, 60 ° C.) to the energized temperature (for example, 225 ° C. for acceleration evaluation conditions) When the temperature fluctuates like the time temperature (for example, normal temperature 25 ° C.), thermal expansion and thermal contraction occur in the air bridge. Due to such thermal expansion and contraction, large internal stresses such as compressive stress and tensile stress are generated in the operating region. As a result, problems such as output characteristics and deterioration of the passivation film formed in the upper layer occur, and it is difficult to obtain good reliability.

Until now, in order to relieve the stress generated in the semiconductor element at the time of assembly, a method such as providing a slit between unit cells has been used (see, for example, Patent Document 2). However, it does not mention the stress generated in the air bridge.
Japanese Patent Laid-Open No. 9-8064 (FIG. 1 etc.) JP-A-7-288299 (FIG. 1 and the like)

  An object of the present invention is to provide a field effect transistor capable of suppressing occurrence of problems such as deterioration of output characteristics and obtaining good reliability.

  According to one embodiment of the present invention, an operation region formed in a compound semiconductor substrate, a gate electrode formed on the operation region, and a source electrode and a drain electrode formed alternately on the operation region with the gate electrode interposed therebetween A source pad and a drain pad for connection to an external circuit, a source electrode, a drain electrode, an air bridge for connecting the source pad and the drain pad, and a source at least on the operation region side of the source electrode or the drain electrode A field effect transistor comprising a slit formed in the longitudinal direction of an electrode or a drain electrode is provided.

  According to one embodiment of the present invention, in a field effect transistor, it is possible to suppress occurrence of defects such as output characteristic deterioration and to obtain good reliability.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a plan view of the FET element of the present embodiment, and FIG. 2 is a cross-sectional view taken along line AA ′. As shown in the figure, an operation region 2 is formed on a substrate 1 made of a compound semiconductor such as GaAs, and a gate electrode 3 is formed on the operation region 2. Then, the source electrode 4 and the drain electrode 5 are alternately formed on the operation region 2 with the gate electrode 3 interposed therebetween. The gate electrode 3 is bonded to the outside through a gate wiring 6 and connected to a gate pad 7 for input / output. A source pad 8 is formed on the gate pad 7 side, and a drain pad 9 is formed on the opposite side of the operation region 2 with respect to the gate pad 7 and the source pad 8. Further, for example, Au single layer plating is used so that the source electrode 4 and the source pad 8 and the drain electrode 5 and the drain pad 9 are connected without contacting a passivation film (not shown) such as the gate wiring 6 or the SiN layer. An air bridge 10 is formed.

  The source electrode 4 and the drain electrode 5 are respectively ohmic electrodes 4a and 5a formed by stacking metals such as Pt / AuGe and pad electrodes 4b and 5b formed by stacking metals such as Au / Pt / Ti. It is composed of In these longitudinal directions, slits 11 for dividing the ohmic electrodes 4a and 5a and the pad electrodes 4b and 5b are formed.

  With such a structure, when stress is generated in the electrode due to thermal expansion and contraction of the Au layer due to temperature fluctuation, the stress in the electrode can be relaxed. And it becomes possible to suppress degradation of output characteristics and a passivation film, and to ensure the reliability of FET.

  This is evaluated by the output value fluctuation amount before and after the energization test when the width of the Au single layer plating (Au wiring) constituting the air bridge 10 greatly affects the reliability, that is, when the Au wiring width exceeds the threshold value. It was discovered from the new knowledge that the reliability to be deteriorated. It is thought that this is because the stress applied in the width direction due to thermal expansion and contraction of the Au layer due to temperature fluctuations affects the contact portion of the ohmic electrode due to the increase of the Au wiring width. It is done.

  The slit formed in this embodiment preferably has a width substantially equal to or larger than the gate electrode width and equal to or smaller than 1/3 of the width of the source electrode or drain electrode. If the width is substantially less than the gate electrode width, it is difficult to pattern the slit with a high yield, and if it exceeds 1/3 of the electrode width, the current operation is affected.

  In addition, in the source electrode and the drain electrode, it is preferable that the ohmic electrode is completely divided by a slit. Furthermore, it is preferable that a slit is formed in at least a part of the pad electrode, and it is more preferable that the pad electrode is also completely divided. Moreover, it is preferable that such a slit is provided in the center part of an electrode.

  Such a configuration can be applied to HEMT (High Electron Mobility Transistor), MESFET (Metal Semiconductor Field Effect Transistor), and MISFET (Metal Insulator Semiconductor).

  In addition, this invention is not limited to embodiment mentioned above. Various other modifications can be made without departing from the scope of the invention.

1 is a plan view of an FET element according to one embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Operation area, 3 ... Gate electrode, 4 ... Source electrode, 5 ... Drain electrode, 6 ... Gate wiring, 7 ... Gate pad, 8 ... Source pad, 9 ... Drain pad, 10 ... Air bridge, 11 …slit

Claims (5)

An operating region formed in the compound semiconductor substrate;
A gate electrode formed on the operating region;
A source electrode and a drain electrode alternately formed on the operation region with the gate electrode interposed therebetween;
A source pad and a drain pad for connection to an external circuit;
An air bridge connecting between the source electrode, the drain electrode, the source pad, and the drain pad;
A field effect transistor comprising a slit formed in a longitudinal direction of the source electrode or the drain electrode at least on the operation region side of the source electrode or the drain electrode.   2. The field effect transistor according to claim 1, wherein each of the source electrode and the drain electrode includes an ohmic electrode formed on the operation region, and the ohmic electrode is divided by the slit. .   The field effect transistor according to claim 2, wherein the source electrode or the drain electrode includes a pad electrode formed on the ohmic electrode, and the pad electrode is divided by the slit.   4. The field effect transistor according to claim 1, wherein the slit width is substantially equal to or larger than the gate electrode width and equal to or smaller than 1/3 of the width of the source electrode or the drain electrode.   The field effect transistor according to claim 1, wherein the air bridge includes an Au layer.

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