JP2009123932A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce influence exerted by a parasitic capacitance generating between a gate electrode and a drain electrode. <P>SOLUTION: The semiconductor device includes: a semiconductor substrate; a channel layer formed on a surface of the semiconductor substrate; the drain electrode formed on the channel layer; a source electrode formed away from the drain electrode on the channel layer; the gate electrode arranged between the drain electrode and the source electrode on the channel layer; a first insulating film formed on a surface of the drain electrode; a guard electrode formed in at least a part of on the first insulating film formed on an upper surface of the drain electrode which is a surface opposite to a joining face to the channel layer in the drain electrode; and a second insulating film formed so as to coat a surface of the guard electrode. This guard electrode is located between at least any one of at least a part of a metal wiring for connecting the gate electrodes arranged across the drain electrode with each other and at least a part of the gate electrode, and the drain electrode, and the guard electrode is electrically connected to the source electrode. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention particularly relates to a semiconductor device having a short gate length and operating at a high frequency.

  In the field effect transistor (FET) and high electron mobility transistor (HEMT), the gate length of the gate electrode should be shortened in order to realize operation at a high frequency of several tens of GHz or more. In particular, it is effective to make it 1 μm or less.

  However, the gate resistance increases as the gate length is reduced. Therefore, the high frequency characteristics of the semiconductor device are deteriorated.

  Therefore, a method of increasing the surface area of the gate electrode is used to reduce the gate resistance. For example, the shape of the gate electrode may be T-type, Y-type, mushroom shape, etc., and the electrode surface area higher than the Schottky junction may be increased while shortening the gate length at the Schottky junction. For example, Patent Document 1 describes a T-type gate electrode.

  However, this method has the following problems. First, since the thickness of the upper layer of the gate electrode is limited by the resist film thickness, there is a limit in reducing the gate resistance. Furthermore, as described in Patent Document 1, as the gate is miniaturized, the ratio (w / d) of the resist opening dimension w and the resist height d at the time of electrode formation becomes smaller. Therefore, it becomes easy to cause disconnection due to electron beam evaporation or the like when forming the gate electrode.

  Therefore, as a method for solving the above problem, Patent Document 2 discloses a method using an air bridge structure gate electrode. This is a structure provided so that the layer above the Schottky junction of the gate electrode extends in a direction parallel to the surface of the channel layer. Under the gate electrode of Patent Document 2, a source electrode and a drain electrode are disposed, and the gate electrode is formed so as to straddle the source electrode and the drain electrode. When the gate electrode has such a structure, the electrode surface area of the upper layer is larger than that of the Schottky junction in the gate electrode, and the gate resistance can be reduced.

  The gate electrode of the air bridge structure disclosed in Patent Document 2 will be further described with reference to FIG. FIG. 10 shows the structure of the FET described in Patent Document 2. The FET shown in FIG. 10 includes a semiconductor substrate 100 and a source electrode 1, a drain electrode 3, and a gate electrode 2 provided on the semiconductor substrate 100. The gate electrode 2 includes a narrow gate finger portion 302 disposed in the center between the source electrode 1 and the drain electrode 3, a pair of wings 304, and a double-sided air bridge portion 303 similar to a T-shape with sagging ends. The gate electrode 2 straddles the source electrode 1 and the drain electrode 3. The gate pad 301 to which the end of the air bridge portion of the gate electrode is joined is made of a conductive material and is formed on the substrate 100.

  As described above, in the FET of FIG. 10, the gate electrode has an air bridge structure so that the surface area of the upper layer of the gate electrode 2 is larger than that of the Schottky junction. For this reason, gate resistance can be reduced. Furthermore, the stress applied to the gate finger portion 302 can be reduced by the gate pad 301 receiving the gate electrode 2. For this reason, a gate electrode can be stably installed on a substrate.

JP 2004-55677 A JP 2001-102393 A

  However, the related art described above has the following problems.

  The gate resistance is reduced by increasing the electrode surface area above the Schottky junction in the gate electrode by using the gate electrode of the T-type, Y-type, mushroom shape, etc. described in Patent Documents 1 and 2 and the air bridge structure. The However, even if the gate electrode having the shape or structure described above is used, the obtained improvement effect of high-frequency gain deterioration is insufficient. This is because factors other than the gate resistance deteriorate the high frequency gain.

  If the gate electrode has the shape or structure described above, a part of the gate electrode is located in the vicinity of the upper layer of the drain electrode, and an insulating film exists between the two electrodes. Therefore, there is a parasitic capacitance (Cgd) between the drain electrode and the gate electrode. Arise. Further, parasitic capacitance (Cgs) is also generated between the gate electrode and the source electrode, and parasitic capacitance (Cds) is also generated between the drain electrode and the source electrode. Among these, the parasitic capacitance (Cgd) generated between the drain electrode and the gate electrode is particularly problematic in realizing a high frequency gain.

  An ideal relationship between frequency and high frequency gain will be described with reference to FIG. In FIG. 12, the horizontal axis represents frequency, and the vertical axis represents high frequency gain with respect to a predetermined frequency. Usually, in a high-frequency device, the high-frequency gain decreases as the frequency increases. The ideal relationship between the frequency and the high-frequency gain is a relationship in which the high-frequency gain always decreases with a constant slope as the frequency increases, as shown in FIG.

  However, in an actual high frequency device, various capacitances are generated between the electrodes, and the high frequency gain is lowered due to the influence of these capacitances.

  The high-frequency gain has a maximum stable gain (MSG) region and a maximum available gain (MAG) region. The MSG region refers to a range where the high frequency gain decreases with a certain slope as the frequency increases. On the other hand, the MAG region refers to a higher frequency range than the MSG region, and its beginning is the point at which the high frequency gain begins to drop sharply. In general, the high-frequency gain decreases at a rate of 3 dB / oct in the MSG region and 6 dB / oct in the MAG region. It can be said that the ideal relationship between the frequency and the high-frequency gain described above is that the gain decreases according to MSG. If not ideal, switch from MSG to MAG at a certain frequency.

  The effect of Cgd and Cgs on high frequency gain will be described with reference to FIG. Cgd in FIG. 13 indicates a high-frequency gain characteristic when Cgd is present. Cgs in FIG. 13 indicates the high frequency gain characteristic when Cgs is present. As shown in FIG. 13, Cgd degrades the high frequency gain in the range of MSG, and further lowers the frequency at which switching from MSG to MAG. On the other hand, Cgs has little effect on high-frequency gain in the MSG range, and only reduces the frequency at which MSG switches to MAG. Therefore, Cgd has an adverse effect on high frequency gain than Cgs. Note that Cds has little influence on the high-frequency gain and is not shown in the graph.

  As described above, when the gate electrode as described in Patent Documents 1 and 2 is used, the high-frequency gain deteriorates in the MSG region due to Cgd existing between the gate electrode and the air bridge portion of the gate electrode and the drain electrode. In addition, the frequency of switching from MSG to MAG decreases. Therefore, there is a problem that the high frequency characteristics of the semiconductor device cannot be sufficiently improved.

  In addition, the gate electrode of the air bridge structure described in Patent Document 2 has a further problem in realizing both high output and high integration. This is a problem that when the number of gate electrodes is increased in order to achieve high output, the area occupied by the gate electrode of the air bridge structure is large, so that the area of the entire transistor increases and high integration cannot be achieved.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent deterioration of high-frequency gain of a semiconductor device. In addition, a semiconductor device capable of high output and high integration is realized.

  In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor substrate, a channel layer provided on a surface of the semiconductor substrate, a drain electrode formed on the channel layer, and the channel layer on the channel layer. A source electrode formed apart from the drain electrode; a gate electrode disposed between the drain electrode and the source electrode on the channel layer; and a first insulation formed on a surface of the drain electrode. A film, a guard electrode provided on at least a part of the first insulating film, and a second insulating film formed so as to cover a surface of the guard electrode. Between at least one part of the metal wiring which connects the said gate electrodes arrange | positioned on both sides of a drain electrode, at least one of at least one part of the said gate electrode, and the said drain electrode Position, and the source electrode and the guard electrode is characterized by being electrically connected.

  In addition, the semiconductor device manufacturing method of the present invention includes a step of forming a source electrode on the surface of a semiconductor substrate, a step of forming a drain electrode, and a step of forming a first insulating film on the drain electrode. A step of forming a guard electrode on the first insulating film so as to cover at least a part of the drain electrode, a step of forming a gate electrode between the source electrode and the drain electrode, and the guard Forming a second insulating film on the electrode; and providing an opening in the second insulating film on the guard electrode to form a conductor that electrically connects the guard electrode and the source electrode. And a process.

  According to the present invention, a semiconductor device having an excellent high frequency gain is realized by reducing the influence of parasitic capacitance generated between the gate electrode and the drain electrode. In addition, a semiconductor device capable of high output and high integration is realized.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to FIGS.

  [First Embodiment] In the first embodiment, a semiconductor device according to the present invention will be described. The semiconductor device here is an FET formed on a semiconductor substrate.

  A cross-sectional structure of the FET of this embodiment is shown in FIG. The FET in this embodiment is formed on the semiconductor substrate 100. A channel layer 101 is formed on the substrate 100. A source electrode 1, a drain electrode 3, and a gate electrode 2 are formed on the channel layer 101. The source electrode 1 and the drain electrode 3 are separated from each other, and the gate electrode 2 is disposed between them. The insulating film 201 is formed on the surface of the drain electrode 3. The guard electrode 4 is provided on at least a part of the insulating film 201. The guard electrode 4 is located between at least a part of the gate electrode 2 and the drain electrode 3. Further, a second insulating film 202 is formed to cover the surface of the guard electrode 4 in order to prevent a short circuit between the guard electrode 4 and the gate electrode 2. The insulating film 201 is also formed on the channel layer 101 other than the portion where the source electrode 1, the drain electrode 3, and the gate electrode 2 are formed. Although not shown in the drawing, the guard electrode 4 is electrically connected to the source electrode 1.

  In the above-described structure, the guard electrode 4 is disposed between a part of the gate electrode 2 and the drain electrode 3. Therefore, the parasitic capacitance (Cgd) generated between the gate electrode 2 and the drain electrode 3 is the parasitic capacitance (Cgg ′) generated between the gate electrode 2 and the guard electrode 4 and between the guard electrode 4 and the drain electrode 3. It is replaced with the parasitic capacitance (Cg'd) generated in In addition, the guard electrode 4 is connected to the source electrode 1. Therefore, Cgg ′ can be replaced with Cgs and Cg′d can be replaced with Cds.

  Usually, parasitic capacitance degrades high frequency gain. As described above with reference to FIG. 13, Cgd degrades MSG and lowers the frequency at which MSG switches to MAG. In contrast, Cgs only lowers the frequency at which MSG switches to MAG. Cds has little effect on gain. Therefore, by converting Cgd to Cgs and Cds, it is possible to prevent the deterioration of MSG and to obtain good high frequency characteristics.

  In addition, in general, a high-frequency semiconductor device is designed so that its intended high frequency falls within the MSG range. Since the semiconductor device according to the present invention can prevent the MSG from being deteriorated as described above, a sufficient gain characteristic can be obtained in the operation at a high frequency.

  In the FET of this embodiment, the guard electrode 4 is provided on the insulating film 201 between the drain electrode 3 and the gate electrode 2 so as to cover at least a part of the drain electrode 3. In general, in order to realize high-frequency operation and high integration of the FET, it is desirable that the distance between the drain electrode 3 and the gate electrode 2 on the substrate is short. However, in this case, it is difficult in terms of manufacturing technology to install the guard electrode in a slight gap between both electrodes. In the FET of the present embodiment, by forming the guard electrode 4 so as to cover the drain electrode 3, the guard electrode 4 is connected to the drain electrode 3 and the gate electrode regardless of the distance between the drain electrode 3 and the gate electrode 2 on the substrate. Between the two.

  Furthermore, in the FET of the present embodiment, a T-type that is a part of the gate electrode 2 on the extension from the drain electrode 3 to the guard electrode 4 in a direction perpendicular to the junction surface between the channel layer 101 and the gate electrode 2. An overhanging portion of the gate electrode 2 exists. In this case, Cgd is generated between the upper surface of the drain electrode 3, which is the surface of the drain electrode 3 facing the bonding surface with the channel layer 101, and the protruding portion of the T-type gate electrode 2. Therefore, by forming the guard electrode on the upper surface of the drain electrode via the insulating film, it is possible to efficiently convert Cgd to Cgs and Cds, and to prevent the high frequency gain from being deteriorated.

  The semiconductor substrate used in the FET of this embodiment may be a general material used for a semiconductor substrate. For example, there is SiC widely used for III-V group semiconductor substrates such as GaAs and nitride semiconductors such as GaN. Si substrates are also commonly used.

The insulating film used in the FET of this embodiment may be a film made of a low dielectric material, and the material is not particularly limited. Examples of the material for the insulating film include SiN, SiO ₂ , and Al ₂ O _{3. It} is particularly preferable that the dielectric constant is low.

  If the insulating film is too thin, a parasitic capacitance (Cgs) generated between a gate electrode and a source electrode, which will be described later, increases, and as a result, the high-frequency gain is reduced. Therefore, for example, when a SiO2 film is used, it is desirable that the thickness be at least 50 nm, more preferably about 100 nm. Note that since the optimum thickness of the insulating film is determined by the dielectric constant, it varies depending on the insulating film material.

  The source electrode and the drain electrode used in the FET of the present embodiment may be any metal that exhibits ohmic properties with the material used for the substrate. The gate electrode may be a material used for the substrate and a metal exhibiting Schottky properties. For example, when a nitride semiconductor is used as the substrate, a Ti / Al alloy can be used as the drain electrode and the source electrode, and nickel and gold can be used as the gate electrode. In FIG. 1, the shape of the source electrode 1 and the drain electrode 3 is rectangular, but the shape is not limited to these, and other shapes may be used.

  The shape of the gate electrode 2 is T-shaped in FIG. 1, but the shape is not limited to this, and a part of the gate electrode is parallel to the channel layer, such as a protruding portion of the T-shaped gate electrode. It is sufficient that the guard electrode 4 exists between the gate electrode 2 and the drain electrode 3. Therefore, the shape of the gate electrode in the cross section including the gate electrode and the drain electrode in the direction perpendicular to the joint surface between the channel layer and the gate electrode may be a Y-type, mushroom shape, air bridge structure, or the like. By using the gate electrode having the shape or structure as described above, the surface area of the upper layer of the gate electrode is increased, so that a reduction in gate resistance can be expected.

  In FIG. 1, there is only one source electrode 1, one drain electrode 3, and one gate electrode 2, but there may be a plurality of electrodes as long as the gate electrode is disposed between the source electrode and the drain electrode.

  The distance between the gate electrode and the drain electrode and the distance between the gate electrode and the source electrode on the substrate vary depending on the intended frequency and operating voltage. For example, when used at a high frequency of 30 GHz or more, each interval is desirably 1 μm or less.

  In FIG. 1, the gate electrode 2 is in contact with the insulating film 202, but the gate electrode 2 and the insulating film 202 do not have to be in contact, and air or the like may exist between them. By interposing air between them, the parasitic capacitance (Cg′g) generated between the gate electrode and the guard electrode can be reduced.

  The guard electrode used in the FET of this embodiment may be made of a general conductive material. For example, titanium and gold can be used for the guard electrode.

  In FIG. 1 representing the first embodiment, the guard electrode 4 covers the entire upper surface of the drain electrode 3, which is the surface facing the bonding surface with the channel layer 101, of the drain electrode 3 with the insulating film 201 interposed therebetween. ing. Since the guard electrode plays a role of replacing Cgd with Cgs and Cds, it is provided in a region where Cgd is generated. Cgd is usually generated at a location between the gate electrode and the drain electrode. Therefore, if Cgd occurs between the gate electrode and the drain electrode, it is possible to replace Cgd with Cgs and Cds even when the guard electrode is smaller than the drain electrode. is there. However, in order to replace more Cgd with Cgs and Cds, it is desirable to cover the entire upper surface of the drain electrode with a guard electrode as shown in FIG.

  Although one guard electrode is provided in FIG. 1, the number is not limited to one. A plurality of guard electrodes may be provided between the gate electrode and the drain electrode.

  The guard electrode need only be thick enough to replace Cgd with Cgs and Cds, and the thickness is not particularly limited.

  It is also effective for the guard electrode to cover the surface other than the junction surface between the upper surface of the drain electrode and the channel layer of the drain electrode through an insulating film. For example, in the case of FIG. 1, the side surface closer to the gate electrode 2 among the side surfaces of the drain electrode 3, which is a surface other than the junction surface between the upper surface of the drain electrode 3 and the channel layer 101 of the drain electrode 3, is the gate electrode. 2 is facing. Therefore, Cgd is also generated between the side surface of the drain electrode 3 and the gate electrode 2. Therefore, particularly when the guard electrode is thick, the influence of Cgd can be reduced by covering the side surface of the drain electrode 3 with the guard electrode via the insulating film 201.

  The guard electrode 4 may extend to the top of the insulating film 201 formed between the drain electrode 3 and the gate electrode 2. By extending the guard electrode 4 in this way, the intrinsic capacitance generated between the gate electrode 2 and the drain electrode 3 in the FET can be reduced, and deterioration of the MSG can be prevented. In addition, the breakdown voltage between the gate electrode 2 and the drain electrode 3 can be increased. However, it is desirable not to connect the guard electrode and the gate electrode.

  The source electrode 1 and the guard electrode 4 may be electrically connected, and the conductor material used for the connection may be a general metal through which a current flows. Examples of the connection method include a method of providing a through hole in an insulating film covering the guard electrode 4 and connecting with a conductor having an air bridge structure. In this case, an air gap exists between the conductor and the gate electrode.

  In the present embodiment, the present invention has been described using the FET. However, in the present invention, the semiconductor device that can obtain the effects of the present invention is not limited to this, and any of various semiconductors such as HEMT may be used.

  Next, a method for manufacturing the FET shown in FIG. 1 will be described with reference to FIGS. 2 (a) to 2 (e). 2A to 2E are cross-sectional views showing the first step, the second step, the third step, the fourth step, and the fifth step of the semiconductor device manufacturing method in the order of steps. .

  In the first step, as shown in FIG. 2A, desired patterning is performed using a photoresist on the surface of the channel layer 101 including the buffer layer formed on the semiconductor substrate 100. Then, an ohmic junction source electrode 1 and drain electrode 3 are formed on the surface of the channel layer 101 using an electron beam evaporation method or the like. In this embodiment, Ti / Al-based metal is used as the electrode component.

  In the second step, as shown in FIG. 2B, an insulating film 201 is formed on the drain electrode 3, the channel layer 102, and the source electrode 1 using a plasma CVD method or the like. The insulating film 201 may be formed on at least the drain electrode 3. In this embodiment, the insulating film 201 is SiN and the film thickness is 200 nm.

  In the third step, as shown in FIG. 2C, patterning is performed using a photoresist on the surface of the insulating film 201, and at least a part of the drain electrode is formed on the insulating film 201 using an electron beam evaporation method or the like. A guard electrode 4 is formed on the portion covering the. In the present embodiment, Ti / Al-based metal is used as a component of the guard electrode 4.

  In the fourth step, as shown in FIG. 2D, an insulating film 202 is further formed on the insulating film 201 and the guard electrode 4 by using a plasma CVD method or the like. The insulating film 202 may be formed on at least the guard electrode 4. In the present embodiment, the insulating film 202 is, for example, SiN, and the film thickness is 60 nm.

  In the fifth step, as shown in FIG. 2E, an opening is formed in the insulating film 202 on the surface of the insulating film 202 by using electron beam exposure and etching techniques. Further, the gate electrode 2 is formed using an electron beam evaporation method or the like. In this embodiment, Ni / Au metal is used as a component of the gate electrode 2. Patterning is performed using a photoresist or the like.

  In the sixth step, the insulating film 201 and the insulating film 202 on the source electrode 1 are removed by wet or dry etching. Further, the insulating film 202 on the guard electrode 4 is removed by wet or dry etching to provide a through hole. Thereafter, a conductor connecting the guard electrode 4 and the source electrode 1 is formed. Through the series of steps, the semiconductor device shown in FIG. 1 is completed.

  In addition, although the manufacturing method of FET in this embodiment was demonstrated using FIG. 1 and FIG. 2 (a)-(e), a manufacturing method is not limited to this. In the present invention, as long as the guard electrode 4 is formed on the drain electrode 3 via the insulating film 201 so as to cover at least a part of the drain electrode 3 between the drain electrode 3 and the gate electrode 2. Each process may be performed by other methods.

  As described above, in the FET according to the first embodiment, as shown in FIG. 1, the insulating film covers at least part of the drain electrode 3 between at least part of the gate electrode 2 and the drain electrode 3. By forming the guard electrode 4 provided on 201, Cgd can be replaced with Cgs and Cds. Therefore, it is possible to suppress the deterioration of the high frequency gain.

  [Second Embodiment] In the second embodiment, a semiconductor device according to the present invention, characterized in that the distance between the guard electrode and the gate electrode is larger than the distance between the guard electrode and the drain electrode, will be described. Since this embodiment is an application of the first embodiment, the description of the same points as the first embodiment will be omitted.

  Differences between the present embodiment and the first embodiment will be described with reference to FIG. FIG. 3 shows a cross-sectional view of the FET of this embodiment.

  In the FET in this embodiment, the second insulating film 202 is thicker than the first insulating film 201. Therefore, the distance between the guard electrode 4 and the gate electrode 2 is larger than the distance between the guard electrode 4 and the drain electrode 3.

  In general, the parasitic capacitance generated between the electrodes decreases as the distance between the electrodes increases. Therefore, by increasing the distance between the guard electrode 4 and the gate electrode 2, Cgg ′ (Cgs) is reduced, and as a result, a good high-frequency gain can be obtained.

  Here, the distance between the guard electrode and the gate electrode and the distance between the guard electrode and the drain electrode refer to the minimum distance between the electrodes. The minimum interval refers to the interval that is the shortest of the intervals that start from every point on one electrode and extend from the other electrode.

  For example, in the case of FIG. 3, the distance between the guard electrode 4 and the gate electrode 2 is equal to the thickness of the second insulating film 202.

  [Third Embodiment] In a third embodiment, a semiconductor device according to the present invention having two gate electrodes and the gate electrodes connected to each other by metal wiring will be described. Since this embodiment is an application of the first embodiment, the description of the same points as the first embodiment will be omitted.

  Differences between the present embodiment and the first embodiment will be described with reference to FIGS. FIG. 4 shows a cross-sectional view of the FET of this embodiment. FIG. 5 is a plan view of the FET shown in FIG. FIG. 4 is a cross-sectional view of the FET of this embodiment taken along the dotted line shown in FIG.

  A channel layer 101 including a buffer layer region made of a semiconductor layer is formed on the substrate 100 in the present embodiment. An electron supply layer 102 is formed on the channel layer 101. On the electron supply layer 102, two source electrodes 1, one drain electrode 3, and a gate electrode 2 are formed. The gate electrodes 2 arranged with the drain electrode 3 interposed therebetween are connected by a metal wiring 5. The guard electrode 4 is located between at least a part of the metal wiring 5 and the drain electrode 3.

  In the FET in the present embodiment, the guard electrode 5 is formed between the drain electrode 3 and the metal wiring 5 so as to cover at least a part of the drain electrode on the insulating film 201. Since the metal wiring 5 connects the gate electrodes 2 to each other, a parasitic capacitance Cgd is generated between the metal wiring 5 and the drain electrode 3. By installing the guard electrode 5 between the drain electrode 3 and the metal wiring 5, Cgd can be replaced with Cgs and Cds, and as a result, deterioration of the high frequency gain can be suppressed.

  As shown in FIGS. 4 and 5, the FET in this embodiment has two gate electrodes 2. Furthermore, as shown in FIG. 4, the source electrode 1, the gate electrode 2, and the drain electrode 3 are arranged in parallel. By using such a structure, high output can be achieved.

  Note that the guard electrode may be disposed between the gate electrode and the drain electrode connected by metal wiring.

  In the FET in the present embodiment, the gate electrodes 2 are electrically connected to each other by the metal wiring 5. By connecting the gate electrodes to each other with a metal wiring, the operation of each gate electrode can be made uniform, so that the output of the semiconductor device and the gain can be increased.

  The number of gate electrodes is not particularly limited to two. Since the output of the semiconductor device increases according to the number of gate electrodes, the number of gate electrodes may be increased in order to obtain a higher output. However, the gate electrode is preferably disposed between the source electrode and the drain electrode.

  The number of source electrodes and drain electrodes is not limited as long as the gate electrode is disposed between the source electrode and the drain electrode. For example, in the case of the FET in this embodiment, as shown in FIG. 4, there are two source electrodes 1, one drain electrode 3, and two gate electrodes 2. The drain electrode 3 is sandwiched between two gate electrodes 2. Further, the two gate electrodes 2 are sandwiched between the two source electrodes 1. With such a structure, the number of source electrodes, drain electrodes, and gate electrodes is different, but an arrangement in which the gate electrode is sandwiched between the source electrode and the drain electrode can be realized.

  In the FET according to the present embodiment, as shown in FIG. 5, there are four metal wirings 5 that connect the gate electrodes 2 to each other, but the number is not limited to four. If the gate electrodes are electrically connected, the operation of each gate electrode is made uniform, so the number of metal wirings may be one.

  The width of the metal wiring 5 that is the length in the longitudinal direction of the gate electrode of the metal wiring 5 shown in FIG. By making the width of the metal wiring 5 wider, the surface area of the upper layer than the Schottky junction of the gate electrode 2 can be increased, and the gate resistance can be reduced.

  The material of the metal wiring 5 should just be a general conductor through which an electric current flows, and the material is not specifically limited.

  The FET in this embodiment uses a semiconductor substrate composed of a plurality of layers. An example of a substrate composed of a plurality of layers is a substrate made of a group III-V nitride semiconductor composed of a GaN buffer layer / channel layer and an AlGaN electron supply layer. As described above, by forming a plurality of layers, an FET having excellent characteristics such as high speed and high frequency can be produced.

  The present invention is also applicable to a gate electrode having an air bridge structure disclosed in Patent Document 2. By applying the present invention, it is possible to reduce deterioration of high frequency gain in a semiconductor device adopting the structure described in Patent Document 2.

  When the semiconductor device according to the present invention is used, high output and integration in a small space can be easily realized. In FIG. 10 showing the structure of Patent Document 2, a gate pad 301 connected to the air bridge end of the gate electrode 2 is disposed next to the source electrode 1 and the drain electrode 3. When the number of gate electrodes is increased with this structure, the semiconductor devices in FIG. 10 are arranged in the electrode width direction, and the semiconductor devices are enlarged. On the other hand, in the present invention, as shown in FIG. 4, each gate electrode 2 is arranged next to the source electrode 1 and the drain electrode 3, so that the source electrode, the drain electrode and the gate electrode are efficiently provided in a limited space. Can be arranged.

  Next, a method of manufacturing the FET shown in FIG. 4 will be described with reference to FIGS. 6 (a) to 6 (e). 6A to 6E are cross-sectional views showing the first step, the second step, the third step, the fourth step, and the fifth step of the semiconductor device manufacturing method described above in the order of steps. .

  In the first step, as shown in FIG. 6A, a photoresist is used on the surface of a multilayer formed by a channel layer 101 including a buffer layer and an electron supply layer 102 formed on the semiconductor substrate 100. Desired patterning is performed. Then, the source electrode 1 and the drain electrode 3 are formed on the surface of the multilayer using an electron beam evaporation method or the like. In this embodiment, Ti / Al-based metal is used as the electrode component.

  In the second step, as shown in FIG. 6B, an insulating film 201 is formed on the drain electrode 3, the electron supply layer 102, and the source electrode 1 using a plasma CVD method or the like. The insulating film 201 may be formed on at least the drain electrode 3. In this embodiment, the insulating film 201 is silicon nitride (SiN), and the film thickness is 200 nm.

  In the third step, as shown in FIG. 6C, at least a part of the drain electrode is formed on the insulating film 201 by patterning using a photoresist on the surface of the insulating film 201 and using an electron beam evaporation method or the like. It forms in the part which covers. In the present embodiment, Ti / Al-based metal is used as a component of the guard electrode 4. Patterning is performed using a photoresist or the like.

  In the fourth step, as shown in FIG. 6D, an opening is formed in the insulating film on the surface of the insulating film 201 using electron beam exposure and etching techniques. Further, the gate electrode 2 is formed using an electron beam evaporation method or the like. In this embodiment, Ni / Au metal is used as a component of the gate electrode 2. Patterning is performed using a photoresist or the like.

  In the fifth step, as shown in FIG. 6E, an insulating film 202 is further formed on the guard electrode 4, the insulating film 201, and the gate electrode 2 by using a plasma CVD method or the like. In the present embodiment, the insulating film 202 is, for example, SiN, and the film thickness is 60 nm. The insulating film 202 may be formed on at least the guard electrode 4.

  In the sixth step, the insulating film 201 and the insulating film 202 on the source electrode 1 and the insulating film 202 on the gate electrode 2 are removed by wet or dry etching. Thereafter, metal wiring 5 for connecting the gate electrodes 2 to each other is formed on the insulating film 202 using sputtering and plating techniques. Further, the insulating film 202 on the guard electrode 4 is removed by wet or dry etching to provide a through hole. Thereafter, a conductor connecting the guard electrode 4 and the source electrode 1 is formed. The series of steps completes the semiconductor device shown in FIG.

  In addition, although the manufacturing method of FET in this embodiment was demonstrated using FIG. 4 and FIG. 6 (a)-(e), a manufacturing method is not limited to this. In the present invention, the guard electrode 4 is formed on the drain electrode 3 via the insulating film 201 so as to cover at least part of the drain electrode 3 between the metal wiring 5 connecting the gate electrodes 2 and the drain electrode 3. As long as it is formed, each process may be performed by other methods.

  As described above, in the FET according to the third embodiment, the drain electrode 3 is covered on the drain electrode 3 so as to cover at least a part of the drain electrode 3 between the metal wiring 5 and the drain electrode 3 connecting the gate electrodes 2 to each other. By forming the guard electrode 4 through the insulating film 201, Cgd can be replaced with Cgs and Cds. Therefore, it is possible to suppress the deterioration of the high frequency gain.

  [Fourth Embodiment] In a fourth embodiment, a semiconductor device according to the present invention using an insulating film using a low dielectric constant material will be described. Since the present embodiment is an application of the first embodiment and the third embodiment, the description of the same points as the first and third embodiments will be omitted.

  Differences between this embodiment and the first and third embodiments will be described with reference to FIG. FIG. 7 shows a cross-sectional view of the FET of this embodiment.

  In the FET in this embodiment, an insulating film 203 having a dielectric constant lower than that of the insulating film 201 is formed on the insulating film 201. The guard electrode 4 is formed on the insulating film 203 so as to cover at least a part of the drain electrode. Further, an insulating film 204 made of the same material as the insulating film 203 covers the surface of the guard electrode 4.

  In the FET according to this embodiment, the drain electrode 3 and the guard electrode 4 are covered with an insulating film 203 and an insulating film 204 using a dielectric constant material lower than that of the insulating film 201. Thereby, the parasitic capacitance (Cgs) generated between the gate electrode 2 and the source electrode 1 (guard electrode 4) can be reduced. Therefore, compared with the semiconductor device of the third embodiment shown in FIG. 4, the frequency at which the switching from MSG to MAG is extended, and deterioration of the high frequency gain is further suppressed.

  The insulating film 203 and the insulating film 204 preferably have a lower dielectric constant than the insulating film 201. For example, SiO 2 can be used as the insulating film 203 and the insulating film 204, and SiN can be used as the insulating film 201.

  Next, the manufacturing method of the FET in this embodiment will be described with reference to FIG. Since the present embodiment is an application of the third embodiment, only the second step and the fifth step that are different from the FET manufacturing method in the third embodiment will be described.

  In the second step of the FET manufacturing method in the present embodiment, the insulating film 201 is formed on the multilayer surface using a plasma CVD method or the like. Then, the insulating film 203 is formed over the insulating film 201 again using a plasma CVD method or the like. For example, SiN is used as the insulating film 201 to a thickness of 20 nm, and SiO2 is used as the insulating film 203 to a thickness of 100 nm.

In the fifth step of the FET manufacturing method in this embodiment, the insulating film 204 is formed on the insulating film and the gate electrode 2 using the plasma CVD method or the like. Here, the insulating film 204 is formed using a low dielectric constant material lower than that of the insulating film 201 as in the case of the insulating film 203. For example, when the insulating film 204 is SiO ₂ , the film thickness is 100 nm.

  In addition, although the 3rd process and the 5th process of the manufacturing method of FET in this embodiment were demonstrated above, a manufacturing method is not limited to this.

  As described above, in the FET according to this embodiment, the drain electrode 3 and the guard electrode 4 are covered with the insulating film 203 and the insulating film 204 using a dielectric constant material lower than that of the insulating film 201. Thereby, the parasitic capacitance (Cgs) generated between the gate electrode 2 and the source electrode 1 (guard electrode 4) can be reduced. Therefore, it is possible to suppress the deterioration of the high frequency gain.

  [Fifth Embodiment] In the fifth embodiment, a semiconductor device according to the present invention in which the metal wiring for connecting the gate electrodes to each other is in the form of an air bridge will be described. Since the present embodiment is an application of the first embodiment and the third embodiment, the description of the same points as the first and third embodiments will be omitted.

  Differences between the present embodiment and the first and third embodiments will be described with reference to FIG. FIG. 8 shows a cross-sectional view of the FET of this embodiment.

  In the FET according to the present embodiment, the gate electrodes 2 are connected to each other by an air bridge-shaped metal wiring 5, and a gap exists between the metal wiring 5 and the insulating film 202. Thereby, the parasitic capacitance (Cgs) generated between the metal wiring 5 and the source electrode 1 (guard electrode 4) can be reduced. Therefore, compared with the semiconductor device of the third embodiment shown in FIG. 4, the frequency at which the switching from MSG to MAG is extended, and deterioration of the high frequency gain is further suppressed.

  Next, the manufacturing method of the FET in this embodiment will be described with reference to FIG. Since the present embodiment is an application of the third embodiment, only the sixth step that is different from the FET manufacturing method in the third embodiment will be described.

  In the sixth step of the FET manufacturing method in the fifth embodiment, the insulating film 201 and the insulating film 202 on the source electrode 1 and the insulating film 202 on the gate electrode 2 are removed by wet or dry etching or the like. Next, a protective pattern having a shape covering the guard electrode 4 and the drain electrode 3 positioned between the gate electrodes 2 is formed using a resist. Here, the protective pattern is formed so as to expose the air bridge-shaped metal wiring 5 that connects the gate electrodes 2 to each other. Thereafter, a metal wiring 5 is formed on the gate electrode 2 by using sputtering, plating technology, and milling technology. Then, the metal wiring 5 having an air bridge structure is formed by selectively etching away the protective pattern using an ashing process using ozone plasma. Further, the insulating film 202 on the guard electrode 4 is removed by wet or dry etching to provide a through hole. Thereafter, a conductor connecting the guard electrode 4 and the source electrode 1 is formed. Through the series of steps, the semiconductor device shown in FIG. 8 is completed.

  Although the sixth step of the FET manufacturing method in the present embodiment has been described above, the manufacturing method is not limited to this. In the sixth step of the FET manufacturing method in this embodiment, if the metal wiring 5 connecting the gate electrodes 2 can be formed in an air bridge shape, this step is performed by another method. Also good.

  As described above, in the FET according to this embodiment, the gate electrodes 2 are connected to each other using the air bridge-shaped metal wiring 5. Thereby, the parasitic capacitance (Cgs) generated between the metal wiring 5 and the source electrode 1 (guard electrode 4) can be reduced. Therefore, it is possible to suppress the deterioration of the high frequency gain.

  [Sixth Embodiment] A semiconductor device according to a sixth embodiment will be described. Since the present embodiment is an application of the first embodiment and the third embodiment, the description of the same points as the first and third embodiments will be omitted.

  Differences between this embodiment and the first and third embodiments will be described with reference to FIG. FIG. 9 shows a plan view of the FET of this embodiment.

  In the FET in the present embodiment, a conductor connecting the source electrode 1 and the guard electrode 4 is sandwiched between metal wirings 5. With such a structure, the gate finger length, which is the length in the longitudinal direction of the gate electrode 5 shown in FIG. 9, is maintained at the same length as the gate finger length of the FET shown in FIG. Smaller than the FET shown.

  [Example 1] In this example, the high-frequency gain characteristics of the FET according to the present invention were compared with the high-frequency gain characteristics of other FETs.

  The FET according to the present invention used in this example was the one shown in FIGS. 4 and 5 and having 10 gate electrodes. In this embodiment, SiC as the substrate 100, GaN as the channel layer 101, AlGaN as the electron supply layer 102, Ti / Al metal material as the drain electrode 3 and the source electrode 1, Ni / Au as the gate electrode 2, Ti as a guard electrode / Au, Au as the metal wiring 5, SiN as the insulating film 201, and SiN as the insulating film 202 are used. The gate length was 0.25 μm, and the gate finger length was 75 μm.

  As FETs other than the present invention, an FET provided with one T-type gate electrode (Comparative Example 1) and an FET provided with two gate electrodes having an air bridge structure (Comparative Example 2) were used. Note that both Comparative Example 1 and Comparative Example 2 are FETs having no guard electrode.

  The graph of FIG. 11 shows the high frequency gain characteristics in each FET. The horizontal axis of the graph represents frequency, and the vertical axis represents high-frequency gain with respect to a predetermined frequency. In the graph, the present invention represents the high frequency gain characteristic of the FET of the present invention. Comparative Example 1 and Comparative Example 2 represent the high frequency gain characteristics of the FET of Comparative Example 1 and the FET of Comparative Example 2, respectively.

  As shown in FIG. 11, when the high frequency gain characteristics of the FET according to the present invention, the FET according to Comparative Example 1, and the FET according to Comparative Example 2 were compared, the high frequency gain characteristics of the FET according to the present invention were the most excellent. In the high-frequency gain characteristic of Comparative Example 1, the frequency at which the switching from MSG to MAG is lower than that of the high-frequency gain characteristic of the present invention. In the high-frequency gain characteristic of Comparative Example 2, the high-frequency gain deteriorated in the MSG region and the frequency at which switching from MSG to MAG was lower than the high-frequency gain characteristic of the present invention.

  As described above, the FET according to the present invention can realize high-frequency gain characteristics superior to those of a FET having a T-type gate electrode and a FET having an air bridge structure gate electrode.

1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to a first embodiment. It is a figure which shows typically the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device which concerns on 3rd Embodiment. It is a top view which shows typically the structure of the semiconductor device which concerns on 3rd Embodiment. It is a figure which shows typically the manufacturing process of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device which concerns on 5th Embodiment. It is a top view which shows typically the structure of the semiconductor device which concerns on 6th Embodiment. 10 is a schematic diagram of a semiconductor device including a gate electrode having an air bridge structure disclosed in Patent Document 2. FIG. 4 is a graph showing high-frequency gain characteristics of a FET, a FET having a T-type gate structure, and a FET having an air bridge type gate electrode in the present invention. It is a graph showing an ideal high frequency gain characteristic. 3 is a graph showing a high frequency gain characteristic when Cgd is present and a high frequency gain characteristic when Cgs is present.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Source electrode 2 Gate electrode 3 Drain electrode 4 Guard electrode 5 Metal wiring 100 Substrate 101 Channel layer 102 Electron supply layer 201 Insulating film 202 Insulating film 203 Insulating film 204 Insulating film 301 Gate pad 302 Gate finger part 303 Air bridge part 304 Wing

Claims (18)

A semiconductor substrate;
A channel layer provided on a surface of the semiconductor substrate;
A drain electrode formed on the channel layer;
A source electrode formed on the channel layer and spaced apart from the drain electrode;
A gate electrode disposed between the drain electrode and the source electrode on the channel layer;
A first insulating film formed on the surface of the drain electrode;
A guard electrode provided on at least a part of the first insulating film formed on an upper surface of the drain electrode, which is a surface of the drain electrode facing a bonding surface with the channel layer;
A second insulating film formed so as to cover the surface of the guard electrode,
The guard electrode is positioned between at least one of the metal wiring that connects the gate electrodes disposed between the drain electrodes, at least one of the gate electrodes, and the drain electrode. And
The semiconductor device, wherein the guard electrode and the source electrode are electrically connected.
2. The semiconductor device according to claim 1, wherein a minimum interval between the guard electrode and the gate electrode or the metal wiring is larger than a minimum interval between the guard electrode and the drain electrode.
3. The semiconductor device according to claim 1, wherein a plurality of the gate electrodes are present, at least one of the drain electrodes and the source electrodes is present, and at least one of the other is present.
4. The semiconductor device according to claim 1, wherein a gap exists between the gate electrode or the metal wiring and the second insulating film. 5.
5. The semiconductor device according to claim 1, wherein the guard electrode covers the entire upper surface of the drain electrode through the first insulating film. 6.
6. The guard electrode covers an upper surface of the drain electrode and a surface of the drain electrode other than a bonding surface with the channel layer, through the first insulating film. The semiconductor device as described in any one.
The first insulating film extends over the channel layer between the drain electrode and the gate electrode, and the guard electrode extends between the drain electrode and the gate electrode. The semiconductor device according to claim 1, wherein the semiconductor device extends to above the insulating film.
The semiconductor device according to claim 1, comprising a plurality of the metal wirings that connect the gate electrodes.
The shape of the gate electrode in a cross section including the gate electrode and the drain electrode in a direction perpendicular to the joint surface between the channel layer and the gate electrode is a T-type, a Y-type, or a mushroom shape, The semiconductor device according to any one of claims 1 to 8.
A part of the gate electrode or the metal wiring is present on an extension from the drain electrode to the guard electrode in a direction perpendicular to a bonding surface between the channel layer and the gate electrode. The semiconductor device according to claim 1.
11. The semiconductor device according to claim 1, wherein a distance between the gate electrode and the drain electrode on the semiconductor substrate is 1 μm or less.
The semiconductor device according to claim 1, wherein the first insulating film is made of SiO ₂ .
The semiconductor device according to claim 1, wherein the semiconductor substrate includes a plurality of layers.
The semiconductor device according to claim 1, wherein the guard electrode and the source electrode are connected by a conductor, and a gap exists between the conductor and the gate electrode.
The semiconductor device according to claim 1, wherein the conductor is disposed between the plurality of metal wirings.
There are two source electrodes,
There is one drain electrode;
There are two gate electrodes,
The drain electrode is sandwiched between two gate electrodes;
The two gate electrodes are sandwiched between the two source electrodes;
16. The semiconductor device according to claim 1, wherein the two gate electrodes are connected by the metal wiring.
On the surface of the semiconductor substrate,
Forming a source electrode;
Forming a drain electrode;
Forming a first insulating film on the drain electrode;
Forming a guard electrode on a portion covering at least a part of the drain electrode on the first insulating film;
Forming a gate electrode between the source electrode and the drain electrode;
Forming a second insulating film on the guard electrode;
Providing an opening in the second insulating film on the guard electrode, and forming a conductor that electrically connects the guard electrode and the source electrode;
A method for manufacturing a semiconductor device, comprising:
The method of manufacturing a semiconductor device according to claim 17, further comprising: forming a metal wiring that connects the gate electrodes.

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